Dynamic Shift Registers - Bitsavers - Trailing-Edge

performance characteristicsPower Dissipation vs Maximum Frequency1000~.§ 100z0;:::.... en...10cII:~0...~TAI='~5'CI==voo = -IOVr---v. = -16V -- M~402v.:l~M~06 ~./~MM400=Minimum Operating Frequency10K5K2KN IKe>.... 500zw 200:::>Clw 100:l:50,I'GUARANTEED ~ ~V /TYPICALi/ ./ Voo = -IOV_/ ./ v., = v'" = -16V200.1 10./10 100 1000 -60 -20 20 60 100 140OPERATING FREQUENCY (kHz!TEMPERATURE ('C)c.§I­ZwII:II::::>....I­ :::>I!=:::>oOutput Sink/Source CurrentIr-'--r-,~r-'--r-'--'4~-+--+o 1t:j~::±:±:::::I::=:b::~o -I -2 -3 -4 -5 -6 -1 -8OUTPUT VOL TAGE (VOLTS) (BELOW V •• )3:3:~o.......3:3:U'IotJ)CD.._.CDenPower Dissipation/Bit vs. Supply Voltage Power Dissipation/Bit vs. Clock Amplitude Clock Timing,Direct-Coupled TTL or DTLIJIJ~ 1.4 1--+--I-4--L-I--:: .....""l-i.§1.2I-~ 1.0 I--::r""""t--'o~ 0 .• 1--+--b-4'iii 0.6 1-"''-I---11:...'''I'''-t-+--+-+--lc~ 0.4 1"""-f---1I-+--t-+--+-+--l~ 0.2 I--+-,I-+-'t=--r--t-+--t0'---'--'---'--'---'--'---'---1-I -9 -10 -11Voo (VOLTS)-12~ 1.4.§1.2I-.. D~Z 1.00;:::.•...iii 0.6CII:w 0.4~00.2...0-12 -14 -16 -18 -20CLOCK AMPLITUDE (VOL TS)w..I-'"....0>I-... :::>!!:I-..05.04.03.02.0o ns 200 ns 400 ns 0.6 ~s 0 .• ~s I ~sCLOCK , WIDTHClock Amplitude VI' V2vs. Maximum FrequencyFRED.4.5 - IMHz! ., ., •• UNITS r-:C 4.0 - 1.0 0.4 0.2 0.1 "' f-~ 1.5 0.3 0.2 0.05 "'~ 3.5 - 2.0 0.2 0.2 0.05 "' r-Z 3.0 '- 2.5 0.15 0.15 0.05", f-~ IJ...:::: 2.5 1--+-+-+-t-lI-t-:::; ...."f!='-1--l:l: .........,- I2.0 I-+--+-+",""*""'f'-+-I[-'.II--I--I1.5 1-, ~-+".,"""'/""-+-+-t-t-Voo=-IOV1.0 F""'""--+--II-+--+TEMPERATURE: 25'CFANOUT: ONE REGISTER INPUT LOAD~u ~u ~~ ~u ~~ ~~V.,. V., (VOLTS)~.§l-ii;Z0;:::~iiicII:W~0...Maximum Package Power DissipationBOO400200o-25......... I'-.... .........~25 15 125TEMPERATURE rC)Power Dissipation/Bit vs. TemperatureI .•1.4~.§1.2I-~z 1.00;::: D ••...iii 0.6CII:w 0.4~00.2...-15 -25 0 25 15 125TEMPERATURE ('C)Note: All typical performance data is gathered with pw = 0.4 f.l; 2pw = 0.2 f.lS; d = 0.1 f.ls; f = 1 MHz; except as otherwise noted.operationEach bit of delay shown in the circuit schematic consistsof two inverters T1 and T4 accompanied by clocked loadresistors T2 and T5 and two coupling devices T3 and T6.The circuit functions as follows: When 2 goes negative(one state) the coupling unit TA and the load resistorT2 are clocked ON allowing information at the input tobe transferred to node A turning T1 ON or OFF dependingon the state of the input. For example, if a negativepotential (near -Voo level) is transferred from the inputto the gate to source capacitance at node A, then T1-Vooturns ON allowing node F to be at --2-' When 2 returnsto its zero state (ground level) T2 turns OFF allowingnode F to discharge to zero volts. When 1 goes negative(one state) the coupling unit T3 and the load resistorT5 are clocked ON allowing information at node Fto be transferred to node B. T4 is held OFF if node F wasat ground potential and is turned ON if node F had beenat -Voo potential. Continuing the example above, T4 isheld OFF and node G is at -Voo since T5 is ON during1 clock pulse. When 1 returns to its zero state, node Gmaintains a -Voo voltage level. This voltage level ismaintained at node G until the 2 clock appears. Thebit delay demonstrated in this example is repeatedthrough each half of the dual register.timing diagramNOoEANODE B -",__...INODE CDATAOUTPUTN BIT DELAYII~11