Dynamic Shift Registers - Bitsavers - Trailing-Edge

Dynamic Shift Registers*MM400/MM500 series dynamic shift registersgeneral descriptionThe National Semiconductor line of dynamic shiftregisters are built on a single silicon chip utilizingMOS P channel enhancement mode transistors.Designed to operate over a wide frequency spec·trum, these devices can be used in any sequentialdigital system that employs a two phase clockingsystem. The low threshold transistors used permitoperation with a V DO supply voltage of -1 OV anda -16V clock amplitude to obtain these devicefeatures:• Direct DTL or TTL compatibility• High FrequencyOperation• Low PowerConsumption1 MHz guaranteed0.8 mW/bit @ 1 MHz• Minimum OperatingFrequency Guarantee 600Hz @ 25°C• Military and Commercial Temperature RangesMM400 Series -55°C to +125°CMM500 Series -25°C to +70°C• Low Output Impedance (V OH ) 500 ohms• Clock inputs directly compatible with MH0009,two phase clock driverThe power dissipation of the device decreases asthe operating frequency is decreased; at 10kHztypical dissipation is 6 p-W/bit. The minimumoperating frequency is also reduced substantiallyat lower temperatures; typical minimum frequencyof operation at 25°C is 100 Hz.3:.,. 3:oo.........~3:CJ1oenCD...CDenschematic and connection diagramsI-v" ---;-1 - ... ---.. --+-... ---.... --+--.... ----~,U.,IIIOATA=n" I FINPUT TA IT2II AIIGNO~-_t::~~;;~~::::~::~:-:7~~::::j:::~;,;:;.~~n·1 STAGECLOCK ~ ON PIN Jtypical applicationsFIGURE 1 - TTL/MOS Interface- Low Frequency(see clock timing graph for detail)3.9K 3.9KNA BIT REGISTERNil BIT REGISTER3.61