Dynamic Shift Registers - Bitsavers - Trailing-Edge

enCD''::CDtJ)o...CDoJ:c:(o~in...oJ:c:(o...~'litoJ:c:(oM...~oJ:c:(~oN...oJ:c:(applications information1. INPUT LOGIC COMPATIBILITYA. Voltage ConsiderationsIn general, the AH0100 series is compatible withmost DTL, TTL, and RTL logic families. The ONinputthreshold is determined by the V BE of theinput transistor plus the Vf of the diode in theemitter leg, plus I x R1, plus VR' At roomtemperature and V R = OV, the nominal ON thresholdis: 0.7V+0.7V+0.2V,= 1.6V.Over temperatureand manufacturing tolerances, the threshold maybe as high as 2.5V and as low as 0.8V. The rulesfor proper operation are:V 1N - V R ~ 2.5V All switches ONV 1N - V R S; 0.8V All switches OFFB. Input Current ConsiderationsIIN(oN), the current drawn by the driver withV 1N = 2.5V is typically 20 /lA at 25°C and is guaranteedless than 120 /lA over temperature. DTL,such as the DM930 series can supply 180 /lA atlogic "1" voltages in excess of 2.5V. TTL outputlevels are comparable at 400 /lA. The DTL andTTL can drive the AH0100 series directly. However,at low temperature, DC noise margin in thelogic "1" state is eroded with DTL. A pull·up resistorof 10 kn is recommended when using DTLover military temperature range.If more than one driver is to be driven by a DM930series (6K) gate, an external pull-up resistor shouldbe added. The value is given by:where:11Rp = N _ 1 for N > 2Rp = value of the pull·up resistor in knN = number of drivers.C. Input Slew RateThe slew rate of the logic input must be in excessof 0.3V l/ls in order to assure proper operation ofthe analog switch. DTL, TTL, and RTL outputrise times are far in excess of the minimum slewrate requirements. Discrete logic designs, however,should include consideration of input rise time.2. ENABLE CONTROLThe application of a positive signal at the V Rterminal will open all switches. The V R (ENABLE)signal must be capable of rising to within 0.8V ofV1N(ON) in the OFF state and of sinking IR(oN)milliamps in the ON state (at V1N(ON) - V R >2.5V). The V R terminal can be driven from mostTTL and DTL gates.3. DIFFERENTIAL INPUT CONSIDERATIONSThe differential switch driver is essentially a differentialamplifier. The input requirements for properoperation are:IV1N1 - V 1N2 12: 0.3V2.5 -:; (V1N1 or V 1N2) - V R -:; 5VThe differential driver may be furnished by a QClevel as shown below. The level may be derivedfrom a voltage divider to V+ or' the 5V Vee ofthe DTL logic. In order to assure proper operation,the divider should be "stiff" with respect to IIN2'Bypassing R1 with a 0.1 /IF disc capacitor willprevent degradation of tON and tOF F'Alternatively, the differential driver may be drivenfrom a TTL flip-flop or inverter.Connection of a 1 mA cu rrent source between V Aand V- will allow operation over a ±10V commonmode range. Differential input voltage must be lessthan the 6V breakdown, and input threshold of2.5V and 300mV differential overdrive still prevail.,lOY ICMRANGE+12V152