Dynamic Shift Registers - Bitsavers - Trailing-Edge

programming of MM5704Keyboard Scan CycleThe matrix scan cycle includes:Counter advancing through each "T" quadrantline T 1 through T 5 each with D c~untetdelay to charge "T" line capacitance.2 Counter advancing through eight switches ineach "T" quadrant except for T 5 static switchquandrant.3 D counter advances on either system clockI/>IN or Cycle Marker (programmable feature).The keyboard scan frequencywherefscan = Kd + I/>fK = 5 (five T quandrants)d = D counter delay time = (D counter modulusx ;s)r = 33 (Four quandrants times eight switchscans + 1 bit time for T 5 static switchtransfer).I/>t = The frequency at wh ich the clock I/IIN isshifting data through the device.1/1 5 =I/If when D counter driven by I/>f or I/>f/Xwhen x is bit times between Cycle Markers.Key Bounce Delay TimeSince the M counter advances the E counter onceeach complete keyboard scan the modulo of the Ecounter determines the key bounce delayrE . (Kd + if}f)E = modulus of E counterThe key bounce delay time is the total time elapsedfrom the first detected key depression until theload flip-flop signals transfer of the character codefrom ROM to the 9 bit shift register. The E countercontrols the number of times the entire keyboardis scanned before a valid key depression is accepted.Variations in timing are obtained from programmingof the D counter, E counter, I/>f (systemoperating frequencyl and Cycle Marker rep rateprovide flexibility for the keyboard interface elementto interface with a wide variety of keyswitch elements.Idle Key ResetDuring an idle key mode (power on) an automaticreset signal is generated by charging an externalcapacitor C R which enables the control logic todetect first key depression. This reset preventskeyboard lock-up by mass depression of keys orany attempt to void the integrity of the keyboardencoding. As an example, if a person attempts tohold down three or more keys to force an alarmcondition to repeat, in hopes of voiding the keyboardlogic, as soon as the keys are released andbounce delay timed out the idle key reset enablesthe control logic. The value of the reset capacitoris dependent on the keyboard scan cycle. The valueof the external capacitor is:i1 x t.:CR = -v:;-i1 = average charging current = 1 mAV 1 = reset voltage = 3.0VE+nt.: = charging time interval tc = ~E = modulo of E countern = number of scan cycles beyond bounceout delayI/>f = frequency of clock I/>INStandard Keyboard TimingNational has programmed a keyboard interface elementwith the following conditions:Static Switch Form Normally Open (NO)Device Number one: static Xmit during bittime 5Case shift form Normally Open (NO) (alphacharacters)Character Code ASCII (8 bits with 9th bitodd parity)E counter modulus = 6D counter modulus = 4D counter driven by Cycle Marker CMIdentified as MM5704-AA (see code pattern)Typical ApplicationThe two main questions in most applications are:a. How much key matrix capacitance can becharged?b. What is the key bounce delay time?c. What is value of idle key reset capacitor?Using MM5704-AA in system with following characteristicsI/>t = 200 kHzl/>oUT(PWI = 0.5p.sCycle Marker frequency = I/>f121 (maximum datatransfer case)Key bounce delayrE (Kd +~)1 336 [5(4 x I/>s) + I/>f I6 . [5(4 x 21 ) + 33 I =200 X 10 3 200 X 10 313.5 ms7