Dynamic Shift Registers - Bitsavers - Trailing-Edge

timing diagramsSequence of Command and Data TransferNOTElIITT1MES - 0 1 Z 3 4 5 I 1 I • 10 11 12 13 14 15 16 11 11 I' 20 21 Z2 nCYCL~~RkER:lL ____ r~ ________________________ J~XMIT KEY :-.-nL-______ =:-:-__________________ _STATICXMIT ________...... n-rT1 NoTE3ALARM SET ______________....... nALARM REUT _______________..... nCHARACTER _________________ ..JnL-________________kEY::::: ___________________ ..... n...._____________________..-:-___________________....::;:::;::;:::;:::;:::;::;::;::::;-___ALARMrCHARAg!;: ___________________----! : : : : : : : : Ll--""","---I I~OVNAMIC(91____lNot. 1: Cycle Mtd., annol_, SODIIIf dian n lit r ......Iottl: litTilnemlif,f -bwtlzV.-IYlllinilnwm:+LIVtI .. V._Hott3: Slite Xmil$itllll i, _lit TifIIII- I'roI!lIIJIJIIId fol Iii TlmIS in MMI' .... AA.code patternKeyboard Interface ASCII Code ProgramCase ShiftUpper C,.. Logic Counter DrivingControl ICS)No X NCModuloLevel + - ProgramFunctionDevice I 1 III 20 o Counter 4 CMStatic Key Fonn No X NC No. 3 0 4 0 E Counter 6TimingUnitsKey ScanKeyPin No. 2(+) (Alpha)ldon· line Iden·tity T R 8 7 6 5 4 3 2 1 0 tityQ T1 RO 1 1 1 0 1 0 0 0W T1 Rl 1 1 1 0 1 0 1 1E T1 R2 1 1 1 0 0 0 1 0R T1 R3 1 1 1 0 1 0 0 1T T1 R4 1 1 1 0 1 0 1 0y Tl R5 1 0 1 0 1 1 0 0U Tl R6 1 0 1 0 1 0 1 0(511 T1 R7 1 1 1 0 0 1 0 0A T2 RO 1 0 1 0 0 0 0 0S T2 Rl 1 0 1 0 1 0 0 10 T2 R2 1 0 1 0 0 0 1 0F T2 R3 1 1 1 0 0 0 1 1G T2 R4 1 0 1 0 0 0 1 1H T2 R5 1 0 1 0 0 1 0 0J T2 R6 1 1 1 0 0 I 0 1K T2 R7 1 0 1 0 0 I 0 IZ T3 RO 1 0 I 0 I I 0 IX T3 Rl 1 1 I 0 1 1 0 0C T3 R2 I I I 0 0 0 0 1V T3 R3 I 0 1 0 1 0 1 IB T3 R4 I 0 I 0 0 0 0 1N T3 R5 1 0 1 0 0 1 1 IM T3 R6 I 0 I 0 0 I I 0L T3 R7 I I I 0 0 I I 00 T4 RO I I I 0 0 I I 1P T4 RI I 0 I 0 1 0 0 0[ T4 R2 I I I 0 I 1 0 1\ T4 R3 1 0 1 0 I 1 I 0I T4 R4 I I 1 0 I I I 0(5)("> T4 R5 1 I 1 0 I I I I@ T4 R6 1 1 1 0 0 0 0 0(5)- T4 R7 1 0 1 0 1 I 1 11 11 71 %0 20 41 91 51 )1 !1 30 $0 &10 (.0 .1 +00 81 #0 60 "01 -01 I0 01 ;0 0 SPI ?8 71 11 11 11 11 11 01 01 11 01 01 01 11 01 0I 11 01 0I 1I II 0I 0I 0I 01 II 1I 01 11 01 11 II II 0Pin No. 2(-) (Numeric)6 5 4 3 20 1 1 0 00 1 1 0 10 1 0 0 10 1 1 0 00 1 1 0 10 1 1 1 00 1 1 0 10 1 0 1 00 1 0 0 00 1 1 0 00 1 0 0 10 1 0 0 10 1 0 0 10 1 0 1 00 I 0 1 00 I 0 I 00 1 I 1 00 I I 1 00 1 0 0 00 1 I 0 10 1 0 0 00 I 0 1 10 I 0 1 I0 I 0 I I0 I 0 1 10 I 1 0 00 I 1 I 00 1 1 I I0 1 1 I I0 I 1 I I0 1 0 0 00 I I I 11 00 11 10 11 00 00 10 10 10 11 10 01 01 10 01 0I II 00 01 II 01 01 00 10 0I 10 0I 10 00 1I 00 01 1Note 1: A logic "1" or "X" "" "most negative voltilge".Note 2: A logic "0" "" "mos~ positive voltage".Not83: All "Don't Care" cases must be defined as a "1" or "0",Note 4: If less than 9 bits are used unused bits will be programmed logic "1".Note 5: These locations are programmed for clearing the keyboard alarm.Note &: Bit eight (column 7) is odd parity bit for ASCII code shown.6