Dynamic Shift Registers - Bitsavers - Trailing-Edge

()coNoJ::E........CONoJ::Eapplication information (con'tl3.4 Summary-Package Power ConsiderationsThe maximum capacitative load that the MH0026can drive is thus determined by package type, heatsink technique, ambient temperature, AC power(which is proportional to frequency and capacitiveload) and DC power (which is principally determinedby duty cycle). Combining equations previouslygiven, the following formula is valid forany clock driver with negligible input power andnegligible power in output high state:10-3C L (max in pF) = -n- XP max(mW) (T A ,pkg) X Req - (v+ - V-,' X (Dc) X 10 3(VT _ V )' X Req X f(MHz)C L (max in pF) = .5 X 10- 3 XPmax(mW) X 500- Vs ' X DcX 10 3Vs ' X 500X f(MHz)Where: n = number of drivers per pkg. (2 forthe MH0026)Pm ax( mW) (T A' pkg) = Package powerrating in milliwatts for given package,heat sink, and max, ambient temperature(See graphs)Req = equivalent internal resistanceReq = (V+ - V-)/IS(LOW) = 500 ohms (worstcase over temperature for the MH0026 or660 ohms typically)Vs = (V+ - V-) = total supply voltage acrossdeviceDc = Duty Cycle =Time in output low stateTime in output low + Time in output high stateTable I illustrates MH0026 drive capability undervarious system conditions.4.0 Pulse Width ControlThe MH0026 is intended for applications in whichthe input pulse width sets the output pulse width;i.e., the output pulse width is logically controlledby the input pulse. The output pulse width is givenby:) _ tr +t f _(PW OUT - (PW)IN+ - PW IN+25nsTwo external input coupling capacitors are required to perform the level translation betweenTTL!DTL and MOS logic levels. Selection of thecapacitor size is determined by the desired outputpulse width. Minimum delay and optimum performanceis attained when the voltage at the inputof the MH0026 discharges to just above thedevices threshold (about 1.5V). If the input isallowed to discharge below the threshold, to F Fand t f will be degraded. The graph on page 132shows optimum values for CIN vs desired outputpulse width. The value for CIN may be roughlypredicted by:CIN = (2 X 10- 3 ) (PW)OUTFor an output pulse width of 500ns, the optimumvalue for C 1 N is:C 1 N = (2 X 10- 3 )(500 X 10- 9 ) == 1000pF5.0 Rise & Fall Time Considerations(Note 3)The MH0026's peak output current is I imited to1.5A. The peak current limitation restricts themaximum load capacitance which the device iscapable of driving and is given by:dvI = C l dt .;;; 1.5AThe rise time, t r, for various loads may bepredicted by:tr = (LW)(250 X 10- 12 + C l )Where: f-,.V = The change in voltage across Cl== V+ - V-CL = The load capacitanceFor V+ - V- = 20V, CL = 1000pF, tr is:tr == (20V)(250 X 10- 12 + 10- 12 )= 25nsTABLE 1. Worst Case Maximum Drive Capability for MH002S*TO·8WITH TO-8 MINI-DIP TO-S AND MINI·DIPPACKAGE TYPE HEAT SINK FREE AIR SOLDERED DOWN FREE AIRMax.Max. AmbientOperatingFrequency I ~Duty Cycle60°C 85°C BO°C 8SoC BO°C 85°C 60°C 8SoC100kHz 5% 30 k 24 k 19 k 15 k 13 k 10k 1.Sk 5.""500kHz 10% 6.5k 5.1k 4.1k 3.2k 2.7k 2k 1.5k 1.1klMHz 20% 2.9k 2.2k 1.8k 1.4k 1.1k 840 600 4302MHz 25% 1.4k 1.1k 850 650 550 400 280 1905MHz 25% 620 470 380 290 240 170 120 8010MHz 25% 280 220 170 130 110 79 - -·NOTE: Values in pF and assume both sides in use as non-overlaping 2 phase driver; each sideoperating at same frequency and duty cycle with (V + - V -) = 17 V136