Dynamic Shift Registers - Bitsavers - Trailing-Edge

uCDNoJ:~........CDNoJ:~application information1.0 IntroductionThe MH0026 is capable of delivering 30 wattspeak power (1.5 amps at 20V needed to rapidlycharge large capacitative loads) while its package islimited to the watt range. This section describesthe operation of the circuit and how to obtainoptimum system performance. If additional designinformation is required, please contact your localNational field application engineer.2.0 Theory of OperationConventional MOS clock drivers like the MH0013and similar devices have relied on the circuitconfiguration in Figure 1. The AC coupling of aninput pulse allows the device to work over a widerange of supplies while the output pulse widthmay be controlled by the time conStant - RJ X CJ.a simplified diagram, OJ (Figure 3) provides 0.7Vdead zone so that Q3 is turned ON for a risinginput pulse and Q 2 OFF prior to QJ turning ON afew nanoseconds later. O 2 prevents zenering of theemitter·base junction of Q 2 and provides an initialdischarge path for the load via Q3' During a fallinginput, the stored charge in Q3 is used beneficiallyto keep Q3 ON thus preventing Q 2 from conduct·ing until QJ is OFF. QJ stored charge is quicklydischarged by means of common-base transistorQ4'The complete circuit of the MH0026 (see schematicon page 130 basically makes Darl ingtons outof each of the transistors in Figure 3....---+-ov·,..--..... -ov·EXTERNALClIN~ r-o"-"""'-0 OUTEXTERNALClIN~ r-o01RlOUTt-4~-+-... o v-L-..... -.... -ov-FIGURE 1. Conventional MOS Clock DriveFIGURE 3. Simplified MH0026O 2 provides 0.7V of dead-zone thus preventing QJand Q 2 from conducting at the same time. Inorder to drive large capacitive loads, QJ and Q 2are large geometry devices but COb now limitsuseful output rise time. A high voltage TTL outputstage (Figure 2) could be used; however, duringswitching until the stored charge is removed fromQJ , both output devices conduct at the same time.This is familiar in TTL with supply line glitches inthe order of 60 to 100 mAo A clock driver builtthis way would introduce 1.5 amp spikes into thesupply lines....--..... -ov·When the output of the TTL input element (notshown) goes to the logic "1" state, current issupplied through CIN to the base of QJ and Q 2turning them ON, and Q 3 and Q 4 OF F when theinput voltages reaches 0.7V. Initial discharge ofthe load as well as E-B protection for Q 3 and Q 4are provided by Oland D 2 . When the inputvoltage reaches about 1.5V, Q 6 and Q7 begin toconduct and the load is rapidly discharged by Q7'As the input goes low, the input side of CIN goesnegative with respect to V- causing Q 8 and Q 9 toconduct momentarily to assure rapid turn-off ofQ 2 and Q7 respectively. When Q 1 and Q 2 turnOFF, Darlington connected Q 3 and Q 4 rapidlycharge the load toward V+ volts. R6 assures thatthe output will reach to within one V SE of theV+ supply.EXTERNALClIN~ r-o01OUTThe real secret of the device's performance isproper selection of transistor geometries and resistorvalues so that Q 4 and Q 7 do not conduct atthe same time while minimizing delay from inputto output.L-..... ~-~-t-ov-FIGURE 2. Alternate MOS Clock DriveUnique circuit design and advanced semiconductorprocessing overcome these clasic problems allow·ing the high volume manufacture of a device, theMH0026, that delivers 1.5A peak output currentswith 20ns rise and fall times into 1000pF loads. In3.0 Power Dissipation ConsiderationsThere are four considerations in determiningpower dissipations.1. Average DC power2. Average AC power3. Package and heat sink selection4. Remember-2 drivers per package134