Dynamic Shift Registers - Bitsavers - Trailing-Edge

RAMsMM5260 1024-bit fully decodeddynamic random access memorygeneral descriptionThe MM5260 fully decoded dynamic 1024 word x1-bit word read/write random access memory is amonolithic MOS integrated circuit using silicongate low threshold technology to achieve bipolarcompatibility on all I/O lines except the prechargeand read/write lines. This provides an efficientapproach to memory design using this systemsoriented device. The MM5260 is used for mainmemory applications where large bit storage andimproved operating performance are important. ATRI·STATETM output is utilized to allow wired"OR" capability and common I/O data busing inmemory applications.features• Fast access time 350 ns• Fast cycle time 450 ns read cycle min600 ns write cycle min• Low overhead circuit count Fully decoded• Systems-oriented design Bipolar compatible(address lines, chipenable data I/O)Common data I/O lineTRI-STATE output• Refresh cycle 2.0 ms• Easy memory expansion Chip enable• Device protection All I/O lines haveprotection againststatic charge• Standard power supplies +5V, -12V• Low power dissipation 400 mW• Small package size 16 pin dual-in-line packageapplications• High speed mainframe memory• Mass memory storagetypical applicationMain Memory Module Storing 4096 16-Bit Words" " / >--I+---tr