Dynamic Shift Registers - Bitsavers - Trailing-Edge

RAMsMM1103 1024-bit fully decodeddynamic random access read/write memorygeneral descriptionThe MM1103 fully decoded dynamic 1024 wordx 1-bit per word readlwrite random access memoryis a monolithic MaS integrated circuit using silicongate low threshold technology. This device providesa non-destructive read out memory cell withchip enable for easy selection when many outputsare "OR"ed. Low power is achieved by the use ofdynamic logic and power dissipation occurs primarilyduring precharge. The MM 1103 is used formain memory applications where large bit storage,high performance and low cost are important.• Refresh cycle• Fully decoded• Easy memory expansion• Device protection• "OR"ing outputcapability• Low power dissipation• Small package size2 msChip enable inputAll 1/0 lines haveprotection againststatic charge250mW18 pin DIPfeatures• Fast access time• Fast cycle time300 ns max480 ns read cycle580 ns write cycleapplications• Mainframe memory• Large buffer memoryconnection diagramDual-I n-Line PackageA, 1- -18 READ!WR1TEA, 2- ,..-17 VssA, 3- _16 CHIPENA8LEAo 4- I--l~ A,PRE-CHARGE ~- 1-14 DATAOUTPo" 6- 1--13 A.As 7- fo-12DATAINA; 8- 1--11 VDDA, 9- 1- 10 v ••TOP VIEW111