Dynamic Shift Registers - Bitsavers - Trailing-Edge

ROMsMM42411MM5241 3072-bit static read-only memorygeneral descriptionThe MM4241/MM5241 3072-bit static read-onlymemory is a P-channel enhancement mode monolithicMOS integrated circuit utilizing a low thresholdvoltage technology to achieve bipolar compatibility.TRI-STATETM outputs provide wire ORedcapability without loading common data' lines orreducing system access times. The ROM is organizedin a 64 x 6 word by 8-bit memory organization.Programmable Chip Enables (CE 1 and CE 2 )provide logic control of mUltiple packages withoutexternal logic. A separate output supply lead isprovided to reduce internal power dissipation inthe output stages.Customer programs may be submitted for productionin a paper tape or punched card format.logic and connection diagramsfeatures• Bipolar compatibility• Standard supplies• Bus ORable output• Static operation• Multiple ROM controlapplications• Character generator• Random logic synthesis• Micro-programming• Table look-upNo externalcomponents required+5V. -12VTRI-STATE outputsNo clocks requiredTwo programmableChip Enable linesA,A, A,Dual-In-Line PackageA.A,A,l,l,l,VDECODECE,o--------ICE,o--------IMEMORYARRAYB,B,B,B.B,B,B,B,NC 24 v"CE," v"NC 4 21 B,A, 20 ..A, IB ..CE, l 12 ..A, IB.. , '.11 B,A,• " B,A, 10 15 B,l, 11 14 l,v§ 12" l,TDPVIEWtypical applicationsTTL/MOS Interfacev§FIGURE 1. Power SaverforSmall Memory ArraysFIGURE 2. Power Saver forLarge Memory ArraysANY TTL/OllDEVICE.,....MM4241/..l,l,MM5241CE,----'CE,-----'B,B.B,..B,ANY TTL/OlLDEVICEr- --, r----,I I I -::- II I I II I I II Iv" L ___ ..JI IL ___ ..JASSUME IIVLL IIMIN '" 11-3V IIVOG - VLL MIN = R 11.& mAl (N) 1/I'here N = 1 fot 5 x 1lont.N= "oraIl8tont.When CE 1 '" 1, CE2 '" 1 the outputs are enabled when a logic LOW is applied to the chip enable line. The outputs are in the thirdstate when disabled. The logic states of the chip enables are specified on the program tape.103