Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsVGG Supply VoltageV D D Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4240MM5240Lead Temperature (Soldering, 10 sec)Vss - 30VVss - 15V(Vss - 20)V < V 1N < (Vss +0.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°C300°Celectrical characteristics (Note 1)PARAMETERCONDITIONSMINTYPMAXUNITSOutput Voltage LevelsMOSto MOSLogical "1"Logical "0"IMD to GNDVss - 1.0VSS - 9.0VVMOSto TTLLogical "1"Logical "0"6.8 kD to VGG Plus OneStandard Series 54/74 Gate+2.5+0.4VVOutput Current CapabilityLogical "0"V OUT = VSS - 6.0V2.5mAInput Voltage LevelsLogical "1"Logical "0"Vss - 2.0Vss - 8.0VVPower Supply CurrentIDDIGG (Note 2)25401mApAInput LeakageV 1N = VSS - 12V1pAInput CapacitanceVGG Capacitancef = 1.0 MHz, V 1N = OVf = 1.0 MHz, V 1N = OV525840pFpFAddress Time (Note 3)TACCESSSee Timing DiagramTA =25°C150450600nsOutput AND Connection(Note 4)MOS LoadTTL Load410Note 1: These specifications apply for VSS = +12V ±5%, VGG = -12V ±5%, and T A = -55°C to+125°C (MM4240), T A = -25°C to + 70°C (MM5240) unless otherwise specified.Note 2: The V GG supply may be clocked to reduce device power without affecting access time.Note 3: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram). See curves for guaranteed limit over temperature.Note 4: The address time in the TTL load configuration follows the equation:T ACCESS = The specified limit + (N - 1) (50) nsWhere N = Number of AND connections.The number of AND ties in the MOS load configuration can be increased at the expense of MOS "0"level.100