Dynamic Shift Registers - Bitsavers - Trailing-Edge

ROMsMM4232/MM5232 4096 -bit static read-only memorygeneral descriptionThe MM4232/MM5232 4096-bit static read-onlymemory is a P-channel enhancement mode monolithicMOS integrated circuit utilizing a low thresholdvoltage technology to achieve bipolar compatibility_TRI-STATETM outputs provide wire ORedcapability without loading common data lines orreducing system access times. The ROM is organizedin a 512 word x 8-bit or 1024 word x 4-bitmemory organization that is controlled by themode control input. Programmable Chip Enables(CE, and CE 2 ) provide logic control of up to 16Kbits without external logic. A separate outputsupply lead is provided to reduce internal powerdissipation in the output stages.Customer programs may be submitted for productionin a paper tape or punched card format.features• Bipolar compatibility No externalcomponents requ ired• Standard supplies +5V, -12V• BusORableoutput TRI-STATEoutputs• Static operation No clocks required• Multiple ROM control Two-programmableChip Enable linesapplications• Character generator• Random logic synthesis• Micro-programming• Table look-uplogic and connection diagramsA, A,Dual-In-Line PackageA. 1--~--oB,A,A,A,A,A,A"CON~~~~ o---..JCE,o----------ICE,o----------IMEMORYARRAYI--~-:I:-o B,1---Dt:~-oB,I---Dt:=-f-o B.B,B,B,1--~-+-oB,MODE CONTROL 1 24 V"CE, 2l V"CE," B,A" •21 B,A,, 20 B,A, I 19 B,A, 7 18 B.A, 17 B,A, 16• B,A,15 B,A, " 11V~ 12 " ..13 A,TQPVIEWtypical applicationsTTL/MOS InterfaceFIGURE 1_ Power Saver forSmall Memory ArraysFIGURE 2. Power Saver forLarge Memory ArraysA,A,A,A,A,A,v"MM42321MMS232B... ..B,--,IIIIIL ___ .Jr----,I'::' IIII II IVGGL ___ .JCE,o----.JCE,o------I512 x 8 ROM connectionMode Control - logic HIGHAl0 - logic lOWASSUME IIVlL IIMIN ~ II-JV IIVGG - Vu MIN R (1.6 rnA) (N) where N ""4 lor 1024 x 4 organizationN ~ 810r 512 x 8 organizationOperating Modes1024 x 4 ROM connectionMode Control - Logic LOWA10 - Logic HIGH enables the odd(8, ... 8 7 ) outputsLogic LOW enables the even(8'2 ... 8a) outputsWhen eE 1 = 1. CE 2 :: 1 the outputs are enabled when a logic LOW is applied to the chip enable line. The outputs are in the thirdstate when' disabled. The logic states of the chip enables are specified on the program tape. Mode Control must be hard wired toVGG or V LL for a logic LOW or to Vss-for a logic HIGH.95