Dynamic Shift Registers - Bitsavers - Trailing-Edge

absolute maximum ratingsVGG Supply VoltageVoo Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4231MM5231Vss - 20VVss - 20V(Vss - 20)V < V 1N < (Vss + 0.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsPARAMETERCONDITIONSMINTYPMAXUNITSOutput Voltage LevelsMOS to TTLLogical "1"Logical "0"6.8 kn ±5% to Voo Plus OneStandard Series 54/74 Gate2.4+0.4 VVOutput Current CapabilityLogical "0"V OUT = 2.4V2.5mAInput Voltage LevelsLogical "1"Logical "0"Vss - 2.0Vss - 4.2VVPower Supply Current100IGG (Note 1)TA = 25°CVss = +5VVGG = Voo = -12V1530 mA1 p.AInput LeakageV 1N = -12V1 p.AInput Capacitancef = 1.0 MHz, V 1N = OV5pFV GG Capacitancef = 1.0 MHz, V 1N = OV15pFAddress Time (Note 2)TAccEssSee Timing DiagramT A = 25°C Vss = +5.0VVGG = Voo = -12.0V640950 nsOutput AND Connections(Note 3)6.8 kn ±5% to Voo Plus OneStandard Series 54/74 Gate8Note 1: These specifications apply for VSS = +5V ±5%, VGG = VOO = -12V, ±5%, and T A = -55"Cto +125°C (MM4231), T A = -25°C to +70oC (MM5231) unless otherwise specified.Note 2: The VGG supply may be clocked to reduce device power without affecting access time.Note 3: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.Note 4: The address time in the TTL load configuration follows the equation:T ACCESS = The specified limit + (N -1) (50) ns.Where N = Number of AND connections.Note 5: Capacitances are measured on a lot sample basis only.92