Dynamic Shift Registers - Bitsavers - Trailing-Edge

National Semiconductor CorporationMOS INTEGRATED CIRCUITS

G^0 ?4LONDON :PRINTED BY CHAS. J. CI.ARK. 4, LINCOLN'S INN FIELDS, W.C.

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Table of ContentsMOS Selection Guide ....................................................... viMAPS (Microprogrammable Arithmetic Processor System) ............................... 1MM5704AA MOS/LSI Keyboard Interface Subsystem ................................. 3Dynamic Shift RegistersMM400/MM500 Dual 25-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9MM401/MM501 Dual 25-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9MM402/MM502 Dual 50-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9MM403/MM503 Dual 50-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9MM406/MM506 Dual 100-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9MM407/MM507 Dual 100-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9MM1402A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12MM1403A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12MM1404A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12MM4001A/MM5001A Dual 64-Bit Dynamic Shi.ft Register .............................. , 15MM4006A/MM5006A Dual 100-Bit Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18MM4007/MM5007 Dual 100-Bit Programmable Shift Register ............................ 18MM4010A/MM50l0A Dual 64-Bit Accumulator ..................................... 15MM4012/MM5012 Dual 256-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21MM4013/MM5013 1024-Bit Dynamic Shift Register/Accumulator ......................... 25MM4015A/MM5015A Triple 60 + 4-Bit Accumulator/Register. . . . . . . . . . . . . . . . . . . . . . . . . . .. 28MM4016/MM5016 512-Bit Dynamic Shift Register ................................... 31MM4017/MM5017 Dual 512-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 34MM4018/MM5018 Triple 64-Bit Dynamic Shift Register ............................... , 37MM4019/MM5019 Dual 256-Bit Mask Programmable Shift Register ........................ , 18MM4020/MM5020 Quad 80-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40MM4021/MM5021 Triple 80-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40MM5024A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. 12MM5081 10-Bit Serial In-Parallel Out Lamp Driver/Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43MM4104/MM5l04 Multi-Length Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 45MM4105/MM5l05 Quad 64-Bit Dynamic Shift Register/Accumulator. . . . . . . . . . . . . . . . . . . . . .. 48Static Shift RegistersMM404/MM504 Dual 16-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 51MM405/MM505 Dual 32-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 51MM4040/MM5040 Dual 16-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 54MM4050A/MM5050A Dual 32-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 57MM4051A/MM5051A Dual 32-Bit Static Shift Register-Split Clock. . . . . . . . . . . . . . . . . . . . . . . .. 57MM4052/MM5052 Dual 80-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. 60MM4053/MM5053 Dual 100-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60MM5054 Dual 64/72/80-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 63ROMsMM3501 1024-Bit Static Read-Only Memory ....................................... TBAMM4203/MM5203 2048-Bit Electrically Programmable Static Read-Only Memory (pROM) . . . . . . . .. 67MM4210/MM5210 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 71MM4211/MM5211 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 75MM4213/MM5213 1024-Bit Read-Only Memory ..................................... TBAMM4220/MM5220 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 79MM4221/MM5221 1024-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 83MM4230/MM5230 2048-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87MM4231/MM5231 2048-Bit Static Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 91MM4232/MM5232 4096-Bit Static Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95MM4240/MM5240 2560-Bit Static Character Generator/Read-Only Memory. . . . . . . . . . . . . . . . . .. 99MM4241/MM5241 3072-Bit Static Character Generator/Read-Only Memory ................... 103iii

RAMsMM1101 256-Bit Fully Decoded Static Random-Access Memory __ ......................... 107MM11011 256-Bit Fully Decoded Static Random-Access Memory ......................... 107MM1101A 256-Bit Fully Decoded Static Random-Access Memory ............ " ........... 107MM1101A1 256-Bit Fully Decoded Static Random-Access Memory ......................... 107MM1101A2 256-Bit Fully Decoded Static Random-Access Memory ......................... 107MM1103 1024-Bit Fully Decoded Dynamic Random-Access Memory ....................... 111MM5260 1024-Bit FlJlly Decoded Dynamic Random-Access Memory ....................... 114MM5262 2048-Bit Fully Decoded Dynamic Random-Access Memory ....................... TBAClock DriversMH0007/MH0007C Single Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 117MH0009/MH0009C Two Phase MOS Clock Driver .................................... 119MH0012/MH0012C High Speed MOS Clock Driver ................................... 121MH0013/MH0013C Two Phase MOS Clock Driver .................................... 123MH0025/MH0025C Two Phase MOS Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 127MH0026/MH0026C 5 MHz Two Phase MOS Clock Driver ............................... 130MH0027C Dual High Speed MOS Interface Driver 138Analog SwitchesMM450/MM550 Dual Differential Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 141MM451/MM551 Four-Channel Analog Switch ....................................... 141MM452/MM552 Four MOS Transistor Package ....................................... 141MM454/MM554 Four-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 145MM455/MM555 Three MOS Transistor Package ...................................... 141AH0120 Series High Level Analog Switches ......................................... 148AH0130 Series High Level Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 148AHO 140 Series High Level Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 148AH0150 Medium Level Analog Switches ........................................... 148AH0160 Medium Level Analog Switches ........................................... 148AH2114/AH2114C DPST Analog Switch .......................................... 155AM1000 Silicon N-Channel High Speed Analog Switch ................................. 157AM 1 001 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 157AM 1002 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 157AM3705/AM3705C 8-Channel MOS Analog Multiplexer ................................ 159NH0014/NH0014C DTL/TTL Compatible DPDT Analog Switch ........................... 163NH0015/NH0015C Quad Analog Switch ........................................... TBANH0019/NH0019C (MH453/MH533) DTL/TTL Compatible Dual DPST Analog Switch ........... 163Logic ElementsMM480/MM580 Dual 3-lnput NOR GateMM481/MM581 Dual Exclusive OR GateMM482/MM582 Dual Digital Multiplex Switch ....................................... 167MM483/MM583 JK Flip Flop .................................................. 167167167ROM Character GeneratorsMM4220NP/MM5220NP 7x9 Horizontal Scan Display Character Generator ................... 173MM4230NN/MM5230NN 7x9 Horizontal Scan Display Character Generator. . . . . . . . . . . . . . . . . .. 173MM4230NO/MM5230NO 7x9 Horizontal Scan Display Character Generator. . . . . . . . . . . . . . . . . .. 173MM4240AA/MM5240AA 7x5 Horizontal Scan ASCII-7 Character Generator. . . . . . . . . . . . . . .. 99,267MM4240AE/MM5240AE ASCII-7 and Lower Case Character Generator ..................... 267MM4240ABU/MM5240ABU Hollerith Character Generator ........................... 175,267MM4240ABZ/MM5240AIiZ EBCDIC-8 Character Generator .......................... 177,267MM4240ACA/MM5240ACA EBCDIC Character Generator ............................ 178,267MM4241ABL/MM5241AIJL Vertical Scan ASCII-7 Character Generator ..................... 267MM4241ABV/MM5241ABV Vertical Scan ECMA-7 (Scandinavian) Character Generator ........... 267MM4241ABW/MM5241ABW Vertical Scan ECMA-7 (German) Character Generator ............. 267MM4241ABX/MM5241ABX Vertical Scan ECMA-7 (French, British, Italian) Character Generator .... 267MM4241ABY /MM5241ABY Vertical Scan ECMA-7 (Spanish) Character Generator .............. 267iv

For information on the following character generators contact National,Santa Clara:MM4240AD/MM5240AD Katakana Alphabet Character GeneratorMM4240AF/MM5240AF 5x7 ASCII-6 with Low True Outputs Character GeneratorMM4240AH/MM5240AH 5x7 ASCII-6 with High True Outputs Character GeneratorMM4240AK/MM5240AK 5x7 ECMA-6 (French, British, Italian) Character GeneratorMM4241AAN/MM5241AAN ASCII Vertical Scan Character GeneratorROM Code ConvertersSK0003 Sine/Cosine Look-Up Table Kit ___ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 179MM4220AE/MM5220AE ASCII-7 to Hollerith Code Converter ........................... 181MM4220AP/MM4220AP BCDIC to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 183MM4220BL/MM5220BL Baudot to ASCII Code Converter. .............................. 185MM4220BM/MM5220BM Sine Look-Up Table ....... _ ............................... 187MM4220BN/MM5220BN Arctangent Look-Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 189MM4220DF/MM5220DF "Quick Brown Fox" Generator ............................... 191MM4220EK/MM5220EK BCDIC to EBCDIC and ASCII to EBCDIC Code Converter ............. 193MM4220LR/MM5220LR BCOIC to ASCII-7, ASCII-7 to BCDIC Code Converter ............... 195MM4221RQ/MM5221RQ ASCII-7 to EIA RS244A, EIA RS244A to ASCII-7 Code Converter ....... 197MM4221RR/MM5221RR ASCII-7 to EBCDIC Code Converter ........................... 199MM4230BO/MM5230BO Hollerith to ASCII Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 201MM4230FE/MM5230FE Selectric to EBCDIC, EBCDIC to Selectric Code Converter ............. 202MM4230JT/MM5230JT BCDIC to EBCDIC, EBCDIC to BCDIC Code Converter ............... 205MM4230KP/MM5230KP ASCII-7 to Selectric Code Converter ............................ 207MM4230QW/MM5230QW Hollerith to EBCDIC Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . .. 209MM4230QX/MM5230QX EBCDIC-8 to ASCII-8 Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 210MM4230QY /MM5230QY ASCII-8 to EBCDIC-8 Code Converter ........................... 212MM5230RS Binary to Modulo-n Divider Code Converter ....... _ .. _ .................... 214MM4231 RP/MM5231 RP IBM 1130 EBCDIC to ASCII-7 Code Converter ..................... 216DM5488AA/DM7488AA (SN5488/SN7488) 256-Bit Sine Look-Up Table Read-Only Memory ....... 218DM7598AA/DM8598AA TRI-STATETM 256-Bit Sine Look-Up Table Read-Only Memory ....... " 222For information on the foUowing code converters contact National, Santa Clara:MM350lTL ASCII to Baudot, Baudot to ASCII Code ConverterMM4213UW/MM5213UW EBCDIC-8 to Hollerith Code ConverterMM4221TM/MM5221TM ASCII to Baudot, Baudot to ASCII Code ConverterMM4230JC/MM5230JC ASCII to Hollerith Code Converter*MM4230JP/MM5230JP ASCII to MDS Code ConverterMM4230JQ/MM5230JQ Hollerith to EBCDIC Code Converter*MM4230JR/MM5230JR Selectric to EBCDIC Code Converter*MM4230JS/MM5230JS EBCDIC to Selectric Code Converter*MM4230SQ/MM5230SQ ASCII-a to Hollerith Code ConverterCustom MOS/LSI ............... __ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225Application NotesAN-40 The Systems Approach to Character Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 229AN-44 High Voltage Shift Registers Move Displays ................................... 241AN-50 Dynamic MOS Random Access Memories System ............................... 245AN-52 Using the MM5704 Keyboard Interface in Keyboard Systems Consideration ............. 251AN-55 Low Frequency Operation with Dynamic Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . .. 263AN-57 American and European Fonts in Standard Character Generators . . . . . . . . . . . . . . . . . . . .. 267MOS BriefsMOS Brief 10 Trig Function Generators ........................................... 273MOS Brief 14 Mask Programming Specializes MOS Shift Register Designs ..................... 275Ordering Information and Physical Dimensions ....................................... 277Definition of Terms. _ .................... _ .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 279*Not recommended for new designs. TBA - To Be Announcedv

MOS Selection GuidePRODUCT TYPE NO.MIL/COMMAX FREQVDD2DESCRIPTION OR MIN VSS VDD ORACCESS TIMEVGGCLOCKSWINGMM400/MM500 Dual 25 Bit 1.0 MHz +10 GND None 16MM401/MM501 Dual 25 Bit 1.0 MHz +10 GND None 16MM402/MM502 Dual 50 Bit 1.0 MHz +10 GND None 16MM403/MM503 Dual 50 Bit 1.0 MHz +10 GND None 16MM406/MM506 Dual 100 Bit 1.0 MHz +10 GND None 16MM407/MM507 Dual 100 Bit 1.0 MHz +10 GND None 16MM4001A/MM5001A Dual 64 Bit Split Clock 2.5 MHz +5 None -12 17MM4006A/MM5006A Dual 100 Bit 2.5 MHz +5 None -12 17MM4007/MM5007 Dual 100 Bit Mask Programmable 2.5 MHz +5 None -12 17MM4010A/MM5010A Dual 64 Bit Accumulator 2.5 MHz +5 None -12 17MM4011A/MM5011A Dual 64 Bit Common Clock 2.5 MHz +5 None -12 17MM4012/MM5012 Dual 256 Bit Accumulator 2.5 MHz +5 None -12 17e:.U) MM4013/MM5013 1024 Bit Accumulator 2.5 MHz +5 None -12 17.>! MM4015A/MM5015A Triple 60 + 4 Accumul!'tor 2.5 MHz +5 None -12 17EMM4016/MM5016 500/512 Bit 2.5 MHz +5 None -12 17'" c:> MM4017/MM5017 Dual 500/512 Bit 2.5 MHz +5 None -12 17QMM4018/MM5018 Triple 64 Bit 2.5 MHz +5 None -12 17MM4019/MM5019 Dual 256 Mask Programmable 2.5 MHz +5 None -12 17MM4020/MM5020 Quad 80 Bit 2.5 MHz +5 None -12 17MM4021/MM5021 Triple 80 Bit 2.5 MHz +5 None -12 17e:.MM4100/MM5100 144/156 Bit 1.0 MHz +5 None -12 17MM4104/MM5104 360/359 + 288/287. 40/32 Bit 2.5 MHz +5 None -12 17MM41 05/MM51 05 Quad 64 Accumulator 2.2 MHz +5 None -12 17MM1402A Quad 256 Bit 5.0 MHz +5 -9 None 14MM1403A Dual 512 Bit 5.0 MHz +5 -9 None 14MM1404A Single 1024 Bit 5.0 MHz +5 -9 None 14MM5024ASingle 1024 Bit withInternal Pullup Resistor 5.0 MHz +5 -9 None 14MM404/MM504 Dual 16 Bit 1.0 MHz +10 GND -6 16MM405/MM505 Dual 32 Bit 1.0 MHz +10 GND -6 16MM4040/MM5040 Dual 16 Bit 2.2.MHz +5 GND -12 17U) MM4050/MM5050 Dual 32 Bit Common Clock 1.6 MHz +5 GND -12 17.~ "MM4051/MM5051 Dual 32 Bit Split Clock 1.6 MHz +5 GND -12 17MM4052/MM5052 Dual 80 Bit 1.6 MHz +5 GND -12 17tilMM4053/MM5053 Dual 100 Bit 1.6 MHz +5 GND -12 17MM4054/MM5054 Dual 64/72/80 On Chip Clock 2.2 MHz +5 GND -12 TTLMM5081 High Voltage (VL =-55V) MM413 250 kHz GND -20 -20 -20MM4203/MM52032048 Bit ROM (Pin CompatibleMM4213) TSL 1.0 IlS +5 -12 -12 NoneMM4210/MM5210 1024 Bit (256 x 4) 650 ns +12 -12 -12 NoneMM4211/MM5211 1024 Bit (256 x 4) 950 ns +5 -12 -12 NoneMM4213/MM52132048 Bit ROM (Pin CompatibleMM4203) TSL 750 ns +5 -12 -12 NoneMM4220/MM5220 1024 Bit (256x4 or 128x8) 650 ns +12 -12 -12 Nonei MM4221/MM5221 1024 Bit (256x4 or 128x8) 950 ns +5 -12 -12 None0a: MM4230/M M5230 2048 Bit (512x4 or 256x8) 725 ns +12 -12 -12 NoneMM4231/MM5231 2048 Bit (512x4 or 256x8) 950 ns +5 -12 -12 NoneMM4232/MM5232 4096 Bit (1024x4 or 512x8) TSL 1.0 IlS +5 -12 -12 NoneMM4240/MM5240 2560 Bit Character Generator 600 ns +12 -12 -12 NoneMM4241/MM5241 3072 Bit Character Generator 900 ns +5 -12 -12 NoneSKOO03 Sine Look·Up Table 1.0 MHz +12 -12 -12 NoneMMll0l 256 Bit Static (256 xl) 1.5 IlS +5 -7 -10 NoneMMll0ll 256 Bit Static (256 xl) 1.0 IlS +5 -7 -10 NoneMMll01A 256 Bit Static (256 xl) 1.5 IlS +5 -9 -9 NoneMMll01Al 256 Bit Static (256 xl) 1.0 IlS +5 -9 -9 Nonei MMll01A2 256 Bit Static (256 xl) 500 ns +5 -9 -9 None

MAPSmicroprogrammable arithmetic processor systemgeneral descriptionMicroprogrammable Arithmetic Processor Systemdevices (MAPS) are MaS/LSI elements that representsa general purpose serial data processor (seeFigure 1). The system can be programmed to operatein binary or BCD up to a 76 bit one cycle dataword. The system provides a wide variety of dataword formating and is applicable to any serialarithmetic control system from mach ine and pro·cess control to business machines.The basic system is comprised of five MaS/LSIsub-system elements:• MM5700 Arithmetic Unit• MM5701 Register Unit• MM5702 Timing and Control Unit• MM5704 Keyboard Interface Unit• MM5705 Control Read Only MemoryAdditional elements for system expansion are:• MM5703 Control Read Only Memory• MM5706 Static Data MonitorDATA MEMORY(ACCUMULATOR)CONTROL LOGIC(TIMING)1a. General Computer OrganizationREGISTER ELEMENTS (MODULAR)FOR DATA MEMORY RUCONTROL LOGICT&C1b. MAPS OrganizationFIGURE 1. General Purpose Computer Organization Compared to MAPS

The five basic elements are interconnected by aserial bit bus-organized distribution system withthree data buses, and three command buses (seeblock diagram Figure 2). The basic cycle of thesystem is 76 bits, controlled by a set of 32 datamicro-instructions stored in the arithmetic andregister unit.packages for easy handling and test. Compatibilitywith the keyboard, data codes, timing and programsrequired for the system application is obtainedduring wafer fabrication by mask programming.A preprogrammed calculator kit with 14-'digit display outputs is available for evaluationand general use.MICRO INSTRUCTIONBUSYALARM'-++-___ +; ____ H-__ -+-_-i-I---II/OBUSI'--____________ -+-___ --1 1/0 BUS II(4)(5(DISPLAY'--__ ---'I DATA TRANSFER LINE• SIGNAL OR CONTROL DATA LINEFIGURE 2. MAPS Block DiagramData between these elements is passed serial overthe three data buses. The logic sequence of datahandling is programmed in the CRaM element,each CRaM provides the system 256 words of a10-bit command. The T&C element interpolateseach command and generates proper time synchronizationand time enable signals for performing thecommand, thus allowing the data in the AU andRU elements to be acted upon. To perform dataresult tests and control operations, 32 commandmicroinstructions are stored in the T&C element.The format and function performed by each commandinstruction is programmable by storing theproper bit pattern for the op-code in CRaM storage.This allows the same basic command instructionto be programmed differently for a widevariety of mach ine applications. The keyboardencoder will accept up to 32 dynamic keys and 8static switch inputs and the static data monitorwill scan two banks of 8 data points.The specific system configuration is expandablesince additional RU, CRaM, KI and SDM elementscan be added on the data and command bus system.The system will accommodate up to 32CRaMs or a total of 8192 microprogrammed instructions.Access from microprogrammed instructionsin RAM and mass storage can be performedand controlled. This allows the MAPS elements tofunction as mini-processors within a larger system.The system is dynamic two phase logic fabricatedwith National's bipolar compatible, P-channel enhancementmode, low threshold technology. Allelements are in small 16 and 24 pin dual-in-linefeatures• Bus-organized for easy expansion and interfacewith external systems• Keyboard input• Static data monitor binary or BCD input• Error-free keyboard decoding (see MM5704AAdata sheet)• Data and display control outputs• Clock rates to 750 kHz two phase logic• DTl/TTl compatible on output for display• Standard +5V and -12V supplies• Standard 16-pin and 24-pin DIPsapplications• General purpose serial computers• "Smart" data terminals• Numerical controls• Electronic business machines• Point of sales equipment• Electronic scales• Electronic calculators• Traffic controls• Medical electronics (analyzers, patient monitoring,etc.)2

MAPSMM5704AA MOS/LSI keyboard interface subsystemgeneral decriptionThe MM5704AA keyboard interface subsystem isa monolithic MaS/LSI circuit utilizing P-Channelenhancement mode low threshold voltage technology.It self-scans 32 dynamic keys (4 x 8matrix) and 8 static keys for switch closure. Thedynamic key positions are encoded into a 9-bitcode that is transmitted bit serial. The static keysare encoded into an 8-bit code. A read-only memoryallows customer programming of the charactercode for the 9-bit code. Control logic providesprogrammable delay times to match the switchbounce characteristics and key matrix capacjtancefor a wide selection of keyboard elements. Two"busy" lines are provided so several keyboardinterface chips can be paralleled to decode largerkey matrixes. Two key "roll over" is providedalong with positive lock-out for ambiguous keydepressions.features• Bipolar compatibility• Standard suppliesMinimum externalcomponents required+5V. -12V• Bit serial data transmission Uptoa9-bit code• Character code selection• Error-free decodeProgrammable charactercode ROMProvides two key"roll over" multiplekey lock-out by an alarmbusy line for activedecode indication• High speed0.75 MHz• Keyboard element fl-exibility Programmablekey bounce delayProgrammable keymatrix capacitance delayProgrammable keysfor alarm clearProgrammable idlekey reset delay• Large keyboard• Expandable• Timing control• Standard packageapplications• Keyboard decode• Binary multiplexer/encoder32 dynamic keys8 static keysBusy line ORed output(expandable in multiples of32 dynamic-8 static keys)Provides "character ready"command and respondson "transmit" command24-pin dual-in-linepackageTerminal interfaceCalculatorAccounting machineTypewriterBinary remotesensingblock and connection diagramsDual-In-Line Package2JilIIVlI """.,,"""CYClUI~RI(EII ,~ICM)CASlSlW~...!'+-____ I--'"I"'T'·-1- "IV .. 1213¢Cu-rNotol, .. svl ..' .."I2 ...

absolute maximum ratingsVoltage at Any PinBulk Reference (substrate)Package Power Dissipation at 70 0 eVss + 0.3V to Vss - 20.0VVss500mWelectrical characteristicsT A = 2Soc; V 55 "" +5V, V GG = -12V; or Vss = OV. V GG = -17V; all supplies ±5%, unless otherwise notedOperating Temperature RangeStorage Temperature RangePARAMETER CONDITIONS MIN TYPClocks (¢IN ¢OUT)Repetition Rate (¢f) Min. ¢pw 0.02Pulse Width (¢pw)1 Min 190%1 Min'¢f 0.3 0.5o Min 110%1 0.4 0.6AmplitudeLogic Level "0" With Respect to V 55 0Logic Level "1" -16 -17Delay Times

typical applicationsTTL/DTL Logic Compatible -SEE ELECTRICALSPECIFICATIONSBit Serial Data OutputBUSY 1 I__ (NOTEIBUSY! )IDLE KEY RESETKEYBOARD INTERFACESUBSYSTEM (KIIMM5704~ CR NOTElVss OR OPEN CASE SHIFTVGG --0 ""C)-__(;;;,CS;';')_-i~ALARM OUTTTL COMPATIBLECYCLEMARKER(CM)Vss (+5V)TTL COMPATIBLENote 1: With single keyboard interface application, if busy lines are not used in system, leave open. Ifsystem will use busy signal, it will require MOS to TTL interface. In multiple (KI) subsystem.pplicmons. busy lines are connected busy 1 to busy 1 and busy 2 to busy 2.Note 2: D,ta on data bus is in HZ format Data should be strobed attPOUT.Note 3: CR value dependent on keybolrd scan frequency.TTL/DTL Compatible - Output Bit ParallelBUSY 1 1__ (NOTEIBUSY Z )SEE ELECTRICALSPECIFICATIONSIDLE KEY RESETKEYBOARD INTERFACESUBSYSTEM (KIIMM5704~ CR NOTElVss OR OPEN CASE SHIFT(CS)VGG --0 ""C~-"";''''';''-'''''~VssALARM OUTVGG (-lZV)TTL COMPATIBLECYCLEMARKER(CM)16K.'NDATA STROBEV3 (OPEN)V,(VGG)r-~-t!--VssliZ DMBBOOV3 (OPEN)V, (VGG)SERIAL OUTPUT(COMMANO SIGNALS)Note 1: With single keyboard interface application, if busy lines are not used in system, leave open. Ifsystem will use busy signal, it will require MOS to TTl interface. In multiple (KI) subsystemapplications, busy lines are connected busy 1 to busy 1 end busy2 to busy 2.Note 2: Data on data bus is in AZ format. Data should be strobed at !POUT.Note 3: CR value dependent on keyboard scan frequency.5

timing diagramsSequence of Command and Data TransferNOTElIITT1MES - 0 1 Z 3 4 5 I 1 I • 10 11 12 13 14 15 16 11 11 I' 20 21 Z2 nCYCL~~RkER:lL ____ r~ ________________________ J~XMIT KEY :-.-nL-______ =:-:-__________________ _STATICXMIT ________...... n-rT1 NoTE3ALARM SET ______________....... nALARM REUT _______________..... nCHARACTER _________________ ..JnL-________________kEY::::: ___________________ ..... n...._____________________..-:-___________________....::;:::;::;:::;:::;:::;::;::;::::;-___ALARMrCHARAg!;: ___________________----! : : : : : : : : Ll--""","---I I~OVNAMIC(91____lNot. 1: Cycle Mtd., annol_, SODIIIf dian n lit r ......Iottl: litTilnemlif,f -bwtlzV.-IYlllinilnwm:+LIVtI .. V._Hott3: Slite Xmil$itllll i, _lit TifIIII- I'roI!lIIJIJIIId fol Iii TlmIS in MMI' .... AA.code patternKeyboard Interface ASCII Code ProgramCase ShiftUpper C,.. Logic Counter DrivingControl ICS)No X NCModuloLevel + - ProgramFunctionDevice I 1 III 20 o Counter 4 CMStatic Key Fonn No X NC No. 3 0 4 0 E Counter 6TimingUnitsKey ScanKeyPin No. 2(+) (Alpha)ldon· line Iden·tity T R 8 7 6 5 4 3 2 1 0 tityQ T1 RO 1 1 1 0 1 0 0 0W T1 Rl 1 1 1 0 1 0 1 1E T1 R2 1 1 1 0 0 0 1 0R T1 R3 1 1 1 0 1 0 0 1T T1 R4 1 1 1 0 1 0 1 0y Tl R5 1 0 1 0 1 1 0 0U Tl R6 1 0 1 0 1 0 1 0(511 T1 R7 1 1 1 0 0 1 0 0A T2 RO 1 0 1 0 0 0 0 0S T2 Rl 1 0 1 0 1 0 0 10 T2 R2 1 0 1 0 0 0 1 0F T2 R3 1 1 1 0 0 0 1 1G T2 R4 1 0 1 0 0 0 1 1H T2 R5 1 0 1 0 0 1 0 0J T2 R6 1 1 1 0 0 I 0 1K T2 R7 1 0 1 0 0 I 0 IZ T3 RO 1 0 I 0 I I 0 IX T3 Rl 1 1 I 0 1 1 0 0C T3 R2 I I I 0 0 0 0 1V T3 R3 I 0 1 0 1 0 1 IB T3 R4 I 0 I 0 0 0 0 1N T3 R5 1 0 1 0 0 1 1 IM T3 R6 I 0 I 0 0 I I 0L T3 R7 I I I 0 0 I I 00 T4 RO I I I 0 0 I I 1P T4 RI I 0 I 0 1 0 0 0[ T4 R2 I I I 0 I 1 0 1\ T4 R3 1 0 1 0 I 1 I 0I T4 R4 I I 1 0 I I I 0(5)("> T4 R5 1 I 1 0 I I I I@ T4 R6 1 1 1 0 0 0 0 0(5)- T4 R7 1 0 1 0 1 I 1 11 11 71 %0 20 41 91 51 )1 !1 30 $0 &10 (.0 .1 +00 81 #0 60 "01 -01 I0 01 ;0 0 SPI ?8 71 11 11 11 11 11 01 01 11 01 01 01 11 01 0I 11 01 0I 1I II 0I 0I 0I 01 II 1I 01 11 01 11 II II 0Pin No. 2(-) (Numeric)6 5 4 3 20 1 1 0 00 1 1 0 10 1 0 0 10 1 1 0 00 1 1 0 10 1 1 1 00 1 1 0 10 1 0 1 00 1 0 0 00 1 1 0 00 1 0 0 10 1 0 0 10 1 0 0 10 1 0 1 00 I 0 1 00 I 0 I 00 1 I 1 00 I I 1 00 1 0 0 00 1 I 0 10 1 0 0 00 I 0 1 10 I 0 1 I0 I 0 I I0 I 0 1 10 I 1 0 00 I 1 I 00 1 1 I I0 1 1 I I0 I 1 I I0 1 0 0 00 I I I 11 00 11 10 11 00 00 10 10 10 11 10 01 01 10 01 0I II 00 01 II 01 01 00 10 0I 10 0I 10 00 1I 00 01 1Note 1: A logic "1" or "X" "" "most negative voltilge".Note 2: A logic "0" "" "mos~ positive voltage".Not83: All "Don't Care" cases must be defined as a "1" or "0",Note 4: If less than 9 bits are used unused bits will be programmed logic "1".Note 5: These locations are programmed for clearing the keyboard alarm.Note &: Bit eight (column 7) is odd parity bit for ASCII code shown.6

programming of MM5704Keyboard Scan CycleThe matrix scan cycle includes:Counter advancing through each "T" quadrantline T 1 through T 5 each with D c~untetdelay to charge "T" line capacitance.2 Counter advancing through eight switches ineach "T" quadrant except for T 5 static switchquandrant.3 D counter advances on either system clockI/>IN or Cycle Marker (programmable feature).The keyboard scan frequencywherefscan = Kd + I/>fK = 5 (five T quandrants)d = D counter delay time = (D counter modulusx ;s)r = 33 (Four quandrants times eight switchscans + 1 bit time for T 5 static switchtransfer).I/>t = The frequency at wh ich the clock I/IIN isshifting data through the device.1/1 5 =I/If when D counter driven by I/>f or I/>f/Xwhen x is bit times between Cycle Markers.Key Bounce Delay TimeSince the M counter advances the E counter onceeach complete keyboard scan the modulo of the Ecounter determines the key bounce delayrE . (Kd + if}f)E = modulus of E counterThe key bounce delay time is the total time elapsedfrom the first detected key depression until theload flip-flop signals transfer of the character codefrom ROM to the 9 bit shift register. The E countercontrols the number of times the entire keyboardis scanned before a valid key depression is accepted.Variations in timing are obtained from programmingof the D counter, E counter, I/>f (systemoperating frequencyl and Cycle Marker rep rateprovide flexibility for the keyboard interface elementto interface with a wide variety of keyswitch elements.Idle Key ResetDuring an idle key mode (power on) an automaticreset signal is generated by charging an externalcapacitor C R which enables the control logic todetect first key depression. This reset preventskeyboard lock-up by mass depression of keys orany attempt to void the integrity of the keyboardencoding. As an example, if a person attempts tohold down three or more keys to force an alarmcondition to repeat, in hopes of voiding the keyboardlogic, as soon as the keys are released andbounce delay timed out the idle key reset enablesthe control logic. The value of the reset capacitoris dependent on the keyboard scan cycle. The valueof the external capacitor is:i1 x t.:CR = -v:;-i1 = average charging current = 1 mAV 1 = reset voltage = 3.0VE+nt.: = charging time interval tc = ~E = modulo of E countern = number of scan cycles beyond bounceout delayI/>f = frequency of clock I/>INStandard Keyboard TimingNational has programmed a keyboard interface elementwith the following conditions:Static Switch Form Normally Open (NO)Device Number one: static Xmit during bittime 5Case shift form Normally Open (NO) (alphacharacters)Character Code ASCII (8 bits with 9th bitodd parity)E counter modulus = 6D counter modulus = 4D counter driven by Cycle Marker CMIdentified as MM5704-AA (see code pattern)Typical ApplicationThe two main questions in most applications are:a. How much key matrix capacitance can becharged?b. What is the key bounce delay time?c. What is value of idle key reset capacitor?Using MM5704-AA in system with following characteristicsI/>t = 200 kHzl/>oUT(PWI = 0.5p.sCycle Marker frequency = I/>f121 (maximum datatransfer case)Key bounce delayrE (Kd +~)1 336 [5(4 x I/>s) + I/>f I6 . [5(4 x 21 ) + 33 I =200 X 10 3 200 X 10 313.5 ms7

programming of MM5704 (can't)o counter is programmed to charge key matrixcapacitanceo counter delay1 21d=4x-=4x

Dynamic Shift Registers*MM400/MM500 series dynamic shift registersgeneral descriptionThe National Semiconductor line of dynamic shiftregisters are built on a single silicon chip utilizingMOS P channel enhancement mode transistors.Designed to operate over a wide frequency spec·trum, these devices can be used in any sequentialdigital system that employs a two phase clockingsystem. The low threshold transistors used permitoperation with a V DO supply voltage of -1 OV anda -16V clock amplitude to obtain these devicefeatures:• Direct DTL or TTL compatibility• High FrequencyOperation• Low PowerConsumption1 MHz guaranteed0.8 mW/bit @ 1 MHz• Minimum OperatingFrequency Guarantee 600Hz @ 25°C• Military and Commercial Temperature RangesMM400 Series -55°C to +125°CMM500 Series -25°C to +70°C• Low Output Impedance (V OH ) 500 ohms• Clock inputs directly compatible with MH0009,two phase clock driverThe power dissipation of the device decreases asthe operating frequency is decreased; at 10kHztypical dissipation is 6 p-W/bit. The minimumoperating frequency is also reduced substantiallyat lower temperatures; typical minimum frequencyof operation at 25°C is 100 Hz.3:.,. 3:oo.........~3:CJ1oenCD...CDenschematic and connection diagramsI-v" ---;-1 - ... ---.. --+-... ---.... --+--.... ----~,U.,IIIOATA=n" I FINPUT TA IT2II AIIGNO~-_t::~~;;~~::::~::~:-:7~~::::j:::~;,;:;.~~n·1 STAGECLOCK ~ ON PIN Jtypical applicationsFIGURE 1 - TTL/MOS Interface- Low Frequency(see clock timing graph for detail)3.9K 3.9KNA BIT REGISTERNil BIT REGISTER3.61

......tnG)G)(I)0010:E:E......00..:E:Eabsolute maximum ratingsDrain Voltage (-Veel+0.5V to-25VClock Inputs (V4>" V4>21 +0.5V to -25VData Inputs +0.5V to -25VPower Dissipation (Note 11500mWOperating Temperature MM400 Series_55°C to +125°CMMSOO Series _25°C to + 70°CStorage Temperature_65°C to +150°Celectrical drive requirementsPARAMETER CONOITIONS MIN TVP MAX UNITSClock Pulse Width See Timing Diagram, Page 3.1 Clock pw 0.4 10.0 ItS~ Clockpw 0.2 10.0 It·Clock Delay. f/jd See Definition 0.1 It·,CloCk Pulse Transition t .... tflt! t MHz, lfipw '" 0.2 ~s 0.05 It·100 kHz, tPpw = 0.2 JlS 0.5 It·10 kHz.lfipw '" lOllS 5.0 It·Clock Input Level (V.)Logic "0" IV.,..I Vss -0.5 Vss -1.5 VLogic "," (Vt/.ILI V. -14.5 Vss -16.0 Vss -18.0 VData Pulse Width tdw 0.4 It·Data Setup Time td. 0.1 It·Data Input Voltage LevelsMOSto MOSLogic "0" IV IH ) Voo '" -TOV. Vss = GND 2.0 VLogic "1" (V,d freq = 1 MHz max. -7.0 VTTLto MOS (Fig. 11Logic "0" IV IH) Voo '" GNO, Vss '" +10V Vss - 2.0 VLogic "1" (V,d freq '" 1 MHz max. Vss -7.0 VTTL to MOS IFig. 21Logic "0" (V'HI Veo '" -5V, Vss '" +5V Vss - 1.5 VLogic "," (V,d(Vss = 4.75 min)freq '" 0.5 MHz max. Vas -4.2 Velectrical characteristics (Note 2)PARAMETER CONDITIONS MIN TVP MAX UNITSClock Repetition Rate See Fig. 2 See Note 5 1.0 MHzSee Fig. 1 See Note 5 0.5 MHzClock Input Capacitancef"" 1.0 MHz, OV Bias(Pins3& 5) MM400, 401, 500. 501 22 40 pFMM402, 403, 502. 503 40 60 pFMM406, 407, 506, 507 85 100 pF-20V BiasMM400, 401, 500, 501 18 25 pFMM402, 403, 502, 503 32 40 pFMM406. 407. 506, 507 55 65 pFData Output Voltage LevelsMOS'0 MOSVoo z -'OV, Vss - GNDLogic "0" (VaH ) freq "" 1 MHz max. Vss -1.5 VInput (d.c.)Logic "1" (VaLlV .. -8.0VVMOStoTTL IFig.l1 Voo == GNO, Vss "" +10Vfreq "', MHz max.Input (d.c.)Logic "0" (VaH)2.5 VLogic "1" (Vad:~ : ~i~6m:A} See Note 60.4 VMOS to TTL (Fig. 21 Voo "" -5V, VSS "" +5V(Vss "" 4.75 minifreq = 0.5MHz max,Logic "0" (VaH )2.5 VLogic "1" (VaLl :~: ~i~6m:A} See Note 60.4 V1.0 IlA Test CurrentTA ==25°COn Pin 1 GND on Pins 2,3,4,5,6,7 -25 V-aVon Pin 8On Pin 2 (Note 3) GND on Pins 1, 4, 6, 7.8 -25 V-8V on Pins 3, 5On Pin 6 (Note 3) GND on Pins', 2, 4, 7.8 -25 V-aVon Pins 3, 5On Pin 7 GND on Pins 1,2,3.4,5,6 -25 V-aVon PinSBreakdown VoltageLeakage Currant TA '" 25°CPin' V, = -18V. Va =-8V 0.5 itA'All Other Pins at GNDPin 2 (Note 4) V2 =' -lSV, V3 = Vs '" -SV 0.5 itAAll Other Pins at GNDPin 6 (Note 4) V6 == -1aV. V3 == Vs ""-8V 0.5 itAAll Other Pins at GNDPin 7 V, = -18V, Va =-8V 0.5 ItAAll Other Pins at GNDPin a (Note 4) Va = -8V 0.5 itAAll Other Pins at GNOPower Supply Current DrainOutPUts at Logic "'"1 MHz Operations, T A ,. 25°CI~, • 0.4 It., ~2 = 0.2 It.IMM400.401.500,501 4.5 9.0 mAMM402,403.502,503 9.0 14.0 (Average)MM406.407.506,507 18.0 30.0No" t: For operating at .I.v.ted temperlltu,..; the dIIvlce must be deratad baMd on +1150oC maximum J"nctJon tamperature end a th.rmal .... ist.nee of 150 0 CIW junction to ambi.nt.The full rating tlPPli.s for c .... mperatures to + 125°C for MM400 Serlo and +70oc for MM500 S.rlel units.NOla 2: Th ... specific_ions apply ov.r the Indlcateet operating temp.rature ran .. s for VSS. OV and -11V

performance characteristicsPower Dissipation vs Maximum Frequency1000~.§ 100z0;:::.... en...10cII:~0...~TAI='~5'CI==voo = -IOVr---v. = -16V -- M~402v.:l~M~06 ~./~MM400=Minimum Operating Frequency10K5K2KN IKe>.... 500zw 200:::>Clw 100:l:50,I'GUARANTEED ~ ~V /TYPICALi/ ./ Voo = -IOV_/ ./ v., = v'" = -16V200.1 10./10 100 1000 -60 -20 20 60 100 140OPERATING FREQUENCY (kHz!TEMPERATURE ('C)c.§I­ZwII:II::::>....I­ :::>I!=:::>oOutput Sink/Source CurrentIr-'--r-,~r-'--r-'--'4~-+--+o 1t:j~::±:±:::::I::=:b::~o -I -2 -3 -4 -5 -6 -1 -8OUTPUT VOL TAGE (VOLTS) (BELOW V •• )3:3:~o.......3:3:U'IotJ)CD.._.CDenPower Dissipation/Bit vs. Supply Voltage Power Dissipation/Bit vs. Clock Amplitude Clock Timing,Direct-Coupled TTL or DTLIJIJ~ 1.4 1--+--I-4--L-I--:: .....""l-i.§1.2I-~ 1.0 I--::r""""t--'o~ 0 .• 1--+--b-4'iii 0.6 1-"''-I---11:...'''I'''-t-+--+-+--lc~ 0.4 1"""-f---1I-+--t-+--+-+--l~ 0.2 I--+-,I-+-'t=--r--t-+--t0'---'--'---'--'---'--'---'---1-I -9 -10 -11Voo (VOLTS)-12~ 1.4.§1.2I-.. D~Z 1.00;:::.•...iii 0.6CII:w 0.4~00.2...0-12 -14 -16 -18 -20CLOCK AMPLITUDE (VOL TS)w..I-'"....0>I-... :::>!!:I-..05.04.03.02.0o ns 200 ns 400 ns 0.6 ~s 0 .• ~s I ~sCLOCK , WIDTHClock Amplitude VI' V2vs. Maximum FrequencyFRED.4.5 - IMHz! ., ., •• UNITS r-:C 4.0 - 1.0 0.4 0.2 0.1 "' f-~ 1.5 0.3 0.2 0.05 "'~ 3.5 - 2.0 0.2 0.2 0.05 "' r-Z 3.0 '- 2.5 0.15 0.15 0.05", f-~ IJ...:::: 2.5 1--+-+-+-t-lI-t-:::; ...."f!='-1--l:l: .........,- I2.0 I-+--+-+",""*""'f'-+-I[-'.II--I--I1.5 1-, ~-+".,"""'/""-+-+-t-t-Voo=-IOV1.0 F""'""--+--II-+--+TEMPERATURE: 25'CFANOUT: ONE REGISTER INPUT LOAD~u ~u ~~ ~u ~~ ~~V.,. V., (VOLTS)~.§l-ii;Z0;:::~iiicII:W~0...Maximum Package Power DissipationBOO400200o-25......... I'-.... .........~25 15 125TEMPERATURE rC)Power Dissipation/Bit vs. TemperatureI .•1.4~.§1.2I-~z 1.00;::: D ••...iii 0.6CII:w 0.4~00.2...-15 -25 0 25 15 125TEMPERATURE ('C)Note: All typical performance data is gathered with pw = 0.4 f.l; 2pw = 0.2 f.lS; d = 0.1 f.ls; f = 1 MHz; except as otherwise noted.operationEach bit of delay shown in the circuit schematic consistsof two inverters T1 and T4 accompanied by clocked loadresistors T2 and T5 and two coupling devices T3 and T6.The circuit functions as follows: When 2 goes negative(one state) the coupling unit TA and the load resistorT2 are clocked ON allowing information at the input tobe transferred to node A turning T1 ON or OFF dependingon the state of the input. For example, if a negativepotential (near -Voo level) is transferred from the inputto the gate to source capacitance at node A, then T1-Vooturns ON allowing node F to be at --2-' When 2 returnsto its zero state (ground level) T2 turns OFF allowingnode F to discharge to zero volts. When 1 goes negative(one state) the coupling unit T3 and the load resistorT5 are clocked ON allowing information at node Fto be transferred to node B. T4 is held OFF if node F wasat ground potential and is turned ON if node F had beenat -Voo potential. Continuing the example above, T4 isheld OFF and node G is at -Voo since T5 is ON during1 clock pulse. When 1 returns to its zero state, node Gmaintains a -Voo voltage level. This voltage level ismaintained at node G until the 2 clock appears. Thebit delay demonstrated in this example is repeatedthrough each half of the dual register.timing diagramNOoEANODE B -",__...INODE CDATAOUTPUTN BIT DELAYII~11

Dynamic Shift Registers~~ MM1402A/MM1403A/MM1404A/MM5024Aoq- 1024-bit dynamic shift register.....~ general description«~Moq-.....~~«~Noq-.....~~The MM1402A/MM1403A/MM1404A/MM5024A1024-bit dynamic shift registers are MOS monolithicintegrated circuits using silicon gate technologyto achieve bipolar compatibility. 5 MHzdata rates are achieved by on-chip mUltiplexing.The clock rate is one-half the data rate; i.e.,one data bit is entered for each ¢, and ¢2 clockpulse.All devices in the family can operate from +5V,-5V, or +5V, -9V power supplies.features• Guaranteed 5 MHz operation• Low power dissipation .1 mW/bit at 1 MHz• DTL/TTL compatible• Low clock capacitance125 pF• Low clock leakage::;:: 1 pA• Inputs protected against static charge• Operation from +5V, -5V or +5V, -9V powersupplies• Four standard configurationsMM1402AMM1403AMM1404AMM5024AapplicationsQuad 256-bitDual 512-bitSingle 1024-bitSingle 1024-bitwith internal 4.7kpull-down resistor• Radar and sonar processors• CRT displays• Terminals• Desk top calculators• Disk and drum replacement• Computer peripherals• Buffer memory• Special purpose computers-signal processors,digital filtering and correlators, receivers, spectralcompressors and digital differential analyzers• Telephone equipment• Medical equipmentconnection diagramsDual-I n·Line PackageMetal Can PackagesOUTPUT 1 16NC 151N1 1413V~ 12DU12 11NC 10IN.NtOU14NCV";,1N3TOP VIEWMM1403Atypical applicationTOP VIEWMM1404ATOP VIEWMM5024AIN2TOP VIEWMM1402AOUT3DTL/TTL to MOS Interface>S,3KINV~UV~.,0.~..·R..3'. ·r '.MMI402A1JAJ4A'"MM511Z4A"" ",~.,U V~V

absolute maximumData and Clock Input Voltagesand Supply Voltages withRespect to V 55Power DissipationOperating Temperature RangeStorage Temperature RangeLead Temperature (Soldering, 10 sec)ratings+ 0.3V to -20V600 mWat TA = 25°C-25°C to +70°C-65°C to +160°C300°Celectrical characteristicsT A = _25° C to +70° C, Vss = 5V ±5%, V DO = -5V ±5% or -9V ±5%, unless otherwise specified.PARAMETERData I nput LevelsLogical LOW Level (V,dLogical HIGH Level (V'H)Data I nput Leakage CurrentInput CapacitanceClock Input LevelsLogical LOW Level (V dLogical HIGH Level (VH)Logical LOW Level (V dLogical HIGH Level (VH)Clock Leakage CurrentClock CapacitanceData Output LevelsLogical LOW Level (VodLogical HIGH Level (VOH )Logical LOW Level (VOL)Logical HIGH Level (VOH )Logical HIGH Level (V OH)'Logical HIGH Level (VOH )Power Supply Current (lDD)Data Output Leakage CurrentInternal Resistor (MM5024A)Output CapacitanceCONDITIONSV'N = -15V, TA = 25°C, All Other Pins GNDV'N = VssVDo=-5V±5%V DD = -9V ± 5%Min VL, TA = 25°CV = VssRLl = 3k to V DD , IOL = 1.6 mA, V DD = -5V ± 5%RLl = 3k to VDD,loH = 100MARL1 = 4.7k to V DD , IOL = 1.6 mA, V DD = -9V ± 5%RLl = 4.7k to V DD , IOH = 100 MARL2 = 4.7k to V DD , V DD = -5V ± 5%RL2 = 6.2k to V DD , V DD = -9V ± 5%RL3 = 3.9k to VssT A = 25°C, V DD = -5V ± 5%Output Logic "0", 5 MHzData Rate; 33% Duty Cycle,Continuous Operation, V L = V S5 -TA = O°C17VTA = 25°C, V DD = -9V ±5%Output at Logic "0", 3 MHzData Rate, 26% Duty Cycle,Continuous Operation, VL = Vss - 14.7VT A = O°CVOUT = O.OV, T A = 25°C, Vl = V2 = VS5 - 10V,All Other Pins +5VT A =25°CVOUT = V5S , f = 1 MHzMINVss - 10.0Vss - 1.7Vss - 17Vss - 1Vss - 14.7Vss - 12.42.4Vss -l.6Vss - 1.63.7TYPVV...3:3:nA ~pFV0~l>V3:VV 3:(J'1nA0pFVVVVVVmAmAmAmAnAN~l>ac characteristics TA = -25°C to +70°C, Vss = 5V ± 5%PARAMETERMINVoo = -5V ± 5%MAXVoo = -9V ± 5%MINMAXUNITSClock Frequency (

performance characteristics! 100,.J'a:Q.J'~. 10...wQwen'"~ 1.0!;::IEx 0.1Guaranteed Maximum DataPhase Delay Times vsTemperature (Note 11""'- ¢I>w = 130 nsI- ¢I, = ¢t, = 10 ns'\~ -60 -20 20 60AMBIENT TEMPERATURE, TA (OC)100!... >~:::>'" we:'" ....'"Q::IE:::>i!lzi10klk10010Guaranteed Minimum DataFrequency vs Temperature(Note 1)./ ./¢d OR ¢d = 10 ns:/¢d =¢d - f---¢I>w = 130 ns =¢t, = ¢t, = 10 ns-1-60 -20 20 60 100AMBIENT TEMPERATURE. TA (OC)switching time waveformsMultiplexed 4-Bit MOS Shift RegisterBIT TIMES I BIT 1I BIl2 I BIT 3 8114I I I I I I I I I"-U I LJ LJ LJ I LJ I LJ r-+-I ---lLJ II I I I I I I I I I I I I I" I LJ I LJ I U I LJ I LJ I LJ I U-I I I I I I I I I I I I I I"1" "1"----F""l DATA IN I DA.~rlN fFl I I I I I IDATA IN 1 2"0"II I"1" I I I "1" I I I I I IDATA OUTShown is a simplified illustration of the timing ofa 4-bit multiplexed register showing input outputrelationships with respect to the clock. If dataenters the register at cf>, time, it exits at cf>, time.(8eginning on cf>l's negative going edge and endingon the succeeding cf>2's negative going edge.)timing diagramIBITI IBIT2I81TH8IT"+1 81TN+2BIT IBI12C(OCK'l~_-1 ~: L_[ ,:-U---------~~~I -+1 ~!- I ~ :: II-/Ipw--!--.,~CLOCKPIERIOD I ¢1j-lr -tt--¢t,.:~I",,'14>z II ':II~V,"CLOCK '*1 'j- __ 90% 911% -- l 90% -- ---\It.t.-+-l r-::: I I ~~ I ---l ¢Pw I--DATA PEIUOO--i ::;;;;1. X"------------~~----------r-+-----1------VWi\.iNiiTi'" INBIU l I .... H -I \-- --I r-- IpoII. Vl~;,.:;:;;.;------------------f~----------"CVOH-------------;lIl--------I\-oiiTii;;-J OUTBITZ VOL14

Dynamic Shift RegistersMM4001A/MM5001A dual 64-bit dynamic shift registerMM4010A/MM5010A dual 64-bit accumulatorgeneral descriptionThe MM4001A/MM5001A dual 64-bit dynamicshift register is a monolithic MOS integrated circuitutilizing P-channel enhancement mode lowthreshold technology. The device consists of two64-bit registers with independent two phase clocksand is guaranteed to operate at a 2.5 MHz operatingfrequency for CRT display appl ications.The MM401 OA/MM501 OA is a dual accumulatorfunction capable of operating at very high frequency.The device is also constructed on a singlesilicon chip utilizing MOS P-channel enhancementtransistors. With the recirculate control line at anMOS logic "0" state, the device functions as anaccumulator. A logic "1" state at the recirculatecontrol line allows external information to enterthe register serially. It is important to note thatrecirculation of data is performed internally, independentof the output circuit thus making itinsensitive to output loading.features• High frequency operation 3.3 MHz typ• Low power consumption 0.4 mW/bit at 1 MHz• DTLlTTL compatibility +5V, -12V powersupplies, push-pulloutput stage• Minimum operating frequency guaranteed250 Hz at 25°C• Application versatility "Split clock" opera-tion, independentcontrol of eachregister forMM4001 A/MM5001 Aapplications• Business machine• CRT refresh memory• Delay line memory• Arithmetic operations3:3:~o-l>.......3:3:C1Io-l>3:3:~o-ol>.......3:3:C1Io-ol>connection diagramsload control truth tableMM4001A1MM5001AMM4010AlMM5010AMM4010A/MM5010ALOGICAL HIGH LEVEL(VLCH )Recirculates "old" dataLOGICAL LOW LEVEL(VLcdLoads" new" dataNola: Pin 5 ~onllll£tedto~lI$Ii.TOPI,fIEWNote: Pin 5 connected IDcase.TOP VIEWtypical applicationsMM4001A/MM5001A TTL/MOS InterfaceMM4010A/MM5010A TTL/MOS InterfaceI MM4010A/MM5010AL.:---------v-;;;,r' ..-1211 9)N \'>oUT15

«o ....oLC'):E:E.......«.... oo-.::t:E:E«....~oLC'):E:E.......«....o-.::t:E:Eabsolute maximum ratingsVoltage at Any PinOperating Temperature RangeMM4010A/MM4001 AMM5010A/MM5001AStorage Temperature RangeLead Temperature (Soldering, 10 sec)electrical characteristicsVss + 0.3V to Vss - 22V_55°C to +125°C-25°Cto +70°C-65°C to +150°C300°CT A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ±1 0%, unless otherwise stated.PARAMETERData Input LevelsLogical HIGH Level (V,H )Logical LOW Level (V IL)Data Input LeakageData Input CapacitanceLoad Control I nput LevelsLogical HIGH Level (V LCH)Logical LOW Level (V LCcILoad Control I nput LeakageLoad Control Input CapacitanceClock Input LevelsLogical HIGH Level (V~H)Logical LOW Level (V ~cIClock Input LeakageClock Input CapacitanceData Output LevelsLogical HIGH Level (VOH )Logical LOW Level (VOL)Power Supply CurrentIGGClock Frequency (1),)Clock Pulsewidth (r/>pw)Clock Phase Delay Times (¢d,¢d)Clock Transition Times (cPtr, 4>tf)Partial Bit Times (T)I nput Partial Bit Time (TIN)Output Partial Bit Time (TOUT)Data Input Setup Time (tdS)Data Input Hold Time (tdh)Load Control Input Setup Time(tLes)Load Control Input Hold Time!tLCh)Data Output Propagation DelayFrom cPOUTDelay to HIGH Level (tpdH )Delay to LOW Level (tpdL )CONDITIONSV ,N = -20V. T A = 25°CAll Other Pins GNDV ,N = O.OV, f = 1 MHz,All Other Pins GNDNote 2V ,N = -20V, T A = 25°CAll Other Pins GN DV ,N = O.OV, f = 1 MHz,All Other Pins GNDNote 2Vr/> = -20V. T A = 25°C,All Other Pins GN DVr/> = O.OV, f = 1 MHz,All Other Pins GNDMM4001A/MM5001AMM401OA/MM501OA Note 2'SOURCE := -0.5 rnAISINK = 1.6 mAT A = 25°C, VGG = -12V,r/>pw = 150 ns, Vss = 5.0V,Vr/>L = -12V, Data=0-1-0-10.01 MHz ~ r/>, ~ 0.1 MHzr/>, = 1 MHzr/>, = 2.5 MHz¢tr "" 4>1f = 20 ns, Note 1r/>t, + r/>pw + r/>t, ~ 1O.51'sNote 1r/>t, + r/>pw + r/>t, ~ 10.5 lISNote 1See ae test circuitMINVss - 2.0Vss -1S.5Vss - 2.0Vss - lS.5Vss - 1.5Vss - 18.52.40.010.15100.200.20SO20SO20TYP1734MAXVss + 0.3Vss - 4.20.01 0.53.0 5.0Vss + 0.3Vss - 4.20.01 0.53.0 5.0Vss + 0.3Vss - 14.50.05 1.02.03.05.03.330o30o1501502040Vss0.43.04.57.02.510100100200200UNITSvVI1ApFvVI1ApFpFpFVVmAmAmAMHzlISnsI'sI'snsnsnsnsnsnsNote 1: Minimum clock frequency is a function of temperature and partial bit times. TIN and TOUT.as shown by the

performance characteristics-;:r~... >zw:::.0wff:... '":l...::;::::.::;:;;;:il101.00.1Guaranteed Minimum ClockFrequency vs Temperature(Note 1)r- T'N DR TOUT = 200 nsV" t'TIN = TOUTV"0.01-60 -20 20 60 100 140TEMPERATURE (,C)-or..s...::>0....i,:::;::::.::;:X< ::;:100101.0Guaranteed Maximum TINand TOUT vs Temperature(Note 1)..........I ......0.1-60 -20 20 60 100TEMPERATURE ('C)140Typical Power Supply Currentvs Clock Frequency10.0_.3.0 I-+tttttltl-l-n;I~II-'" ~e­ETAI=12~~ 125'C-;; 1.0.!:~=150ns0.3 -t-t+1Ittflf- Vss = 5.0V-t-tt1Itt1tf- VGG = -12.0VV~L = -12.0VDATA = 0-1-0-10.10.001 0.01 0.10 1.0 10.0CLOCK FREQUENCY, ~f (MHz)5.0Typical Power Supply Currentvs VoltageTypical Data Output SourceCurrent vs Data OutputVoltage12Typical Data Output SinkCurrent vs Data OutputVoltage4.54.0_ 3.5

Dynamic Shift Registers.....enoLn:?j:?j....en....o.q-:?j:?jMM4007/MM5007 dual 100-bit mask programmable shift registerMM4019/MM5019 dual 256-bit mask programmable shift registerMM4006A/MM5006A dual 100-bit shift registergeneral descriptionThe MM4007/MM5007 and MM4019/MM5019 aremonolithic dual 100-bit and dual 256-bit,dynamicshift registers utilizing P-channel enhancementmode technology to achieve bipolar compatibility .The length of the registers may be varied at manufactureby the altering of the metal mask providingcustom length of both registers. Additional connectionbetween registers may be accomplished at themetal mask to provide single shift register lengthsof up to 200 or 512-bits, with or without anappropriate tap provided at the juncture. TheMM5006A is an MM5007 programmed as a dual100-bit shift register.For the MM4007/MM5007 N = 20 to 100 bitsFor the MM4019/MM5019 N = 40 to 256 bitsSTANDARD LENGTHS:MM4006AMM4007/AAMM4019Dual 100-bitDual 80-bitDual 256-bitCUSTOM LENGTHS:The programmed sh ift registers are assigned a lettercode for each option. These are designated by apair of letters after the number code but beforethe package designation such asMM5007/AA/Hwhich is a -25°C to +70°C dual 80-bit dynamicshift register in the TO-99 package. Pattern codesare assigned by National upon initial order entry.See MOS Brief 14 for a more detailed descriptionof the custom mask.features• Bipolar compatibility• Mask programmable lengthMM4007/MM5007MM4019/MM5019• Low clock capacitanceMM4007/MM5007MM4019/MM5019Standard +5V, -12Vpower suppliesdual 20-100 bitsdual 40-256 bits65 pF max125 pF max• Standard clock frequency 250 Hz mintypicalat 25°C2.5 MHz maxguaranteedover temp• Full temperature rangeMM4007,MM4019MM5007,MM5019applications• Custom shift registers• CRT recirculate display-55°C to +125°C-25°C to +70°Cconnection diagramsDual-In-Line PackageMetal Can PackagesOPTION A,OUTPUT B CONNECTED TO INPUT A OPTION 810UTPUT A CONNECTED TO INPUT 8v" VGGDATA OUT 2 6 TAPoOT TAPOUT 2 6 DATA OUT(OPTIONAL) (OPTIONAL)TOP VIEWNote: Pin1connRtedtouse.v"TOP VIEWNote: Pin 4connectedtllClise.Standard ConnectionTOP VIEWTOP VIEWNote: Pin 4 connected to case.Note: Pin 4 connetted to case.Optional Connections18

absolute maximum ratingsVoltage at Any PinOperating Temperature RangeMM4006A,MM4007,MM4019MM5006A,MM5007,MM5019Storage Temperature RangeVSS + 0.3V to Vss - 22V-55°C to +125°C_25°C to +70°C_65°C to +1 50°Celectrical characteristicsTA within operating temperature range, Vss = 5.0V ±5%, VGG = -12.0V ±10%, unless otherwise noted.PARAMETER CONDITIONS MIN TYP MAX UNITSData Input LevelsLogical HIGH LevelIV,HI Vss - 2.0 Vss + 0.3 VLogical LOW Level IV,eI Vss - 18.5 Vss - 4.2 VData I nput Leakage Y'N = -20V, TA = 25°C, 0.D1 0.5 IlAAll Other Pins GNDData I nput Capacitance Y,N = O.OV, I = 1 MHz, 3.0 5.0 pFAll Other Pins GNDINote 11Clock Input LevelsLogical HIGH LevellV¢H1 Vss - 1.5 Vss + 0.3 VLogical LOW Level IV ~LI Vss - 18.5 Vss - 14.5 VClock I nput Leakage V¢ = -2.0V, TA = 25°C, 0.05 1.0 IlAAll Other Pins GNDClock Input CapacitanceV~ = O.OV, I = 1 MHz,All Other Pins GNDINote 11MM400SA/MM5006A &MM4007/MM5007 50 S5 pFMM4019/MM5019 95 125 pFData Output LevelsLogical HIGH Level (VoHI ISOURCE = -0.5 mA 2.4 Vss VLogical LOW Level (Voel ISINK = l.S mA 0.4 VPower Supply CurrentIGGTA = 25°C, VGG = -12V,

performance characteristicsN~ '"> u... '"... '" co~..u...cou:Ii:Ii '"Ziii101.00.1Guaranteed Minimum ClockFrequency vs Temperature(Note 2) .-- T,N .r TOUT" 200 n.~ VT,N" TOUT - --'" V -100! ..J 10Z,.:-:Ii'" ~ 1.0:!iGuaranteed Maximum TINand TOUT vs Temperature(Note 2)....".0.01 0.1 l""'l-60 -20 20 60 100 140-20 20 60 100 140AMBIENT TEMPERATURE rC)TEMPERATURE (OC)'"'"Typical Data Output SourceCurrent vs Voltage1~ 4 r--1--~--~~~~~~z...0:0:...U'"U0:'"'"4 -I1!2 ...Typical Power Supply Current vsTypical Data Output SinkVoltage MM4006A/MM5006ACurrent vs VoltageMM4007/MM500712 ~~--~--~---r---r--~ 100:0:'" u~ 4 1---j----+---+---+.~.::"""""""--1enVss = S.OV....54....-TA-;t;JVGG = -12.0V --+--+---1---1 ... -o V~L "-12.0V4-I 14IS-55°C~" 25°C--rT I16-i--"" --I-"""-r-17 1810Typical Power Supply Currentvs Voltage MM4019/MM5019JJr--~5oJt11r-.....--r r-- .J....I.--II25:CI II I(Jf- 1.OMHz¢row: 150ns--Vss 0 5.0V _V"L'" -12.0VDATA = 0-1-0-1-I- TA " 25°C543 1- ~-19 14 15 16 17Vss - VGG (VI18 19C.§2 "10.03.01.00.30.1Typical Power Supply Currentvs Clock Frequency MM40191MM5019~ -SSoC~~i'l TA " 25°C12~r-r-0.001 0.01 0.10 1.0switching waveformsr-CLOCK FREQUENCY, ~f (MHz)10.03.0c.§ 1.0j0.30.1Typical Power Supply Current vs ClockFrequency MM4006A/MM5006AIMM4007/MM5007!/>row-150nsvss'" 5.0VvGG =-12.0YVL '" -12.OVDATA o Il-HI-l0.001 0.01 0.10 1.0 10.0CLOCK FREQUENCY.~f (MHz)ac test circuit~NCLOtIC+5V4K~!~ouTCLOCI{-------,IDATA OUTPUT-~'.. t -I ,.~" ..., .UV '-__________ ~T10pF20

Dynamic Shift RegistersMM4012/MM5012 dual 256-bit dynamic shift registergeneral descriptionThe MM4012/MM5012 dual 256-bit dynamic shiftregister is a monolithic MOS integrated circuitusing P-channel enhancement mode technology toachieve bipolar compatibil ity. The device providesfull read/write control, recirculate logic andan independent wire-OR-able TRI-STATETM outputwhich allows a common output bus-line to beconnected between several registers.The input logic allows recirculating both registersor recirculating either register while loading theother from the data bus input, wh ich along withthe TRI-STATE bus output, is enabled by a 2·input NOR gate wh ich allows multiple addressdecoding. N-bits may be added to the recirculateloop by connecting additional shift registers betweenoutputs A or B and data inputs A or B.features• Bipolar compatibility +5 V, -12V operationNo pull-upor pull-downresistors requ ired• Wide frequency range f min = 400 Hz at 25°Cf max = 2.5 MHz overtemperature guaranteed• TRI-STATE output Common bussystems may bebuilt using wire-ORoutput• System flexibility Chip contains all recir-culate logic, controllogic and shift registerfor disc and drumreplacement memoriesapplications• Disc and drum memory replacement• CRT refresh memory• Serial and parallel data storagelogic and connection diagramsDual-I n-Line PackageOA"!"AINPUTA 1OUTPUT A ZoUTPu~:~~~gi 3OUTPUT ENABLE 4OUTPUT B 515

absolute maximum ratingsVoltage at Any PinOperating Temperature MM4012MM5012Storage Temperature RangeLead Temperature (Soldering. 10 sec)Vss + 0.3 to VSS - 22_55°C to +125°C-25°C to +70°C-65°C to +150°C300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ± 10%, unless otherwise noted.PARAMETERCONDITIONSMINTYPMAXUNITSData Input LevelsLogical HIGH Level (V IH )Logical LOW Level (V.dVss - 2.0Vss + 0.3Vss - 4.2VVData Input LeakageVIN ""- -2D.DV, TA '" 2SoC,All Other Pins GND0.010.5)J.AData Input CapacitanceVIN '" D.DV, f '" 1 MHz,All Other Pins GNDNote 25.0pFControl I nput Levelslogical HIGH Level (VCH )Logical LOW Level (VcdVss - 2.0Vss + 0.3Vss - 4.2VVControl I nput LeakageVIN '" -20.0V, TA == 25°C,All Other Pins GND0.010.5)J.AControl Input CapacitanceVIN '" O.OV, f "" 1 MHz,All Other Pins GNDNote 27.010.0pFClock Input LevelsLogical HIGH Level (V lPH )Logical LOW Level IV¢dVss -l.5Vss - 18.5Vss + 0.3Vss - 14.5VVClock Input LeakageVq,""-20V,TA = 25°C,All Other Pins GND0.051.0)J.AClock I nput CapacitanceVI/> '" O.OV, f '" 1 MHz,All Other Pins GNDNote 2110125pFData Output LevelsLogical HIGH level (VOH )Logical LOW Level (VoLIISOURCE'" -0.5 rnA'SINK = 1.6 rnA2.4Vss0.4VVData Bus Output LeakageVss - 5V -:;:: Bus V OUT S;; VssBus Output Disabled, T A == 2SoC10)J.APower Supply CurrentIGGTA "" +25°C, VGG "" -12V,¢pw'" 150 ns, Vss == +5.0V,V¢L "" -12V, Data"" 0-1-0-1Clock Frequency (

performance characteristics!...:IE;::..10010:>0lī,.::IE:IE = 1.0)(co::IEGuaranteed Maximum PartialBit Times vs Temperature (Note 1)"-'"~0.1-60 -20 20 60 100AMBIENT teMPERATURE rC)140Guaranteed Minimum ClockFrequency vs Temperature (Note 1)10-& T'N OF TOUT = MINIMUM... ~ 1.0iii" II"...II

logic table (Notes 3,4)MOOEREGISTERSELECTCONTROLENABLECONTROLSFUNCTIONPIN 9PIN 10 PIN 11INPUTSELECTIONI0I0001oooA Register to A input, 8 Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputA Register to A input, B Register to B inputB Register to Data Bus input, A Register to A inputA Register to Data Bus input, B Register to B inputPIN 3PIN 4PIN 13OUTPUTSELECTIONTRI-STATETM output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTRI-STATE output in high impedance stateTAl-STATE output connected to A RegisterTRI-STATE output connected to B RegisterNote 3: The outpUl control. are sampled bV IN' The TRI·STATE output mu.t be enabled ordi.abledduring the tPlN clock time prior to the roUT clock time at which the output is expected to be true orin the high impedance state. See timing diagram. Two bus~connected devices may be in opposite lowimpedance states simultaneously without damaging either.Note 4: Data Input and Input Control Setup and Hold Times are referenced to the trailing edge oftPIN. whereas the Output Control Timing is referenced to the leading edge of tPIN. See timing diagram.24

Dynamic Shift RegistersMM4013/MM5013 1024-bit dynamic shift register/accumulatorgeneral descriptionThe MM4013/MMS013 1024-bit dynamic shiftregister/accumulator is an MOS monolithic integratedcircuit using P-channel enhancement modelow threshold technology to achieve direct bipolarcompatibility_ There is on-chip logic to load andrecirculate data, and a read control for enabling thebus-ORableTRI-STATETM push pull output stage.features• Bipolar compatibility Standard +SV, -12Vpower suppliesNo pull down orpull up resistorsrequired• Package option TO-99 ormolded 8-pin mini-DIP• Low clock capacitance 160 pF max• Wide frequency range rf>f min = 400 Hz @2SOC typrf>f max = 2.S MHzover temp. guaranteed• Built-in recirculate Exclusive-OR andrecirculate loop on-chip• TRI-STATE output Allows wire-OR busstructure on output• Full temperature operationMM4013MMS013applications-SSOC to +12SoC- 2SoC to +70°C• "Silicon Store" replacement for drum and discmemories• File memories• CRT refreshconnection diagramsTO-l00 PackageDual-In-Line PackageVooWRITECONTROLDATAINAEADCONTROL\flOUT 36 OUTPUTV"TOP VIEWV" 4TOP VIEW5 III.".typical applicationsTTL/MOS Interfacetruth tableL~.£~.JIIL-----"~F·~----.J.r.. .-------------,.~ IIII I.'-1III2--1 MM40UIMM5CIl IL - - - - - '1'= ----- .J(Positive Logic)Logic "1" = V,H = Logical HIGH LevelLogic "0" = V'L = Logical LOW LevelWRITE READ FUNCTION0 00 11 01 1RecirculateOutput DisabledRecirculateOutput EnabledWrite ModeOutput DisabledWrite ModeOutput Enabled-12V.'111%2S

absolute maximum ratingsVoltage at Any Pin Vss + 0.3 to Vss - 22Operating Temperature Range MM4013-S5°C to +12SoCMMS013- 2SoC to +70°CStorage Temperature Range-6SoC to +lS0°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ± 10%, unless otherwise noted.PARAMETER CONDITIONS MINData I nput LevelsLogical HIGH Level (V'H) Vss - 2.0Logical LOW Level (V,e!Vss -18.SData I nput LeakageV ,N ' -20.0V, TA • 2SoC,All Other Pins GNDData I nput CapacitanceY'N • O.OV, f· 1 MHz,All Other Pins GNDControl Input Levels(Note 1)Logical HIGH Level (VHI Vss - 2.0Logical LOW Level (Ve! Vss - 18.5Control Input LeakageY'N • -20.0V, T A • 25°C,All Other Pins GNDControl Input CapacitanceV ,N • O.OV, f· 1 MHz,All Other Pins GNDClock I nput LevelsINote 11Logical HIGH Level (V.H )Vss - I.SLogical LOW Level (V.e! Vss - 18.5Clock Input LeakageV.' -20.0V, TA • 25°C,All Other Pins GNDClock I nput CapacitanceV.' O.OV, f· 1 MHzAll Other Pins GNDData Output Levels(Note 11Logical HIGH Level (VoHI 'SOURCE = -0.5 rnA 2.4Logical LOW Level (Voe!'SINK = 1.6 rnAData Output Leakage VOUT ' -5.0V, T A • 25°COutput in Highlmpedance StatePower Supply CurrentIGGTA = 25°C, VGG ' -12V,¢pw' ISO ns, Vss' 5.0V,V.L • -12V, Data' 0-1-0-10.01 MHz:'O: 41,:'0: 0.1 MHz41, • 1.0 MHz41,' 2.5 MHzClock Frequency (41,1 ¢t,' ¢t,' 20 ns, (Note 21 0.01Clock Pulsewidth (¢pwi ¢t, + ¢pw + ¢t,:'O: 10.5 j.lS 0.15Clock Phase Delay Times (¢d, iFd) (Note 2) 10.0Clock Transition Times (¢t,. ¢tf)¢t, + ¢pw + ¢t,:'O: 10.5 j.lsPartial Bit Times (T) (Note 21Input Partial Bit Time (TIN) 0.2Output Partial Bit Time (TOUT) 0.2Data Input Setup Time (tds) 80Data Input Hold Time (tdh) 20Write Setup Time (!OUTDelay to HIGH Level (tpd')Delay to LOW Level (tpdo)Propagation Delay FromRead Control Disable toHIGH Impedance State:Delay From HIGH level (t1H)Delay From LOW Level (toHIPropagation Delay FromRead Control Enable toLOW Impedance State:Delay to HIGH Level (tH')Delay to LOW Level (tHO)(see ac test circuit)TYP1400.D13.00.013.00.051.605.310.3303.30300150150150ISO150150MAXUNITSVss + 0.3VVss - 4.2V0.5 j.lA5.0 pFVss + 0.3VVss - 4.2V0.5 j.lA5.0 pFVss + 0.3VVss - 14.5V1.0 j.lA160 pFVssV0.4 V10.0 j.lA3.0 mA8.0 mA15.0 mA2.5 MHz10 j.lSns1.0 j.ls100 j.lS100 j.lSnsnsnsnsnsns200 ns200 ns200 ns200 ns200 ns200 nsNote 1: Capacitance is guaranteed by periodic testing.Note 2: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT)as shown by the 1>t versus temperature and TIN, TOUT versus temperature curves. The lowest guar·anteed clock frequency for any temperature can be attained by making TIN equal to TOUT' Theminimum guaranteed clock frequency:1¢tlmin) '= TIN + TOUT where TIN and TOUT do not exceed the guaranteed maximums.Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a hightemperature point.26

perform ance characteristicslOOkN= >Guaranteed Minimum ClockFrequency vs Temperature(Note 21I .! I 1 •• 1 / /~ 10k § ~T1N DR TOUT - 200 nsw:::>dw0:~ 1.0kc.J::c.J~ 100:;;Z~10/I!fT'N-ToUT~ ~-60 -20 20 60 100 140AMBIENT TEMPERATURE rC)IGuaranteed Maximum TINand TOUT vs Temperature(Note 21100 __10010Typical Power Supply Currentvs Clock Frequency

Dynamic Shift RegistersMM4015A/MM5015A triple 60+4 bit accumulator/registergeneral descriptionThe MM4015A/MM5015A triple 60+4 bit dynamicaccumulator is a monolithic MOS integrated circuitutilizing P-channel enhancement mode lowthreshold technology. The device consists of threeindependent shift registers with logic to controlthe entry of external data or to recircu late thedata stored in that register. A common two phaseclock is requ ired to operate the device.• Low frequency operation• Low power consumption• Recirculate logic on-chip• BCD correction look ahead tapapplications250 Hz at 25°Cguaranteed0.4 mW/bittypically at 1 MHzfeatures• Data storage registers in BCD arithmetic appl i-• Direct DTL and TTL compatibility No p.ull-upcationsor pull-down • Basic accumulator functionsresistors required • Business machine memory applications• High frequency operation 2.5 MHz guaranteed • Recirculating delay lineconnection diagramDual-I n-Line PackageINPUT! 1 16 VOGLOAOCONTROll 2~-1f--15 OUTPUT IAOUTPUTIB J-+---+-=-------'INPUT 2 4 -I-----f",14 OUTPUT2AlJOUTPUT3ALOAD CONTROl2 5OUTPUl2B 6INPUTJ 1~:>-E:;~+-J;;h--.~ to OUTPUTlBVss 8L'=========="-_~_g LOAD CONTROLJNote Pili 8 conneGted to case.TOPVIEWtypical applicationsTTL/MOS Interface~~, r------I.------, r-I~,r TTl/Dn MM4015AIMM5D15A TTl/OTlI I " I ITypical Arithmetic ConfigurationtOld Cont.ol : ~::: ~~; = ~:::: ~::~.:~.~.A+C ___ S-,A-_A28

absolute maximum ratingsVoltage at Any PinOperating Temperature Range MM4015AMM5015AStorage Temperature RangeVss + O.3V to Vss - 22.0V-55°C to +125°C_25°C to +70°C-65°C to +150°Celectrical characteristicsT A within operating temperature range, Vss = 5.0V ±5%, VGG = -12.0V ±10%, unless otherwise statedPARAMETERCONDITIONSMINTYPMAXUNITSData I nput LevelsLogical HIGH Level (V'H)Logical LOW Level (V,c!Data I "put LeakageV'N = -20.0V. T A = 25'C,All Other Pins GNDVss - 2.0Vss - lB.50.01Vss + 0.3Vss - 4.20.5VV)J.AData I nput CapacitanceLoad Control I nput LevelsLogical HIGH Level (V'H)Logical LOW Level (V'L)V'N = O.OV, f = 1 MHz,All Other Pins GNDSee Note 2Vss - 2.0Vss - 18.53.05.0Vss + 0.3Vss - 4.2pFvVLoad Control Input LeakageLoad Control Input CapacitanceV'N = -20.0V, T A = 25'C,All Other Pins GNDV'N = O.OV, f = 1 MHz,All Other Pins GNDSee Note 20.013.00.55.0!'ApFClock I nput LevelsLogical HIGH Level(Vq,H)Logical LOW Level (Vq,L)Vss - 1.5Vss - 18.5Vss + 0.3Vss - 14.5Clock Input LeakageVq, = -20V, T A = 25'C,All Other Pins GND0.051.0Clock I nput CapacitanceVq, = O.OV, f = 1 MHz,All Other Pins GNDSee Note 245.060.0pFData Output LevelsLogical HIGH Level (VOH )Logical LOW Level (VoelISOURCE = -0.5 mAISINK = 1.6 rnA2.4Vss0.4VVPower Supply CurrentIGGClock Frequency (q,,)Clock Pulsewidth (q,pw)TA = 25'C, VGG = -12V,q,pw = 150 ns, Vss = +5.0V,Vq,L =-12V,Data=0-1-0-10.01 MHz ~ q" ~ 0.1 MHzq" = 1 MHzq" = 2.5 MHzq,t, = q,t, = 20 ns, Note 1q,t, + q,pw + q,t, ~ 10.5)J.s0.010.152.24.57.03.33.05.58.52.510.0mAmAmAMHzClock Phase Delay Times (q,d, ;Pd) Not. 1Clock Transition Times (q,t" q,t,) q,t, +

performance characteristics~~>...zw:::Ilil..e:...~...::;;:::I::;;z:Ii101.00.1Guaranteed Minimum ClockFrequency vs Temperature(Note 1)- T,N or TOUT = 200 nsV VT,N = TOUT - -0.01-60 -20 20 60 100AMBIENT TEMPERATURE ('CI-140!~;:::...::>0....".=::;;:::I::;;X«::;;100101.0Guaranteed Maximum PartialBit Times vs Temperature(Note 1)"0.1-60 -20 20 60 100AMBIENT TEMPERATURE (OCI14010.03.01" 1.0.2Power Supply Current vsClock Frequency'i ~~rI~11Vss = 5.0VVGG = V¢L = Vss -12.0V0.3

Dynamic Shift RegistersMM4016/MM5016 512-bit dynamic shift registergeneral descriptionThe MM4016/MM5016 512-bit dynamic shift registeris a monolithic MOS integrated circuit utilizingP channel enhancement mode low thresholdtechnology to achieve bipolar compatibility. Aninput tap provides the option of using the deviceas either a 500 or 512-bit register.features• Bipolar compatibility +5V. -12V operationNo pull-up or pull-downresistors required.• Package option TO-l00 or choice of twoDual-I n-Line Packages• Fewer clock drivers required Clock linecapacitance of100 pF typ• System flexibility 300 Hz guaranteed min.operating frequency at 25°C.500 or 512-bit register length.• Military and Commercial Temperature RangesMM4016-55°C to +125°CMM5016_25°C to +70°C• Low power dissipationapplications< 0.17 mW/bitat 1 MHz max.< 30/J.W/bitat 100 kHz typo• Glass and magnetostrictive delay line replace·ment.• CRT refresh memory.• Radar delay line.• Drum memory storage (silicon store)• Long serial memory.connection diagramsMetal Can Package Dual-In-Line Package Dual-In-Line PackageNCNCNCVG.500-81TINPUTNCOUTPUTOUTPUT --,r-:::::I....----'=::--.--- 512-INPUTNC.'N-'-"-'"'-500-INPUTVssNote: Pin 5 connectld to caR.TOP VIEWVssTOPVIEW!;lOUTtypical applicationTTL/MOS Interface+5V;~~::)oi_tl::~::~V.S--------,IIIIL. _____ - T v 7.-------'-IIYNote: The unuMIi input pin must be connected 11:1 Vss-MM40161MM5016 ! I31

.... co0LC):E:E........CO....0~:E:Eabsolute maximum ratingsVoltage at Any Pin Vss + 0.3V to Vss -22VOperating Temperature Range MM4016 -55°C to +125°CMM5016-25°C to +70°CStorage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ±10%, unless otherwise specified.PARAMETER CONDITIONS MIN TYP MAXUNITSData I nput LevelsLogical HIGH Level (V IH ) Vss - 2.0 Vss + 0.3Logical LOW Level (VIL) Vss - 18.5 Vss - 4.2Data Input Leakage V IN = - 20V, T A = 25°C, 0.01 0.5All Other Pins GNDData I nput CapacitanceV IN = O.OV, f = 1 MHz,All Other Pins GND, (Note 2) 3.0 5.0Clock I nput LevelsLogical HIGH Level (V¢H) Vss - 1.5 Vss + 0.3Logical LOW Level (V¢d Vss - 18.5 Vss - 14.5Clock Input Leakage VrfJ = -20V, T A = 25°C, 0.05 1.0All Other Pins GNDClock Input Capacitance VrfJ = O.OV, f = 1 MHz, 100 120All Other Pins GND, (Note 2)Data Output LevelsLogical HIGH Level (VOH ) ISOURCE = -0.5 mA 2.4 VssLogical LOW Level (VOL) ISINK = 1.6 mA 0.4Power Supply CurrentIGGTA = 25°C, VGG = -12V,rfJpw = 150 nsVss = 5.0V, VrfJL = -12V,Data = 0-1-0-10.01 MHz:S: rfJf:S: 0.1 MHz 1.0 2.0rfJf = 1 MHz 3.5 5.0rfJf = 2.5 MHz 7.0 10.0Clock Frequency (rfJf) rfJt, = rfJtf = 20 ns, (Note 1) 0.01 3.3 2.5Clock Pulsewidth (rfJpw) tf = rfJpw + rfJt,:S: 10.511s 0.15 10Clock Phase Delay Times (rfJd, ¢d) (Note 1) 10Clock Transition Times (t" rfJtf) rfJtf + rfJpw + rfJt, :s: 10.511s 1Partial Bit Times (T) (Note 1)Input Partial Bit Time (TIN) 0.20 100Output Partial Bit Time (TOUT) 0.20 100Data Input Setup Time (td,) 80 30Data I nput Hold Time (tdh) 20 0Data Output Propagation DelaySee ac test circuit.from ouTDelay to HIGH Level (tpdH) 150 200Delay to LOW Level (tpdL) 150 200VVI1ApFVVI1ApFVVmAmAmAMHzI1snsI1sI1sI1snsnsnsnsNote 1: Minimum clock frequency is a function of temperature and partial bit times, TI N and TOUT,as shown by the t/>f versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteedclock frequency for any temperature can be attained by making TIN equal to TOUT. The1minimum guaranteed clock frequency is: t/>f(min) =,where TIN and TOUT may notTIN + TOUTexceed the guaranteed maximums.Note 2: Capacitance is guaranteed by statistical lot sample testing.32

performance characteristics10KN= 5K.......>" 2K~ lK::>S 500II:,. 200g 100::;; 50::>::;;Z 20i 10Guaranteed Minimum ClockFrequency vs Temperature(Note 1)MM4016MM5016~- -./ =L..~~ 7- -T'N=ToUT=./ ~ ~ T'N 01 TOUT = 200 ns-60 -20 20 60 100 140TEMPERATURE rC)10050....20.!0- lD0... " 5.0...!:E 2.0::>::;; 1.0;c.. 0.5::;;0.2Guaranteed Maximum TINand TOUT vs Temperature(Note 1)...........I .......MM5016~0.1-60 -20 20 60 100TEMPERATURE rC)MM4016-"'l:"l14010.03.0Typical Power SupplyCurrent vs Clock Frequency-F-.-55°CII.. ~TA = 25°C'1125°C

Dynamic Shift RegistersMM4017/MM5017 dual 512-bit dynamic shift registergeneral descriptionThe MM4017/MM5017 dual 512-bit dynamic shiftregister is a monolithic MOS integrated circuitutilizing P channel enhancement mode low thresholdtechnology to achieve bipolar compatibility.An input tap provides the option of using eitherregister in a 500-bit or 512-bit configuration.features• Standard +5V, -12V supplies Bipolar compatibility.No pull-upor pull-downresistors requ ired.• Package option TO·l00 or Dual-I n-Line Package.• Fewer clockdrivers requiredClock linecapacitance of140 pF typo• System flexibility 400 Hz guaranteedmin. operating frequencyat 25°C. 500 or512-bit register length.• Military and Commercial Temperature RangesMM4017-55°C to +125°CMM5017_25°C to +70°C• Low power dissipationapplications

absolute maximum ratingsVoltage at Any Pin Vss + 0.3 to Vss - 22Operating Temperature MM4017 _55°C to +125°CMM5017 -25°C to +70°CStorage Temperature -65°C to 150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, VGG = -12.0V ±10%, unless otherwise specified.PARAMETER CONDITIONS MIN TYPMAXUNITS3:3:,J:Io0"'"' ~.......3:3:U10"'"' ~Data Input LevelsLogical HIGH Level (VIH ) Vss - 2.0Logical LOW Level (Vld Vss -18.5Vss + 0.3Vss - 4.2VVData I nput Leakage V IN = -20V, T A = 25°C, 0.01All Other Pins GNDData I nput Capacitance V IN = OV, f= 1 MHz, 3.0All Other Pins GND0.5 p.A5.0 pFClock Input LevelsLogical HIGH Level (VH) Vss - 1.5Logical LOW Level (V d Vss -18.5Vss + 0.3Vss - 14.5VVClock Input Leakage V = -20V, T A = 25°C, 0.05All Other Pins GNDClock Input Capacitance V=OV,f=lMHz, 140All Other Pins GNDData Output LevelsLogical HIGH Level (VOH ) ISOURCE = -0.5 rnA 2.4Logical LOW Level (VOL) ISINK = 1.6 rnA1.0 p.A160 pFVss V0.4 VPower Supply CurrentIGGT A = 25°C, VGG = -12V,

perform ance ch a racteristicslOOkN:>~ 10k...::>co...a:::; 1.0k..,~ ..,~ 100:e;;;i10Guaranteed Minimum ClockFrequency vs Temperature(Notes 1 and 21~ ~TI~ o~ TO~T =12001ns L V//1TIN - TOUT ~~100.§ ""10~:>0I-2>= 1.0:e::>:;;X«:;; 0.1Guaranteed MaximumTIN and TOUT(Notes 1 and 2)~I'0.010.1 LJ..JJ..lJ.WL.....L...UJ..LIIII-..l...LL.LWII-..!....LJ.JJ.llII-60 -20 20 60 100 140 -60 -20 20 60 100 140 0.001 0.01 0.1 1.0 10.0AMBIENT TEMPERATURE (OC)"AMBIENT TEMPERATURE (OC)Typical Power SupplyCurrent vs Clock Frequency100 F""-"!""'-"''''''''''''''101.0~SICLOCK FREnUENCY, ¢, (MHz)

MM4018/MM5018 triple 64 -bitdynamic shift registerDynamic Shift Registerss:s:~...oco.......s:s:U'I...ocogeneral descriptionThe MM4018/MM5018 triple 64·bit dynamic shiftregister is a monolithic MOS integrated circuitutilizing P·channel enhancement mode low thresholdtechnology to achieve bipolar compatibility.features• Bipolar compatibility +5V, -12V operationNo pull·up or pull·downresistors requ ired• System flexibility Guaranteed minimumoperating frequency of600 Hz at 25°C• Military and commercial temperature rangesMM4018 -55°C to +125°CMM5018 -25°C to +70°Capplications• Calculator storage register• CRT refresh memory• Serial data storage.connection diagramMetal Can PackageTOP VIEWtypical applicationTTL/MOS Interface+5VANY TTL/OTLOEVICE-12V37

absolute maximum ratingsVoltage at Any PinOperating Temperature Range MM4018MM5018Storage Temperature RangeLead Temperature (Soldering, ~O sec)Vss + O.3V to Vss - 22.0V_55°C to +125°C_25°C to +70°C-65°C to +150°C300°Celectrical characteristics(T A within operating temperature range, Vss; +5.0V ±5% and VGG ; -12.0V ±10%, unless otherwise specified.)PARAMETER CONDITIONS MIN TYP MAXData Input LevelsLogical High Level (V,H ) Vss - 2.0 Vss + 0.3Logical Low Level (V,L ) Vss - 18.5 Vss - 4.2Data Input Leakage V ,N ; -20V, T A; 25°C, 0.01 0.5All other pins GNDData Input Capacitance V ,N ; O.OV, f; 1 MHz, 3.0 5.0All other pins GNDClock Input LevelsLogical High Level (V¢H) Vss - 1.5 Vss + 0.3Logical Low Level (V¢L) Vss - 18.5 Vss - 14.5Clock Input Leakage V, ; -20V, T A; 25°C, 0.05 1.0All other pins GNDClock I nput Capacitance V, ; O.OV, f; 1 MHz, 45 60All other pins GNDData Output LevelsLogical High Level (VOH ) ISOURCE ; -0.5 mA 2.4 VssLogical Low Level (VOL) ,SINK ; 1.6 mA 0.4UNITSVVMApFVVMApFVVPower Supply Current (IGG)T A ; 25°C, VGG ; -12V,¢pw; 0.15Ms, V¢L; -12V0.01 MHz::; ¢t::; 0.1 MHz 2.9 4.5¢t;lMHz 3.8 5.5¢t; 2.5 MHz 5.8 7.0mAmAmAClock Frequency (¢t) ¢tr ; ¢tt ; 20 ns (Note 1) 0.01 3.3 2.5Clock Pulsewidth (¢pw) ¢tt + ¢pw + ¢tr ::; 10.5 MS 0.15 10Clock Phase Delay Times (¢d or ¢d) Note 1 10Clock Transition TimesRisetime (¢tr) ¢tt + ¢pw + ¢tr::; 10.5 MS 2Falltime (¢tt! ¢tt + ¢pw + ¢tr ::; 10.5 MS 2Partial Bit TimesInput Partial Bit Time (T,N) Note 1 0.20 100Output Partial Bit Time (TOUT) 0.20 100Data Input Setup Time (tds) 80 30Data Input Hold Time (tdh) 20 0Data Output PropagationDelay from ¢OUTSee AC Test CircuitDelay to Output High Level (t pdH ) 150 200Delay to Output Low Level (tpdLl 150 200MHzMSnsMSMMSMSnsnsnsnsNote 1: Minimum clock frequency is a function of temperature and partial bit times (T, N and TOUT)as shown by the ¢t versus temperature and T,N, TOUT versus temperature curves. The lowest glJaranteedclock frequency for any temperature can be attained by making T, N equal to TOUT' The1minimum guaranteed clock frequency: q)f(min) ; T T ' where T,N and TOUT do notexceed the guaranteed maximums. IN + OUT38

performance characteristics600Maximum Power Dissipation........... ..................... ,o-25 25 75TEMPERATURE (OC)125Power Supply Current vsClock Frequency10.0 '-o-pw-= '"'15"'0-n-, --rmnr-l...,.,..,."",.....,r-n-mm8.0 Vss = +5V6.0 VGG=-12V" VOL = -12V-7; 4.0 DATA=I·0·1·0.2w'" :;;ZSi1101.00.1Guaranteed Minimum ClockFrequency vs Temperaturei-- T'N DR TOUT = 200 n'V- I'V ~T'N = TOUT -0.01-60 -20 20 60 100TEMPERATURE rC)i---I--140ac test circuitv"OK~'N CLOCKoOU1C1DCK---~,:-.-:.,-:::-

Dynamic Shift RegistersMM4020/MM5020 quad SO-bit dynamic shift registerMM4021/MM5021 triple SO-bit dynamic shift registergeneral descriptionThe MM4020/MM5020, and MM4021/MM5021shift registers are monolithic MOS integrated circuitsutilizing P-channel enhancement mode lowthreshold technology to achieve bipolar compatibility_The MM4021/MM5021 is a metal maskoption of the MM4020/MM5020 which eliminatesone of the 80-bit registers. Power and clock capacitanceare reduced proportionally.features• Bipolar compatibility +5V, -12V operationNo pull-up or pull-downresistors required• System flexibility Guaranteed minimumoperating frequency of250 Hz at 25°C• Military and commercial temperature rangesMM4020, MM4021 -55°C to +125°CMM5020, MM5021 -25°C to +70°Capplications• Calculator storage register• CRT refresh memory• Serial data storageconnection diagramsDual-In-Line Package Metal Can Package Dual-In-Line Packager/lOUT 1 16 VGG

absolute maximum ratingsVoltage at Any Pin Vss + O.3V to Vss - 22.0VOperating Temperature RangeMM4020, MM4021-55°C to +125°CMM5020, MM5021_25°C to +70°CStorage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, VGG = -12.0V ±10%, unless otherwise stated.PARAMETER CONDITIONS MIN TYP MAXData I nput LevelsLogical HIGH Level (V ,H) Vss - 2.0 Vss + 0.3Logical LOW Level (V,d Vss - 18.5 Vss - 4.2Data Input Leakage Y'N = -20V, T A = 25°C, 0.Q1 0.5All Other Pins GNDData I nput Capacitance Y'N = O.OV, f = 1 MHz, 3.0 5.0All Other Pins GND (Note 2)Clock I nput LevelsLogical HIGH Level (V.jJH) Vss - 2.0 Vss + 0.3Logical LOW Level (V~d Vss - 18.5 Vss - 14.5Clock I hput Leakage V~ = -20V, T A = 25°C, 0.05 1.0All Other Pins GNDClock Input CapacitanceV~ = O.OV, f = 1 MHz,All Other Pins GND MM4020 70 90(Note 2) MM4021 55 70Data Output LevelsLogical HIGH Level (VOH ) ISOURCE = -0.5 mA 2.4 VssLogical LOW Level (VaLl ISINK = 1.6 mA 0.4Power Supply CurrentIGGTA = +25°C, VGG = -12.0V,rppw = 150 ns, Vss = +5.0V,V~L = Vss - 17.0V, Data = 0-1-0-1UNITSVVIlApFVVIlApFpFVV3:3:~oNo........3:3:CJ1oNo .3:3:~o....N........3:3:CJ1oN....MM4020/MM5020 0.01 MHz:::; ,:::; 0.1 MHz 2.9 4.4rp, = 1.0 MHz 6.4 8.0rp, = 2.5 MHz 10.1 12.5MM4021 IMM 5021 0.01 MHz:::; ,:::; 0.01 MHz 2.2 2.75rp, = 1.0 MHz 4.8 6.0rp, = 2.5 MHz 7.7 9.6Clock Frequency (rp,) t versus temperature and TIN. TOUT versus temperature curves. The lowest guaranteedclock frequency for any temperature can be attained by making TIN equal to TOUT. Theminimum guaranteed clock frequency is:1

performance characteristics!ji,:Ii'"! 1.0c>

Dynamic Shift RegistersMM508110-bit serial in-parallel out lamp driver/registergeneral descriptionThe MM5081 is a 1 O-bit serial in-parallel out staticshift register. It is a monolithic MOS P-channelenhancement mode device utilizing a low thresholdmanufacturing process. The output circuits weredesigned to interface directly with gas tubes andother high voltage applications and will withstand100V transient voltages and will hold off 55V. Aserial output is provided for cascading of theregisters without additional circuitry_ This deviceutil izes a single phase clock to control the operationof data manipulation.features• High voltage output - -55V guaranteed• Direct control of neon tubes• Dual-In-Line Package• Single phase clock• Serial output for package cascading• Data output - 10 bits in parallelapplications• Electric Sign Boards• Neon Lamp Displays• Test Equipment Displaysblock and connection diagramsCLOCK16VooSERIAL OUTPUT15SERIAL INPUTCLOCK INPUTSERIAL INPUT15MM5DBI16PARALlEl OUTPUT 10PARAllEL OUTPUT 9GND or VssPARALLEL OUTPUT 8SERIAL OUTPUT PARAllEL OUTPUT 7PARAllEL OUTPUT 6\41312"10PARALLEL OUTPUT 1PARAllEl OUTPUT 2PARALLEl OUTPUT JPARAllEl OUTPUT 4PARAllEl OUTPUT 5V"V,,TOP VIEWtiming diagramCLOCK INPUTSERIAL INPUTQt,r----- V",----V"SERIAL OUTPUTID-BIT OUTPUToutput junction testsStress TestLeakage Testr-..... --~~-

absolute maximum ratingsGate Voltage (V G G )Drain Voltage (V D D)Clock Input Voltage (VIP)Data Input Voltage (V IN )Storage TemperatureOperating TemperatureOutput Stress (Parallel Output Lines)- 25V to +O.3V-25V to +O.3V- 25V to +O.3V- 25V to +O.3V-55°C to +125°C-25°C to +70°C-100V (see stress test)electrical characteristics (-25°C to +70°C) (Vss = OV)SYMBOL PARAMETER MIN MAX UNITS CONDITIONV OH Parallel Output Voltage 5 VVGG = Voo Supply Voltage -20.0 -16.0 VIGG Supply Current 6.0 mA Voo = VGG= -20.0V registerloaded alllogical highSerial Inputlevels. Vss = GNDV ,H Logical HIGH Level Vss - 2.5 Vss VV,L Logical LOW Level VGG Vss - 7.0 Vtd• Data Setup Time 400 nstdh Data Hold Time 50 nsSerial OutputVOH Logical HIGH Level Vss - 1.5 Vss VVOL Logical LOW Level VGG Vss - 8.0· VClock AmplitudeV¢H Logical HIGH Level Vss -1.5 Vss VV¢L Logical LOW Level Vss - 20 Vss - 16 VI L Clock Leakage Current 5 pA V¢= -20.0V

Dynamic Shift RegistersMM4104/MM5104 dynamic shift registergeneral descriptionThe MM4104/MM5104 360/359,228/287,40/32bit dynamic shift register is a monolithic MOSintegrated circuit utilizing p-channel enhancementmode low threshold technology to achieve bipolarcompatibility. The register lengths are lengthenedor shortened by hard wiring the length select lineto VGG or Vss. The lengths available are: 40,288, 328, 360, 400, 560, 688; or 32, 287, 319,359, 391, 446, 678.features• DTL/TTL compatibility+5V, -12V powersupply. No pull-upor pull-downresistors requ ired• Multiple length registers Electrically adjustable360/359, 288/287, 40/32 bitregisters• Wide frequency rangeapplications• Data store• CRT displays• Business machine250 Hz min. guar.at 25°C2.5 MHz max. guar.over temp.connection diagramMetal Can PackageDATA OUTPUT 2(40132 OUT)DATA INPUT lA(360.288 IN)VssTOP VIEWtypical applicationsTTL/MOS Interface+5VrL, J_ r------uu........... r--.... 17 1(SHOAT) 0 ,(LONG)VaG Vss+5VNOTE:VGG on pin 3 results in a 28S·bit registerbetween pin 1 and pin 4 and a 281·bitregister between pins 6 and 4. The unusedinput (6 or 7) must be returned to Vss.Also, there is a 32·bit register betweenpins 1 and 2.Vss on pin 3 results in a l60·bit registerbetween pin 7 and pin 4 and a 359·bitregister between pins 6 and 4. The unusedinput (6 or 11 must be returned to Vss.Also, there is a 40·bit register between pins1 and 2.45

absolute maximum ratingsVoltage at Any PinOperating Temperature Range MM4104MM5104Storage Temperature RangeLead Temperature (Soldering, 10 sec)electrical characteristicsVss + 0.3V to Vss - 22V_55°e to 125°e_25°e to 70 0 e-65°e to 150 0 e300 0 e(T A within operating temperature range, Vss = +5.0V, ±5%, VGG = -12.0V ±10%, unless otherwise specified.)PARAMETERData I nput LevelsLogical HIGH Level (VIH )Logical LOW Level (VldData I nput LeakageData I nput CapacitanceLength Select Input LevelsLogical HIGH Level (VLSH )Logical LOW Level (VLsdLength Select Input LeakageLength Select Input CapacitanceClock I nput LevelsLogical HIGH Level (V H)Logical LOW Level (VLlClock I nput LeakageClock Input CapacitanceData Output LevelsLogical HIGH Level (VOH )Logical LOW Level (VoLlPower Supply CurrentIGGClock Frequency (¢,)Clock Pulsewidth (¢pw)Clock Phase Delay Times (¢d, ~d) (Note 1)Clock Transition Time (¢tr' ¢t,)Partial B it Times (T)I nput Partial B it Time (TJN)Output Partial B it Time ITo UT)Data I nput Setup Time (~s)Data I nput Hold Time (tdh)Data Output Propagation Delayfrom ¢OUTDelay to HIGH Level (tpdH)Delay to LOW Level (tpddCONDITIONSVIN = -20.0V, T A = 25°C,All Other Pins GNDVIN = O.OV, f = 1 MHz,All Other Pins GND, (Note 3)VIN = -20V, TA = 25°C,All Other Pins GNDVIN = O.OV, f = 1 MHz,All Other Pins GND, (Note 3)V", = -20V, TA = 25°C,All Other Pins GNDV", = O.OV, f = 1 MHz,All Other Pins GND, (Note 3)ISOURCE = -0.5 mAISINK = 1.6 mATA = 25°C, VGG = -12V, ¢pw = 150 nsVss = 5.0V. V",L = -12V, Data = 0·1-0-10.01 MHz~¢,~O.1 MHz¢tr = ¢t, = 20 ns, (Note 1)¢t, + ¢pw + ¢tr ~ 10.5 JJ.S¢t, + ¢pw + ¢tr ~ 10.5 JJ.S(Note 1)See ac test ci rcu it.¢, = 1 MHz¢, = 2.5 MHzMINVss - 2.0Vss - 18.5VssVss - 18.5Vss - 1.5Vss-18.52.40.010.15100.200.208020TYP850.013.00.016.00.051.53.57:03.330o150150MAXVss + 0.3Vss -4.20.55.0Vss + 0.3VGG0.59.0Vss + 0.3Vss - 14.51001.0Vss0.4·2.55.010.02.510100100200200UNITSvVJJ.ApFvVJJ.ApFvVJJ.ApFVVmAmAmAMHzJJ.snsJJ.sJJ.sJJ.snsnsnsnsNote 1: Minimum clock frequency is a function of temperature and partial bit times, T,N and TOUT,as shown by the

perform ance characteristics]I- ::>0....i,.:::;::>::;x::; '"100101.0Guaranteed Maximum TINand TOUT vs Temperature(Notes 1, 21...."-I"'"0.1-60 -20 20 60 100 140~>-uzw::>:;l~"" u0101.0....u 0.1::;::>::;ZlEGuaranteed Minimum ClockFrequency vs Temperature(Notes 1, 21I-- TIN or TOUT = 200 nsV V~ VTIN = T OUT -0.01-60 -20 20 60 100AM81ENT TEMPERATURE (OC)I--I-14010.03.0Ci'.§ 1.0..!? "0.3Typical Power SupplyCurrent vs Clock FrequencyTA = 25°CI III_55°C f-1=125°C'\ I.-f- ¢pw=150nsVss = 5.0VVGG = -12.0VVOL = -12.0VDA~~,= 0-1-0-10.10.001 0.01 0.10 1.0CLOCK FREQUENCY, ¢I (MHz)10.0Typical Power SupplyCurrent vs V GGTypical Output SourceCurrent vs VoltageTypical Output SinkCurrent vs Voltage5.0Ci'.§..!? "4.54.03.53.02.52.0TA = 25°C\_55°':'-0.- I--I-" ~ I--f.- f.---H-~-~ ~- f-- t- ¢. = 1 MHz¢Pw = 150 nsVss = 5.0VVOL = -12.0V-t::::1.5D~TA =10-1-r-11.015 16 17 18 19Vss - VGG (V)4V OUT (V)-1Ci'.§ 10 k.--I-~_--l--....'" wa:a:::>u'" ""en....~....::>oo5V OUT (V)-1switching time waveformsac test circuitDATA INPUT/LOAD LNPUT4K~!' ..EI~~~= o---4I----4'""""II-.... ~~~~~OUTPUT"OUT CLOCKVss-I.5V___""tDATA OUTPUT---j "," '--I _1.5V '-_______ -'Y,.5V47

Dynamic Shift RegistersMM4105/MM5105 quad 64-bitdynamic shift register/accumulatorgeneral descriptionThe MM4105/MM5105 quad 64-bit dynamic shiftregister/accumulator is a monolithic MOS integratedcircu it utilizing P-channel enhancementmode low threshold technology to achieve bipolarcompatability on input/output and control lines.Anyone of four recirculating shift registers maybe selected, by external logic control, for interrogationat the single common output or forwriting in new data at the common input data line.features• TTL compatability+5, -12V power suppliesno pull up or pull downresistors requiredinternal pull upresistors on inputs• Input bus capability chip select allowscontrol of data entryfrom common bus line• Versatile operationapplications• Oata buffers• Disc/drum memory replacement• Register for arithmetic unitsrecirculation and registerselect logic on-chipconnection diagramMetal Can Packagetruth tableLogic Definition"1" Logical HIGH Level"0" Logical LOW LevelCODING AND MODE TABLEAddress Write Control Chip SelectChip1 2 Write Recir Active InactiveSelect· 0 0 0 1 0 1 10 1 0 1 0 1 11 0 0 1 0 1 01 1 0 1 0 1 0Output levelInputOutput0 01 10 11 1typical applicationr-----------------I-----------------.A, B,B,ADDRES52B.NO.2DATA"WRITECONTROLCHIPSEHeTI• IL ________________ ~I~M~-- ______________ ....JNO.36 vCG-12V48

absolute maximum ratingsVoltage at Any PinOperating Temperature Range MM4105MM5105Storage Temperature RangeLead Temperature (Soldering. 10 seclVss + 0.3V to Vss - 22V_55°C to +125°C_25°C to +70°C_65°C to +150°C300°Celectrical characteristicsT A within operating temperature range. Vss = +5.0V ±5%. VGG = -12.0V ±10%. unless otherwise specified.PARAMETERCONDITIONSMINTVPMAXUNITSData Input LevelsLogical HIGH Level (V,HILogical LOW Level (V1LIVss - 1.5Vss -18.5Vss + 0.3Vss - 4.2vVData Input Leakage (V,L )V ,N = -20V, T A = 25°C,All Other Pins GND.010.5Data I nput CapacitanceChip Select. Write Control andAddress 2 I nput LevelsLogical HIGH Level (VCH )Logical LOW Level (VcdChip Select, Write Control andAddress 2 I nput LeakageV ,N = O.OV, f = 1 MHz,All Other Pins GNDNote 2V ,N = -20V, T A = 25°C,All Other Pins GNDVss -l.5Vss -18.53.00.15.0Vss + 0.3Vss - 4.21.0pFVVChip Select. Write Control andAddress 2 Input CapacitanceData, Chip Select. Write Controland Address 2 Input Pull·upResistanceV ,N = O.OV, f = 1 MHz,All Other Pins GNDNote 2Vss = 5.0VVGG = -12.0VV ,N = 0.5VTA = 25°C3.0156.0209.0pFClock Input LevelsLogical HIGH Level (V"H)Logical LOW Level (V q,L)Vss - 1.5Vss -18.5Vss + 0.3Vss -14.5VVClock Input LeakageV¢ = -20V, TA = 25°C,All Other Pins GND0.51.0MAClock I nput CapacitanceData Output LevelsLogical HIGH Level (VoHILogical LOW Level (VOL)V¢ = O.OV, f = 1 MHz.All Other Pins GNDNote 2'SOURCE = -0.5 mAISINK = 1.6 rnA2.4100Vss0.4pFVVPower Supply Current IGGClock Frequency (

performance c ha racte risticsac test circuit,..10u;:5 1.0... aII:...u~ 0.1u~!2:iii 0.01-60Guaranteed Minimum ClockFrequency vs Temperature(Note 1)T'N 0' TOUT = MINIMUMV VVT,N = TOUT-20 20 60 100 140AMBIENT TEMPERATURE (OC)100]§ 10l­i,.::Ii!:::>~ 1.0~0.1Guaranteed Maximum PartialBit Times vs Temperature"-20'"20 60 100 " 140TEMPERATURE (OC)1DPFT"::' ":"timing diagramsFor Writing DataFor Reading Data...CHIPSELECT.RADDRESSDATAOUTPUTExplanation of Timing DiagramsIn order to write·in or read· out of the MM4105/MM5105, the chip select line must be low duringthe appropriate clock cycle. If the chip select line isheld high during the rfJOUT clock pulse the outputwill go high. If it is high during rfJlN time, data maynot be written in. The timing diagram shows thatin order to read from a register all inputs must bestable during rfJlN time. To write information, thewrite control and chip select must be held low.The address lines and data will depend on whatregister is to be selected and what information isto be stored. When the write control line is highthe information stored in the registers is recir·culated.To read information out chip select must be lowand address lines stable during the rfJOUT clock.Information is always recirculated in the fourregisters unless chip select and the write controlare low. Then, depending on which address isselected, only three registers are recirculating whilethe selected register is receiving new data.It is possible to write into and read out of thesame register during one clock period. To writeinformation into the register, chip select and writecontrol are held low during the rfJlN clock. Dataand the address lines must be stable during thesame rfJlN clock. During the next rfJOUT clock time,'chip select is held low with the address unchanged.An output will appear from the same register.To write information into one register and readout of a second register during one clock periodsimilar timing can be used. The address can bechanged between the rfJlN and rfJOUT clocks toselect either of the other three registers.50

Static Shift Registers*M M404/M M S04 dual16 bit static register*MM40S/MMSOS dual 32 bit static registergeneral descriptionThe National Semiconductor line of MOS staticshift registers are monolithic integrated circuitsutilizing P-channel enhancement mode transistors_The use of a low threshold technology Permitsoperation with a V DD supply voltage of -10 voltsand a V GG supply and clock amplitude voltage ofless than -16 volts. These registers require only asingle clock input to operate from DC to 1 MHzin either synchronous or asynchronous systems.Each register cell is designed specifically to avoidrace conditions during latching, thus insuringoperation under all conditions specified in theelectrical characteristics.Additional features include:• Bipolar compatibility• Single phase clock input• High frequency operation1.0 MHz• Low power consumption 1.7 mW/bit typ• Output impedancl3 (V OH )500Q typ• Military and commercial temperature rangesMM404 MM405 _55°C to +125°CMM504: MM505 -25°C to +70°C~~~oc.n........~~c.noc.nschematic and connection diagrams20KIII15K I,'2,6DATA'OUTPUTVDD,I,cLoci'+'---l'-----.::....-----+-..... ---------~¢ IVaNot.: Pin 4 connecttd to CI.Top Viewtypical applicationsTTL/MOS Interface- -+lDVr-T~I 3'3. V" r-1-1I ~I~~~ I-~ __ ~I~ IIw NA BIT REGISTERI I 1-__ --1I ICLOCK V'h REQUIREMENTS WITH Vss" .,DVlOGIC "0"lOGIC"1"Single 2N Bit RegisterNs BIT REGISTERVssVss -1.5VVss-16V-6VDATA OUTPUT2N Bit Johnson Counter*DrII1 : &:9 IIIII~-------~NOTE: CI'If rllist. to .1 "0" bet .... CGunti,..by .pplyi .. "'" to d .... input .nd dockilllthrough 2N dock cydn.VooGND>il-;~~§~~~=l:t"0IVIOE IBYVo.Waveforms for Applications(complete timing diagrams on page 53),CLOCK ¢ OV ---, r-1 h r-1 r-1 ....-l&V U Lf U U UI....--j.TYPICAL DATA IN -z. 5V ""l I ~\-1.0V~TYPICAL DATA OUT -1.5V "'N"'B"'IT"'O"'EL"'A"'Yo¥---I/ .... """\­.... OV .::....::..:....::=.:......!\;;;;:;-S-.---'_Io.=I2N OUTPUT*For New Designs, see MM4040/MM5040. MM4050A/MM5050A.51

absolute maximum ratingsDrain Voltage (Voo )Gate Voltage (V GG)Clock I nput (V 1 )Data InputsPower Dissipation (Note 1)Operating Temperature MM404, MM504MM405, MM505Storage Temperature+0.5V to -25V+0.5V to -25V+0.5V to -25V+0.5V to -25V300 mW-55°C to +125°C-25°C to +70°C-65°C to +150°Celectrical drive requirements (Note 1)PARAMETERClock pulse WidthH"Vss -0.5 Vss -1.5Logic "V4>L" Vss -14.5 Vss -16.0 Vss -lB.OData Input Voltage LevelsLogic "V'HLogic "V'L"Data Setup Time, td,Data Hold Time, tdhVss -7.00.20.03Vss -2.5UNITS/lS/lS/lS/lSVVVV/lS/lSelectrical characteristics (Note 2)PARAMETERCONDITIONMINTYPMAXClock Repetition Rate Fan·Out "1"dc1.0Data Output Voltage LevelsLogic "VOH Vss -1.5Logic "VOL"Vss -B.OData Input Capacitance f = 1 MHz 1.53.0(Each Input)Y'N = OVClock line Capacitance f = 1 MHz, -20V Bias MM404, MM504 9.5MM405, MM505lBOV Bias MM404, MM504 15.0MM405, MM505 25Output Impedance Outputs at Logic "0" 0.5Output I mpedance Pins 2 & 6 Outputs at Logic" 1" 15 20Impedance Pin 8 All Other Pins at GND 7.5 10Breakdown Voltage1.0/lA Test CurrentT A = 25°COn Pin 1 GND on Pins 2,3,4,5,6,7-llVon Pin 8-25On Pin 7 GND on Pins 1,2,3,4,5,6-llV on Pin 8-25Leakage Current T A = 25°CPin 1V'N=-lBV,Va=-llVAll Other Pins at GNDPin 7Y'N = lBV, Va = -llVAll Other Pins at GNDPin BY'N = -BVAll Other Pins at GNDPower Supply Current Drain Outputs at Logic "0"(voo)1 MHz OperationT A = 25°CMM404, MM504 5.5MM405, MM505 10.0153020401.02512.50.50.50.510.015.0UNITSMHzVVpFpFpFpFpFkr!kr!kr!VV/lA/lA/lAmAmANote 1: For operating at elevated temperatures, the device must be derated based on a 150°C maximumjunction temperature and a thermal resistance of 150 o C!W junction to ambient. The full ratingapplies for case temperatures to +125°C.Note 2: These specifications apply over the specified temperature ranges for -11 V < V DO < -9.5V,and -18V

performance characteristicsPower Dissipation vs VDD Power Dissipation vs VGG Power Dissipation vs Temp.I~ 3.0..sI-;'!!;:-~iiiZ ....... ...- ..s-I­iii0Z-' .l"t~ 2.0~"... -7,;"t~ 2.0 I---t----:;;oi"""--+-I-~i5 - --- f. ~iii.-.... Vss = OVi5a: 1.0a: 1.0 -....... =-1--+-1-~VGG = -16V~ Voo = -10V0... V. = -16V f V.=VGGFREQ = 10 kHz~ 3.0 I---t--I--+-I--.-9..161412..s 10I­... Za:a::::>'"operationVDO-10 -11 -14VOUT vs Load Current-L/V'/to" ;;;;;;;; ~i--""4K EXTERN~~AO(SlNK)o -1 -2 -3 -4 -5 -6 -7 -8 -9VOUT-16-18V GO2.2N 2.0:z:~>- 1.B..I!'l:::> 1.68~ 1.4:;;:::>:;; 1.2.. x:;; 1.0-55 25TEMPE RATU RE 'cMax. Frequency vs Supply Voltages/V/V/' .."VI> = 0.4" ... !il 1 MHzV¢= 0.3" ... !ill.5 MHz-VI> = 0.2""", !il2.0 MHzVoo = -10VI I II --14 -16 -18 -20VGG & VI> (Volts)125A diagram of a one-bit static register employingtwo clock phases (rI>, ¢») is shown in the schematic.The register requires only one external clock phase(rI» since the second clock (4)) is generated internallyby T 19 and 15K; this configuration simplifiesthe input drive requirements.The basic cell functions as follows. Each bit ofdelay consists of three inverters T 2, T 4, and T 8 inconjunction with three MOS load resistors T 3, T 5,and T 9 followed by three coupling devices T 1, T 6,and T 7' The timing diagram shows the sequence ofoperation. Assume the input is at a logic "1" levelduring tl time. When the cloc!: (rI» goes to a logic"1" level, two operations take place simultaneously.First, transistor TI turns "ON", transferringthe input data (logic "1" level) to the gate tosource capacitance (Cd of T 2. The voltage storedon C 1 is sufficient to turn T 2 "ON" dischargingnode B. With the gate to source capacitance (C2)of T4 discharged, T4 turns "OFF" placing a logic"1" level at node C. Concurrently rI> turns T 19"ON" generating the complement of rI>, that is rI>and in turn 4> is used to turn T 6 and T 7 "OFF".This action allows the register's previous informationto be temporarily stored on the gate to sourcecapacitance C 3 of T 8' The output at node E duringthis timing sequence remains unchanged. However,during t2 time, clock rI> returns to ground;concurrently 4> goes to a logic "1" level turning T 1"OFF" allowing T6 and T7 to turn "ON". Theinformation which was previously stored on thegate of T 8 discharges to a logic "0" level causingthe output at node E to switch to a logic "1" levelthereby obtaining the required one·bit of delay.Likewise the information at node C is fed back tonode A latching T 2 in the "ON" state.When a logic "0" level is presented at the registerinput, the sequence is once again repeated. The bitdelay.demonstrated in this example is repeated foreach half of the dual static register.timing diagramI I "--_--1 II I I I IINPUTDATA~, ~I ('---;'1-1 I,r-'--'-~II~' I ----+1 ~'iI ---

Static Shift RegistersMM4040/MM5040 dual 16-bit static shift registergeneral descriptionThe MM4040/MM5040 dual 16-bit static shiftregister is a monolithic integrated circuit utilizingP channel enhancement mode low threshold technologyto achieve direct bipolar compatibility onthe inputs and outputs. The device requires onlya single phase clock.features• Bipolar compatibility +5, -12V operationNo pull-up or pulldownresistors needed• High frequency operation 2.2 MHz guaranteed• Single phase clockapplications• Static data buffer• Serial memory storage• Printer memory• Telemetry systems and data samplingconnection diagramMetal Can PackageVDDVssTOP VIEWtypical application+5VVeer- --, 4 VssI IL_~_JI 1II 116 ·BIT S.R.16·BITS.R.ANY DTlITTl DEVICE-12VdcANY DTLITTL DEVICE54

absolute maximum ratingsVoltage at Any Pin Vss + 0.3V to Vss - 22Operating Temperature Range MM4040-55°C to'+125°CMM5040 _25°C to + 70°CStorage Temperature Range_65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5%, Vss - VDD = 9V to 18.5V, VGG = -12V ±10%, unless otherwise specifiedPARAMETER CONDITIONS MIN TYP MAX UNITSData I nput LevelsLogical High Level (VIH ) Vss - 2.0 Vss + 0.3 VLogical Low Level (Vld Vss - 18.5 Vss - 4.2 VData In pu t Leakage VIN = - 20V, T A = 25°C, 0.5 J.lAAll Other Pins GNDData Input Capacitance V IN = O.OV, f = 1 MHz, 2.5 5.0 pFAll Other Pins GND (Note 1)Clock I nput LevelsLogical High Level (V¢H) Vss - 1.5 Vss + 0.3 VLogical Low Level (V¢d Vss - 18.5 Vss - 14.5 VClock I nput Leakage V¢ = -20V, T A = 25°C, 1.0 J.lAAll Other Pins GNDClock Input Capacitance V¢ = O.OV, f = 1 MHz, 19 22 pFAll Other Pins GND (Note 1)Data Output LevelsLogical High Level (V DH) ISOURCE = -0.5 mA 2.4 VLogical Low Level (Vad ISINK = 1.6 mA 0.4 VPower Supply CurrentT A = +25°C, VGG = -12V,¢pw = 200 ns, Vss = 5V,V DD = -12V, V¢L = -12V,Data = 0-1-0-1IGG 0.01 MHz -:::; ¢f -:::; 0.1 MHz 1.0 2.0 mA¢f = 1.0 MHz 1.8 3.0 mA¢f = 2.0 MHz 3.0 4.0 mA100 0.01 MHz -:::; ¢f -:::; 0.1 MHz 5.0 9.0 mA4>f = 1.0MHz 5.1 9.0 mA4>f = 2.0 MHz 5.2 9.0 mAClock Frequency (¢f) 4>tr = 4>tf = 20 ns DC 3.0 2.2 MHzClock Pulsewidth (¢pw) 4>tr + 4>tf + 4>pw -:::; 10.5 ns .200 .100 10.0 J.lsClock Transition Times (4)tr + 4>tf) 4>tr + ¢tf + 4>pw -:::; 10.5 ns 1.0 J.lsData Input Setup Time (\ls) 120 60 nsData Input Hold Time (\lh) 20 0 nsData Output Propagation Delay from 4> See test c ircu itDelay to High Level (tpdH) 200 300 nsDelay to Low Level (tpdd 200 300 nsNote 1: Capacitance values are guaranteed by statistical lot sample testing.55

guaranteed performance characteristics~a~ 2.0....=>...~Data Input levels vsSupply Voltage~ 1.0 t---t-+-i-'--f-*=i;::---lc1.0 MHz Operating Curve1000 r--r-,.-,.--,--,-,---,---,] 800:r....c~ 600 rc---t---t--t--~=>~ 400 r-t---+-t-'-''"c::j 200500]' 400:r....c~ 300~=>... 200~~'-' 1002.0 MHz Operating Curve¢tr = ¢ltf = 20 ns V,L = 0.8V¢f = 2.0 MHz--V,H = 3.0VTA = _55°C to +125°C V¢H= 3.5V-Vss = +5.0V I ..LMrV'- r- MIN ¢pwOr-O'---'--.J-.....J.--'---''---'----'12 13 14 15 16 17 18 19Vss - V¢L = Vss - Voo = Vss - VGG (V)13 14 15 16 17 18 19 20Vss - Voo = Vss - VGG = Vss - V¢L (V)o15 16 17 1819typical performance characteristics'-'w'-'a::=>....'"=>I!==>'"Data Output SourceCurrent vs VoltageV OUT (V)12'-'"" zin....~....:::>cData Output SinkCurrent vs Voltage0'----'---'--'---'---'----'5 -1V OUT (V)Power Supply Currentvs'voltage10.0 r--.--....-r--,----,-,--,.--.¢f= 1.0MHz< ¢pw= 400 ns.§ 8.0 DATA = 1-0-1-0+-+-+--+-71....i:l~ 6.0:::>'-'c.E 4.0w.. '"~..> 2.014 16 18 20Vss - VGG = Vss - Voo = Vss - VOL (V)5.0~ 4.0....i:l~ 3.0=>'-'.. '"~...2"2.0w> 1.0oPower Supply Currentvs Op4rating Frequency¢rw = 200'~sVss =+5.0VVGG = -12.0VVOL = -12.0VV¢H = 3.5VDATA = 1-0-1-0AI 111111 V)_55°C _~ TA-+25°C+125°C11111111111 11111Power Supply Current5.0 ,.---,--,---,---.,--.,----.

Static Shift RegistersMM4050A/MM5050A dual 32-bit static shift registerMM4051A/MM5051A dual 32-bit static shift register-split clockgeneral descriptionThe MM4050A/MM5050A and M M4051 AIMM5051A dual 32-bit static shift registers aremonolithic MOS integrated circuits utilizing Pchannel enhancement mode low threshold technologyto achieve bipolar compatibility. Operationto 2.2 MHz is achieved with a single phase clock.The MM4051A/MM5051A is a bonding optionof the MM4050A/MM5050A to provide independentclock control of each register.features• Bipolar compatibility +5V, -12V operationNo pull-up or pu,,­down resistors needed• High frequency operation dc to 2.2 MHz• Single phase clock• Improved drive capability Push-pull outputs• Military and commercial temperature rangesMM4050A, MM4051A -55°C to +125°CMM5050A, MM5051A -25°C to +70°Capplications• Serial memory storage• Printer memory• Telemetry systems and data sampling3:3:~oUIo».......3:3:UIoUIo».3:3:~oUI-».......3:3:UIoUI-»logic and connection diagramsDual-In-Line Package Metal Can Package Metal Can PackageNCINPUT AOUTPUT A1413VDDNCINPUT BNCCLOCK ¢OUTPUT BNCNCv'"NCVGGVssTOP VIEWMM5050ATOP VIEWMM4050A/MM5050ATOP VIEWMM4051A/MM5051Atypical applicationsTTL/MOS Interface+5VTTL/MOS Interface+5VVee-,32-BIT REGISTER32-BIT REGISTERr-2 II6 IIIL_J_JVeer-m-lI 1II IL_J;:_JI 732-81T REGISTER32·81T REGISTERVeer - -,TTLIIII IL_J;:_JANY DTL/TTLDEVICE-12VANYOn/TTLDEVICEANT On/TTLDEVICE-12VANY DTL/TTLDEVICEMM4050A/MM5050AMM4051A/MM5051A57

absolute maximum ratingsVoltage at Any PinVss + 0.3V to Vss - 22VOperating Temperature Range MM4050A/MM4051A -55°C to +125°CMM5050A/MM5051A -25°C to +70°CStorage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsTA within operating temperature range, Vss = +5.0V ±5%, Vss - V DD = 9V to 18.5V, VGG = -12V ±10%, unless otherwise stated.PARAMETER CONDITIONS MIN TYP MAX UNITSData I nput LevelsLogical HIGH Level (VIH ) Vss - 2.0 Vss + 0.3 VLogical LOW Level (Vld Vss - 18.5 Vss - 4.2 VData I nput Leakage V IN = -20V, T A = 25°C, 0.5 pAAll Other Pins GNDData Input Capacitance VIN = O.OV, f = 1 MHz, All Other Pins GND 2.5 5.0 pF(Note 1)Clock I nput LevelsLogical HIGH Level (VH) Vss - 1.5 Vss + 0.3 VLogical LOW Level (Vd Vss - 18.5 Vss -14.5 VClock Input Leakage V", = -20V, T A = 25°C, All Other Pins GND 1.0 pAClock I nput Capacitance V", = O.OV, f = 1 MHz, All Other Pins GND 25 35 pF(Note 1)Data Output LevelsLogical HIGH Level (VOH ) ISOURCE = -0.5 mA 2.4 VLogical LOW Level (Vod ISINK = 1.6 mA 0.4 VPower Supply CurrentIGGT A = +25°C, VGG = -12.0V,

guaranteed performance characteristics~a~-' 2.0....~;!!;uwua::::>o'" ....~....:::>oData Output SourceCurrent vs Voltage-1....t::ia:a::::>u'" z;;;........:::>o~ 413 14 15 16 17 18 19 20Vss - Voo = Vss - VGG = Vss - VOL (V)Output Sink Currentvs Voltageo L.---'_-'-_--'-_-'-_~--'5 -1V OUT (V)400] 300.... '"o1:~ 200:::>...'"u~ 100u5.01 4.0....t::i~ 3.0:::>uQ.E 2.0w

Static Shift RegistersMM4052/MM5052 dual 80 bit static shift registerMM4053/MM5053 dual 100-bit static shift registergeneral descriptionThe MM4052/MM5052 dual 80-bit and MM4053/MM5053 dual 100-bit static shift registers aremonolithic integrated circuits utilizing P channelenhancement mode low threshold technology toachieve direct bipolar compatibility on the inputsand outputs. The devices require only a singlephase clock.features• Bipolar compatibility+5, -12V operationNo pull-up or pulldownresistors needed• High frequency operation• Single phase clock• Improved drive capabilityapplications• Static data buffer• Serial memory storage• Printer memory• Telemetry systems and data sampling1.6 MHz guaranteepush-pull outputsconnection diagramMetal Can PackageVssTOP VIEWtypical application+5VVee-,I 1II IL_~_JANY DTLITTL DEVICEI 9V"N·BIT S.R.N·BIT S.R.-IZVANY DTLITTL DEVICE60

absolute maximum ratingsVoltage @ Any Pin Vss +O.3V to Vss -22VOperating Temperature RangeMM4052/MM4053-55°C to +85°C (Ambient)-55°C to +125°C (Case)MM5052/MM5053-25°C to +70°C (Ambient)Storage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5.0V ±5% and VGG = -12V ±10%, unless otherwise specified.PARAMETER CONDITIONS MIN TVP MAX UNITSData Input Le.velsLogical High Level (VIH ) Vss - 2.0 VLogical Low Level (V IL) Vss - 18.5 Vss - 4.2 -vData Input Leakage V IN = -20V, T A = 25°C .01 0.5 /JAAll other pins GNDData Input Capacitance V IN = O.OV, f = 1.0 MHz 3.0 5.0 pFAll other pins GNDClock Input LevelsLogical High Level (V H ) Vss - 1.5 Vss VLogical Low Level (V L! Vss - 18.5 Vss - 14.5 VClock Input Leakage V IN = -20V, TA = 25°C 1.0 /JAAll other pins GNDClock Input Capacitance V 1N = O.OV, f = 1.0 MHz 22 28 pFAll other pins GNDData Output LevelsLogical High Level (V OH ) ISOURCE = -500/JA 2.4V 4.8 Vss VLogical Low Level (VOL) ISINK = 1.6 rnA -3.0 0.4 VLogical High Level (VOH ) ISOURCE =-10/JA Vss -1.0 Vss Vss VLogical Low Level (VOL) ISINK = 10/JA Vss - 12.0 Vss -7.0 VPower Supply Current TA = 25°C

guaranteed performance characteristics1.0 MHz Operating Curve 1.6 MHz Operating Curve1000500-MA~~-~AX~pw -~ BOOI I] 400:r:r...Vss = 5.0V...1,...000-..-00 t"600i~ . = 1.0 MHz300wTA RANGE = _55°C to +B5°C ir-- w......~V,L = O.BV:::>... 400 ~ ...V,H = 3.0V:::>... f;;;: ........... MINpw2001,=1.=20 ..Vss= S.OVI::'"........ 200......... '".=1.6MHz_ I--I I :: TA RANGE = -55°C 10 +BSoC... 100 V,L = O.BV- I--oMINpw_I IoV,H = 3.0V- ~1,=I.=20n,12 14 16 18 20 12 14 16 18 20Vss - VGG (V)typical performance characteristicsVss - VGG (V)Maximum Data Input LowLevel vs Supply Voltage~ 2.2~,; 2.0i> 1.8w...~ 1.6::... 1.4:::>...!! 1.2...oror 1.00:&:::> .8:&;cor:& 12 14 16 18Vss - VGG (V)20Data Output Source Currentvs Data Output Voltage5.0 ...-~-~--r-~-"""-"VGG = -12VC Vss = S.OVt 4.0 I---IL--+-+-+--f-:;;;oo""\zwa:~ 3.0 1---I--+-+~of-~f-7"I...w.....~ 2.0 1---1,---++-#'--74'--1----1o...~ 1.0 1---I16'~=---+-+--t---I:::>o5.0 4.0 3.0 2.0 1.0 0.0 -1.0V OUT (V)cData Output Sink Currentvs Data Output Voltage.s B.O ~-+-""...r_--''''''''':__t_::-~;-:-i...::;~ 6.0 I--+--F ......::+--""...---"I"'-::--I:::>...'" zin...:::>4.0 1--+-+-+--+---"""'-::-..31~ 2.0 1--+-+-+-+--1---1o VGG = -12VVss = S.OV5.0 4.0 3.0 2.0 1.0 0.0 -1.0V OUT (V).10~iii.OBa:...or.s.2"w'" ora:w>or.06.04.02oPower Supply CurrentVss = S.OVpw = 250 n,TA = +2SoC. = 1.0 MHz/'DATA = 1-0-1-0/i-"V.;'12 14 16 18 20Vss - VGG (V)Power Supply Current.10 ...-,....,.",-mr-,-,.,.mTrr-...-r"'-TTTIOL-.L...I....llLI.1IL......L..L..... ___.......J10 100 1000 10.000OPERATING FREQUENCY (kHz)switching time waveformsac test circuitDATA INPUT62

Static Shift Registerss:s:U1oU1~MM5054 dual 64/72/80 bit static shift registergeneral descriptionThe MM5054 dual 80-bit static shift register is amonolithic MOS integrated circuit utilizing silicongate low threshold technology to achieve completebipolar compatibility_ The device has input andoutput taps that also provide register lengths of64 or 72 bits_The single phase bipolar compatible clock linesmay be driven by any conventional DTL or TTLcircuit_ The registers may be operated as a dualregister by connecting the clock lines A and Btogether, or as two independent registers. Twoclock control I ines provide independent logicalcontrol of the shift register clock lines.features• Complete bipolar compatibility DTL/TTLinput/output andclock line compatibilitywithout additionalcomponents• Standard supplies• High freq operation• Single phase clock+5V,-12VDC to 3.0 MHz typDTL/TTL compatibleon-chip clock driver• Low clock line capacitance 8 pF max• System flexibility Split clock or commonclock operation_ Logicalcontrol of clock lines• . Low power dissipationapplications

absolute maximum ratingsVoltage at Any Pin Vss + 0.3V to Vss - 20.0VOperating Ambient Temperature Range-25°C to +70°CStorage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A with in operating range, V GG = -12V ± 1 0%, V DO = GND, Vss = 5V ±5%, unless otherwise noted.PARAMETER CONDITIONS MIN TYP MAX UNITSData, Clock Control, and Clock LevelsLogical High Level (V IH ) See I nput Level vs V GG Curve Vss - 2.0 Vss + 0.3 VLogical Low Level (VI L) Vss - 4.2 -VI nput Leakages V IN = -10V, T A = 25°C 0.5 pAAll Other Pins GNDData I nput Capacitance V IN = O.OV, f = 1 MHz 4.5 6.0 pFAll Other Pins GN D (Note 1)Clock & Clock Control Capacitance VIN = O.OV, f = 1 MHz 6.0 8.0 pF(Note 1)Data Output Levels See Figure 1Logical High Level (VOH ) ISOURCE = -0.5 mA 2.4 Vss VLogical Low Level (VOL) ISINK = 1.6 mA 0.15 0.4 VPower Supply Current ¢f = 2.0 MHz, T A = 25°C(IGG + 100 = Iss) IGG Vss = 5V, Voo = GND 7.0 10.0 mA100 VGG=-12V 5.0 8.0 mAClock F requ ency (¢f) See Operating Curves DC 3.0 2.2 MHzClock Pulsewidth (¢pw)See Operating Curves andFigure 1Clock Pulsewidth ¢t,= ¢tf = 10 ns 0.25 10 psClock Transition TimesClock Risetime (¢t,) 500 nsClock Falltime (¢tf) 500 nsClock Control Setup Time (tcs) See Figure 1, ¢t, = ¢tf = 10 ns 0 nsClock Control Hold Time (tch) See Figure 1, ¢t, = ¢tf = 10 ns 0 nsData Input Setup Time (td.) See Figure 1, ¢t, = ¢tf = 10 ns 60 30 nsData Input Hold Time (tdh) See Figure 1, ¢t, = ¢tf = 10 ns 40 20 nsData Output Propagation Delay See Figures 1 & 2,From Clock¢t, = ¢tf = 10 nsDelay to Output High Level (tpdH) 200 300 nsDelay to Output Low Level (tpdd 200 300 nsNote 1: Capacitance is guaranteed by periodic testing.64

performance characteristics"....w....a::::>e:>'"5.04.03.02.01.0oTypical Data Output SourceCurrent vs Data Output Voltage~, I I Voo = GND~25°C\.:Vss = +5.0VOG = -12.0['. ~+~5oJ.....~+10°Cr-.... ~r--... ~'" ~..... ~~,o 1.0 2.0 3.0 4.0 5.0".... ,.zu;10.09.08.01.06.05.04.03.02.01.0Typical Data Output SinkCurrent vs Data Output VoltageVOG = -12.0Vr- -2~oC /1/1Voo = GND~Vss = +5.0V 4yj/. /' +10°CiIj /~ /'~V V~~",0.2 0.4 0.6 0.8 1.09.0"< 8.0.§I-~ 1.0a:a::::>....6.0~5.0~:::>'" a: 4.0w;::~ 3.0Typical Power SupplyCurrent vs VGGIss = IGG + 100Voo = GNDVss = +5.0VDATA = 1-0-1-0.p,= 1 MHzTA = +25°C.//' -(GVV".,.".,...... -ro:V ~/' '"2.012 13 14 15 16 11 18 19V OUT (V)V OUT (V)Vss - VGO (V)", (Hz)"....400Guaranteed 2.2 MHzOperating CurveVss = 5.0VVoo = GND-300 MAX1>pw-200--r--._25°C

MM4203/MM5203 electrically programmable2048-bit read only memory (pROM)general descriptionThe MM4203/MM5203 is a 2048-bit static readonlymemory which is electrically programmableand uses silicon gate technology to achieve bipolarcompatibility. The device is a non-volatile memoryorganized as a 256-8-bit words or 512-4-bit words.Programming of the memory contents is accomplishedby storing a charge in a cell location byprogramming that location with a 45 volt pulse.Separate output supply lead is provided to reduceinternal power dissipation in the output stage(VLd·features• Field programmable• Bipolar compatibility - +5V. -12V operation• High speed operation - 1 /ls max access timeROMs• Pin compatible with MM5213. MM5231mask programmable ROMs• Static operation - no clocks required• Common data busing (TRI-STATETM output)• "a" quartz lid version erasable with ultra-violetlight• Chip enable output control• 256 x 8 or 512 x 4 organizationapplications• Code conversion• Random logic synthesis• Table look-up• Character generator• Micro-programmings:s:~NoeN........s:s:(J1NoeNblock and connection diagramsDual-In-Line Package1/01 1108A, 1A, ,24 Vll23 VB"A,---,~--..,osCONT---'~ __ "",A, 3B, ,22 PROGRAM21 A4B, 520 A5PROGRAMOUTPUTB, 6B, ,B, BB, 919 A618 A,"'"16 VODB,1015 CONTROLBall14C5Vss 1213 Agtypical applicationsTOPVIEW256 x 8 PROM Showing TTL InterfaceOperating Modes"t MOOECONTROLA, 11 I OHITTLLO~IC, 0,256 x 8 ROM connection (shown!Mode Control - HIGHAS - LOW512 x 4 ROM connectionsMode Control - LOWAg - Logic HLGH enables the odd (81,83.. 87) outputs- Logic LOW enables the even (82,84.. 88) outputsoutputsThe outputs are enabled when a logic LOW is applied tothe Chip Enable line.Mode Control should be "hard wired" to VDD (LOW) orVSS IHIGH).Programming is accomplished in 256 x 8 mode only.Pin 23 is connected to VSS except when programmingwhen it is connected to VBB.Program pin is connected to VSS except when programmingprogram pulse is applied.In the programming mode, data inputs 1-8 are Pins 4-11respectively. Chip Enable should be disabled (HIGH).67

absolute maximum ratingsAll Input or Output Voltages withRespect to V BBPower DissipationOperating Temperature Range MM4203MM5203Storage Temperature RangeLead Temperature (Soldering, 10 sec)+.3 to -20V1W-55°e to 85°e-25°e to 70 0 e-65°C to 125°e300 0 eelectrical characteristicsTA within operating temperature range, Vss ~ +5V ±5%, Voo ~ V LL ~ 12V, ±5% unless otherwise noted.PARAMETERCONDITIONSMINTYPMAXUNITSInput Current, IL 1V IN ~ OV1J..IAOutput Leakage, I LOV OUT ~ OV Output in 3rd State1J..IAPower Supply Current, I DO 1TA ~ 25°C3555mAInput LOW Voltage, V ILVss-4.0VInput HIGH Voltage, V IHVss - 2.0VOutput LOW Voltage, VOL1.6 mA sink.40VOutput HIGH Voltage, VOH100 J..IA source2.4VData Hold Time, T OH(Min Access Time) Figures 1 & 2100nsAccess Time, T ACCT A ~ 25°C Figures 1 & 2.7001J..IsChip Enable Time, T CEFigures 1 & 3500nsChip Disable Time, T CDFigures 1 & 3500nsAllowable Chip Select Delay, tcsFigures 1 & 2Allowable delay in selecting chipafter change of address withoutaffecting access time.100nsInput Capacitance, C INOutput Capacitance, C OUTV IN ~Vss }f~ 1.0 MHzGuaranteed byV OUT ~ Vss design (Note 2)(Chip deselected)881515pFpFoperating characteristics for programming operationsTA = 25°C, Vss ~ OV, Vss ~ +12V ±10% unless otherwise notedPARAMETERCONDITIONSMINTYPMAXUNITSAddress and Data Input LoadCurrent,l L12PV 1N ~ -40V10mAProgram V LL Load Current, I L12PV IN ~ -50V10mAVss Supply Load Current, Iss100J..IAPeak IDD·Supply Load Current, loop (Note 3) V LL ~ V DO ~ V program = -50V750mAInput High Voltage, V 1LP+.3VPulsed Data Input Low Voltage, V IH1P-48Address Input Low Voltage, V 1H2P-48Pulsed Input Low Voltage:-50V LL, V DD, and Program, V 1H3P-40-40-48VVVNote 1: During programming, data is always applied in the 256 x 8 mode, regardless of the logic stateof Ag and mode control.Note 2: Capacitances are not tested on a production basis but are periodically sampled.Note 3: lOOp flows only during program period t¢PWp. Average power supply current lOOp istypically 15 mA at 2% duty cycle.Note 4: Maximum duty cycle of t¢pw should not be greater than 2% of cycle time so that powerdissipation is minimized. To guarantee long term memory retention the program cycle should be reopeated five times with t¢pw ~ 20 ms or the equivalent thereof, i.e. 10 cycles of t¢pw ~ 10 ms.68

operating characteristics (con'tl for programming operations(see Figure 4)PARAMETER CONDITIONS MIN TYP MAX UNITSDuty Cycle 2 %Program Pulse Width, t.ppw (Note 4) V DD ; V LL ; Vprogram ; -48V 20 msData Set Up Time, tDWData Hold Time, tDH11jJ.Sf.lsPulsed V LL and V DD Supply Overlap,tVD3 msOperation of the MM4203/MM5203 in Program ModeInitially, all 2048 bits of the MM4203/MM5203are in the HIGH state. Information is introducedby selectively programming LOWS in the properbit locations.Word address selection is done by the same decodingcircuitry used in the Read mode. The eightoutput terminals are used as data inputs to determinethe information pattern in the eight bits ofeach word. A LOW data input level (-50V) willleave a HIGH and a HIGH data input level willallow programming of a LOW. All eight bits of oneword are programmed simultaneously by settingthe desired bit information patterns on the datainput terminals. The duty cycle of the Programpulse (amplitude and width as specified on page 4).should be limited to 2%. The address should beapplied for at least 1 ps before application of theProgram pulse.During programming, all inputs are pulsed signals.MODEDATA AND ADDRESS LINESLOGIC 00,00 LOGIC "0 00Vss VBB voo PROGRAMRead (Data Out) Vss - 2.0 vss - 4.0Program (Data In) Vss -2.0 Vss - 40!Pulsel+5 +5 -12 +5GNO +12 -481 -48(Pulsel (PulselTape FormatThe custom patterns may be sent in on a Telex orsubmitted as a paper tape in a 7 bit ASCII codefrom model 33 teletype or TWX. The paper tapeshould be as the following example:A programmer specifically designed for theMM4203/MM5203 is available from: SpectrumDynamics, Inc., 2300 East Oakland Park Boulevard,Fort Lauderdale, Florida 33306.Start Character ---, Stop Character ---, Data Field MSB (Pin 11) LSB (Pin 4)Leader: Rubout for .. t I I + +TWf~:;e1el:t(~; I~:s~ B P P P N N N N N F B N N N N N N P P F ... B N P N P P P N N F25 frames') .. ~ ... ~Word aWord'Word 255All Address 1 nputs LOWAll Address Inputs HIGHTrailer: Rubout forT\tVX and letter Keyfor telex lat least25 frames')An output HIGH corresponds to a P on the papertape; an output LOW corresponds to an N.During programming, word 0 will cause -40V topunch tape formatO~~~O"3'000AnOIJ:nnOOO()f)(!~2Sp.~es -+---:;~~~7"'l~-g~~~~?~~ ~ -------~A004 00111]116 I ---1 SpaceNote L -_:gg~ ~g~.~(~~~g ~Alll"' 001111l1D 11AnOR OI1'lIlCl')()n (lA:,11 Oln llj 1 ("] 1 "rss 1 ",0 Note 4TB7 1 ':J1lTSh .,,50TRS "Of")Ta" () 1 f")TB3 InoTB2 299TBI t 197L_-=======:j-l Spacebe applied to all eight address inputs and word255 10 would cause 0 volts to be applied to alleight address inputs.Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tapeshould begin and end with 25 or more "RUBOUT" punches.Note 2: The ROM input address is expressed in decimal form and ispreceded by the letter A.Note 3: The total number of "1's" bits in the output word.Note 4: The total number of "1's" bits in each output column orbit position.Note 5: Specify whether tape is positive true or negative true logic.Negative true is always assumed when not specified.The tape would print out as shown for the 256 x 8 code.69

access time diagrams"L~V-V sr 2.OV~\.. ______________"---V _4,OV sst5V -5%,""EN

ROMsMM4210/MM5210 1024-bit read only memorygeneral descriptionThe MM4210/MM5210 is a 1024-bit static readonly memory. It is a P-channel enhancement modemonolithic MOS integrated circuit utilizing lowthreshold technology. The device is a non-volatilememory organized as 256-4 bit words. Programmingof the memory contents is accomplished bychanging one mask during device fabrication. Customerprograms may be supplied in a tape, card, orpattern selection format.features• Static operation• Common data busing• Chip enable output control.applications• Code conversion• Random logic synthesis• Table look-up• Bipolar compatibility • Character generators• High speed operation 500 ns typ • Micro-programming.no clocks requiredoutput wire ANDcapabilityblock and connection diagramsDual-In-Line PackageINPUTS(LSB) A,SENSEAMPLIFIERSOUTPUTS tB,INPUT II:! 1 16 VDDINPUT A, 2A,INPUT A,A,MEMORYADDRESSDECODERMEMORYB,B,OUTPUT B, 4OUTPUT B,SA,*The output is Enabled by applyinga logic "1" to the Chip Enable line.CHIP *ENABLEB.tThe outputs are cDnnacttd to VDDthrough an internal MOS resistorwhen Disabled.OUTPUT B, B 11 VaGOUTPUT B. 7 10 CHiPENABLEV •• I9 INPUT As~---...TOP VIEWtypical application256 x 4 Bit ROM Showing TTL InterfaceINPUTS-12V----....--------------------4.........- .......,+12v----+---4 .......----4.....----------.,oMBl10 DR OMBl12TTL GATES3.OK~-l-~~~jt-~A~8raa----~~V~ss~~3.0K"JO-ir-_ ....______A~l 123.0K CHiPENABLE 10 1 B.VGG 11 6 B,13MM42101MM52105!"B,B,UKUKUK...... ---t-... -----tUK+5VOUTPUTS14oTLiTTL LOGIC15Voo* Resistont"ue can wry from BIOn to 30 .. n. I71

absolute maximum ratingsV G G Supply VoltageVoo Supply VoltageI nput VoltageStorage TemperatureOperating Temperature MM4210MM5210Lead Temperature (Soldering, 10 sec)Vss-30VV ss-15V(Vss -20)V < V IN < (Vss +0.3)-65°C to +150°C_55°C to +125°C_25°C to +70°C300°Celectrical characteristicsT A within operating temperature range, Vss = +12V ±5% and V GG = -12V ±5%, unless otherwise specified.PARAMETER CONDITION MIN TYPOutput Voltage LevelsMOSto MOSLogical "1"1 Mn to GN D Load (Note 1)Logical "0" Vss -1.0MAXVss -9.0UNITSVVMOSto TTLLogical "1"6.8 kn to V GG Plus OneLogical "0" Standard Series 54/74 Gate Input +2.4+0.4 VVInput Voltage LevelsLogical "1"Logical "0" Vss -2.0Vss -8.0VVPower Supply CurrentTA~25°CVss 19VGG (Note 1)25 mA1 J.lAI nput LeakageV 1N ~ Vss-12V1 J.lAI nput Capacitance f= 1.0MHz V 1N = OV 5Access Time (Notes 2,3)TA =25°CT ACCESS (See Timing Diagram) 150 500Vss = +12V VGG = -12VpF650 nsOutput AND ConnectionMOS LoadTTL Load38Note 1: The VGG supply may be clocked to reduce device power without affecting access time.Note 2: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram.)Note 3: The access time in the TTL load configuration follows the equation: T ACCESS = thespecified time + (N-l) (50) ns where N = number of AND connections. The number of AND ties inthe MOS load configuration can be increased at the expense of MOS "0" level.72

performance characteristicsGuaranteed Access Time vsSupply VoltagesTypical Access Time vsSupply Voltages1000 TA = 12Soe800TA = 70 0 e1000~ TA =zsi ]m 600 ~ 600uu... " 400 ... 400200 200800r/:',"moe iP+ IIII +1/1-'70°C 1/'125°C 'I II I I10.8 12.0 13.2 10.8 12.0 13.2Vss & VGG (V)Vss & VGG (V)Power Supply Current vsVoltagePower Supply Current vsTemperature24 I- GUARANTEE~22TA = 25°CI ...... 26~ 20 TYPICAL I-.§22~c.§18".P c.PL.,..o18""'"- ~Vss = +12.0VVGG = -12.0V,GUARANTEED16 """:-....1414r--....TYPICA"'i:'i'-...10.8 12.0 13.2 -50 -25 0 25 50 75 100 125Vss & VGG (V)TEMPERATURE ec)timing diagram/address time'5V 3.0KI+l vIINPUT AN OUTPUT 8MI+3)L MM421 O/MM521 0OVE'N~L..+5VI*OM8810OM8812 T 10PFI6.8K*Jv*Eour10 PF..L ANY DTlrTTl ..L 15 pF•GATE+12VE'NOV+12vOV'3VEITHERORVss - 9.0~-'''"'I1.5VEOUT0'3VOV1.5VItime73

MOS ROM program formatThe memory contents for individual requirements must be submitted on a tape or card format as shownbelow. An 8·1/2" X 11" size pattern selection form is also acceptable. For copies of the MM421 O/MM521 0selection form, write or call any National sales office or National, Santa Clara.Punched Paper Tape or Cards. (See Note 5.1COLUMN NO.1 2 3 4 5 6 7 8 9 10 11 12 13 1484 83 82 81A 0 0 0 en en 1 0 1 0 en 2~.A 0 0 1 ] ~ 1 1 0 0 ~ 2~~.A () ()0 0 2 0 0 1 0 1 "~ il.I I I I ~ ~I I I II I I II I I II I I IA 2 5 5 1 1 0 0 2T 8 4 en 0 0 8 (Note 4) ZT 8 3 ~1 7 1 ~T 8 2 () 1 6 2!:!T 8 1 ~ 0 3 0frNote 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with25 or more "RUBOUT" punches.Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.Note 3: The total number of "1 's" bits in the output word.Note 4: The total number of "1 's" bits in each output column or bit position.Note 5: Program one address per card. All columns beyond those specified may be used by thecustomer.74

ROMsMM42111MM52111024-bit read only memorygeneral descriptionThe MM4211/MM5211 is a 1024-bit static readonly memory. It is a P-channel enhancement modemonolithic MOS integrated circuit utilizing lowthreshold technology. The device is a non-volatilememory organized as 256-4 bit words. Programmingof the memory contents is accomplished bychanging one mask during device fabrication.features• Bipolar compatibility• High speed operation• Static operation+5V, -12V operation< 700 ns typno clocks required• Common data busing• Chip enable output controlapplications• Code conversion• Random logic synthesis• Table look-up• Character generators• Micro-programmingoutput wire ANDcapabilityblock and connection diagramsDual-In-Line PackageINPUTS(LSB) A,SENSEAMPLIFIERSOUTPUTS t>---B,INPUT A3INPUT A216 Voo15 INPUT A.MEMORYADDRESSDECODERMEMORY>---B,>---B3INPUT AlOUTPUT 8,OUTPUT 8214 INPUT A513 INPUT A612 INPUT A7>---B,OUTPUT 83*The output is Enabled bV applyinga logic "1" to the Chip Enable line.CHIP *ENABLEtThe outputs are connected to VDnthrough an internal-MQS resi.torwhen Disabled.OUTPUT 84 7Vss10 CHIPENABLEL8 ______ --' INPUT ABTOP VIEWtypical application256 x 4 Bit ROM Showing TTL Interface-12V--------~------------------------------------~~f_~~_,.5VA,Vss6.0K 6.8K S.8K 6.aKINPUTSCHIPENABLE10VGG11B,B3A,12B,OUTPUTSANY OIl/TTLlOGIC13MM4211! MM5211B,14ANY OTl/TTllOGIC15tVDO16II175

absolute maximum ratingsVGG Supply VoltageVss - 20VVoo Supply VoltageVss - 20VInput Voltage(Vss - 20)V < V 1N < (Vss +0.3)VStorage Temperature-65°C to +150°COperating Temperature MM4211-55°C to +125°CMM5211_25°C to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = +5V ±5%, V GG = V DO = -12V ±5%, unless otherwise noted.PARAMETER CONDITIONS MIN TYP MAX UNITSOutput Voltage LevelsMOS to TTLLogical "1" 6.8K ±5% to VGG Plus O[1e +0.4 VLogical "0" Standard Series 54/74 Gate +2.4 VOutput Current CapabilityLogical "0" V OUT = 2.4V 2.5 mAInput Voltage LevelsLogical "1" Vss - 4.2 VLogical "0" Vss - 2.0 VPower Supply Current T A = 25°C100 Vss = +5V 6.5 12.0 mAIGG (Note 1) VGG = V DO = -12V 1 /lAI nput Leakage V 1N = Vss - 12V 1 /lAInput Capacitance f = 1.0 MHz, V 1N = OV 5 pFV GG Capacitance f = 1.0 MHz, V 1N = OV 15 25 pFAddress Time (Note 2)See Timing DiagramT ACCESS TA = 25°C, 700 950 nsVss = 5VVGG = Voo = -12VOutput AND Connection 6.8K ±5% to VGG Plus One 8(Note 3)Standard Series 54/74 GateNote 1: The V GG supply may be clocked to reduce device power without affecting access time.Note 2: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.Note 3: The address time in the TTL load configuration follows the equation:T ACCESS = The specified limit + (N -1) (50) nsWhere N = Number of AND connections.76

performance characteristicsPower Supply Current vsPower Supply VoltagesPower Supply Current vsAmbient Temperature16 16Voo - VGG14 TA = 25'C 1412"j,.oo!'"12~......MAXIMUM 1-1-f-MAXIMUM~ 10 10,g ~0 B ,g BVss - +5.0VVDD = VGG = 7.2VS> 0 TYPICAL __ f--6l- S>6TYPICALr--4 42 20 016.0 17.0 lB.O -50 -25 0 25 50 75 100 125Vss - VGG (V)r-AMBIENT TEMPERATURE ('C)Typical Access Time vsPower Supply Voltages1400 1400voo = vGG1200 ]: 1200e1 1000 1Guaranteed Access Time vsPower Supply Voltagesl-voo

~~N~ MOS ROM program format::EThe memory contents for individual requirements must be submitted on a tape or card format as shown........ below. An 8-1/2" x 11" size pattern selection form is also acceptable. For copies of the MM4211 /MM5211;::: selection form, write or call any National sales office or National, Santa Clara.N'lit Punched Paper Tape or Cards. (See Note 5.)::E::ECOLUMN NO1 2 3 4 5 6 7 8 9 10 11 12 13 1484 B3 B2 B1A 0 0 0 U> U> 1 0 1 0 .g> 2F r] " ~~0 0 1 0 1 'II [~ ~~A 0 0 1 ~ 1 1 0 0 ~ 2 0;A 0 0 2I I I II I I II I I II I I II I I IA 2 5 5 1 1 0 0 2T B 4 U> 0 0 8 (Note 4)T B 3 "~1 7 1T B 2~1 6 2T 8 1 0 3 0Note': The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with25 or more "RUBOUT" punches.Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.Note 3: The total number of ""s" bits in the output word.Note 4: The total number of ""s" bits in each output column or bit position.Note 5: Program one address per card. All columns beyond those specified may be used by thecustomer.~~rI78

MM4220/ MM5220 1024-bit read only memorygeneral descriptionThe MM4220/MM5220 is a 1024-bit static readonly memory. It is a P-channel enhancement modemonolithic MOS integrated circuit utilizing lowthreshold voltage technology. The device is a nonvolatilememory organized as 12S-S-bit words or256-4-bit words. Programming of the memory contentsis accomplished by changing one mask duringthe device fabrication. Customer programs may besupplied in a tape, card, or pattern selection format.features• Bipolar compatibility• High speed operation 500 ns typblock and connection diagrams• Static operation• Common data busing• Chip enable output control.applications• Code conversion• Random logic synthesis• Table look-up• Character generators• Micro-programming.ROMsno clocks requiredoutput wire ANDcapability1It'IITSILSI) A,SENSE AMPLIfiERSOUTPUTSB,Dual-In-Line PackageA,A,B,B,B,B,B,B,!N'UrAl ..INPUT A2IN'UTA,v ••" NeOUTPUT .1 'NPUT A.OUTPuralounUT B3OUTPUT 8.OUTPUT B!"IN'UT~INPUT .,B, OUTPUlls" MODECONTROLOUTPUT',v ••" " CM.,ENABLEOUTPUTB8 INPUT "-~----~--~ ~~------ ENABLEMODE CONTAOl-----L...FCHIP v"" " NeTOI'VIEWtypical application128-8 Bit ROM Showing TTL Interface-'2V_____ ~------------~-..... .,, A • ..t CHI' ..~NAILEt MODE..CONTROLV ••..A, ..MM4220/MM5Z20.. B,'-IOMll10 OR OMAn . A,'"A,AoTTL GATES

absolute maximum ratingsVGG Supply VoltageVoo Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4220MM5220Vss-30VVss-15V(Vss -20)V < V 1N < (Vss +0.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = + 12V ±5% and V GG = -12V ±5%, unless otherwise specified.PARAMETER CONDITION MIN TYPOutput Voltage LevelsMOSto MOSLogical "1"1 Mil to GND Load (Note 1)Logical "0" Vss -1.0MAXVss -9.0UNITSVVMOSto TTLLogical "1"6.8 kil to V GG Plus OneLogical "0" Standard Series 54/74 Gate Input +2.4+0.4 VVInput Voltage LevelsLogical "1"Logical "0" Vss -2.0Vss -8.0VVPower Supply Current T A = 25°CVss 19VGG (Note 1)I nput Leakage V 1N = Vss -12VI nput Capacitance f= 1.0MHz V 1N = OV 5Access Time (Notes 2, 3) TA = 25°CTAccEss (See Timing Diagram) 150 500Vss = +12V VGG=-12V25 mA1 /lA1 /lApF650 nsOutput AND ConnectionMOS LoadTTL Load38Note 1: The V GG supply may be clocked to reduce device power without affecting access time.Note 2: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing DiagramJNote 3: The access time in the TTL load configuration follows the equation: T ACCESS = thespecified time + (N-1) (50) ns where N = number of AND connections. The number of AND ties inthe MOS load configuration can be increased at the expense of MOS "0" level.80

performance characteristicsGuaranteed Access Ti me vsSupply VoltagesI I1000 TA = 125°e 1000800TA = 75°CTA=~:rc ]~ 600 ~ 600" ~ "

MOS ROM program formatThe memory contents for individual requirements must be submitted on a tape or card format as shownbelow. An 8-1/2" X 11" size pattern selection form is also acceptable. For copies of the MM4220/MM5220selection form, write or call any National sales office or National, Santa Clara.Punched Paper Tape or Cards. (See Note 5.1COLUMN NO.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18B8 B7 B6 B5 B4 B3 B2 BlA 0 0 0 en en 1 0 1 0 1 0 1 0 en 4&'A 0 0 1~ ~1 1 1 1 1 1 0 0~6A 0 0 2 1 0 1 1 0 0 1 0g> g>" 4 "I I I I g- g-i'r-~.~ " ~~I I I II I I I 3I I I IA 1 2 7 0 1 1 1 1 1 0 5T B 8 0 0 8 INOTE 41 ZT B 7 1 7 1 ~T B 6 1 6 2 !o!I I I en I I II I I " I I II I I ~ I I II I I g> I I IT B 1g-O 3 0Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with25 or more "RU80UT" punches.Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.Note 3: The total number of "1's" bits in the outP.ut word.Note 4: The total number of "1's" bits in each output column or bit position.Note 5: The punched card format is as shown except that columns 17 and 18 are not necessary.Program one address per card. All columns beyond those specified may be used by the customer.82

ROMsMM42211MM52211024-bit read only memorygeneral descriptionThe MM4221iMM5221 is a 1024-bit static readonly memory. It is a P-channel enhancement modemonolithic MOS integrated circuit utilizing lowthreshold voltage technology. The device is a nonvolatilememory organized as 128-8-bit words or256-4-bit words. Programming of the memorycontents is accomplished by changing one maskduring the device fabrication.features• Bipolar compatibility• High speed operation+5V, -12V operation

absolute maximum ratingsVGG Supply VoltageVoo Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4221MM5221Lead Temperature (Soldering, 10 sec)Vss - 20V. Vss - 20V(Vss - 20)V < V 1N < (V SS +0.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°C300°Celectrical characteristicsT A within operating temperature range, Vss = +5V ±5%, VGG = Voo = -12V ±5%, unless otherwise specified.PARAMETER CONDITIONS MIN TYPMAXUNITSOutput Voltage LevelsMOS to TTLLogical "1"6.8 kQ ±5% to V GG Plus OneLogical "0" Standard Series 54/74 Gate +2.4Output Current CapabilityLogical "0" V OUT = 2.4V 2.5+0.4 VVmAInput Voltage LevelsLogical "1"Logical "0" Vss - 2.0Vss - 4.2VVPower Supply Current TA = 25°C100 Vss = +5V 6.5IGG (Note 1) VGG = V DO = -12V12.0 mA1 pAI nput LeakageV 1N = Vss - 12V1 pAInput Capacitance f = 1.0 MHz, V 1N = OV 5V GG Capacitance f = 1.0 MHz, V 1N = OV 15Address Time (Note 2)See Timing DiagramTAccEss TA = 25°C, 700Vss = 5VVGG = Voo = -12VpF25 pF950 nsOutput AND Connections(Note 3)6.8 kQ ±5% to V GG Plus OneStandard Series 54/74 Gate8Note 1: The VGG supply may be clocked to reduce device power without affecting access time.Note 2: Address ti me is measured from the change of data on any i·nput except mode control or ChipEnable line to the output of a TTL gate. (See Timing Diagram). See curves for guaranteed limitover temperature.Note 3: The address time in the TTL load configuration follows the equation:TACCESS = The specified limit + (N -1) (50) nsWhere N = Number of AND connections.84

performance characteristicsPower Supply Current vsPower Supply VoltagesPower Supply Current vsAmbient Temperature16 16VOD = VGGVss = +S.OV14 TA = 2SoC 14Vee = Vaa = -12VNo..J,.oooI""1212.-MAXIMUM r-+-i-MAXIMUM.. 10 10.! ..Q B .! 8.E Q I""" TYPICAl._i'"" .E i""I--6 6TYPICAL4 4s:s:~NN-'.........s:s:UINN-'2 20 016.0 11.0 lB.O -SO -2S 0 25 SO 15 100 12SVss- Vaa (V)AMBIENT TEMPERATURE (OC)Typical Access Time vsPower Supply Voltages1400 1400Vee = VaaGuaranteed Access Time vsPower Supply VoltagesVoo= VGG! 1200 ] 1200 to- +12SoC11 1000 11 1000 +10°·C+2so·C.. " +10°C +125°C "BOO ~ BOO!::. I I !::.w::;;+25°C600 ~;::: ;::: 600~~w 400w 400.. .. 200 2000 016.0 11.0 lB.O 16.0 11.0 18.0Vss - Vaa (V)Vss - Vaa (V)timing diagram/address time+&V+&V+5VI+ INPUT AN OUTPUT s.. ++3TL MM4221/MM5221 EOUTov E~ANY TTL/DTl IN 10 pFGATE ~I 1-Xv" "*6.8KGATE10PF.l ANY TTL/on .l15 pF"*Vss - 2.0VE'NEOUTOV+5VOV+3V0+3VOVEITHERVSS - 4.2V~I- '-'"i1.5V1.5VItime85

-NN~ MOS ROM program format:::!!: The memory contents for individual requirements must be submitted on a tape or card format as shown........ below. An 8-1/2" X 11" size pattern selection form is also acceptable. For copies of the MM4221/MM5221-N selection form, write or call any National sales office or National, Santa Clara.N!lid' Punched Paper Tape or Cards. (See Note 5.):::!!::::!!:COLUMN NO.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18B8 B7 86 B5 B4 B3 B2 BlA 0 0 0 III III 1 0 1 0 1 0 1 0 III 4A 0 0 1i i 1 1 1 1 1 1 0 0 1l 6~ ~~ ~ . ...A 0 0 2 n n 1 0 1 1 0 0 1 0 n 40I I I I0~ ii- ii- " a.I I I II I I I~I I I IA 1 2 7 0 1 1 1 1 1 0 5T B 8 0 0 8 (NOTE 41 Z0T B 7 1 7 1 :;;T B 6 1 6 2wI I I I I IIIII I Ii I I II I I I I II I I &' I I IT B 1 ii- 0 3 0*Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with25 or more "RUBOUT" punches.Nota 2: The ROM input address is expressed in decimal form and is preceded by the letter A.Note 3: The total number of "1's" bits in the output word.Note 4: The total number of "1's" bits in each output column or bit position.Nota 5: The punched card format is as shown except that columns 17 and 18 are not necessary.Program one address per card. All columns beyond those specified may be used by the customer.86

illSROMsMM4230/MM5230 2048-bit read only memorygeneral descriptionThe MM4230/MM5230 is a 2048-bit static readonly memory. It is a P-channel enhancement modemonolithic MOS integrated circuit utilizing lowthreshold voltage technology. The device is a nonvolatilememory organized as 256-8 bit words or512-4 bit words. Programming of the memory contentsis accomplished by changing one mask duringthe device fabrication. Customer programs may besupplied in a tape, card, or pattern selection format.features• Bipolar compatibility• High speed operation 500 ns typblock and connection diagrams• Static operation no clocks required• Common data busing output wire ANDcapability• Chip enable output control.applications• Code conversion• Random logic synthesis• Table look-up• Character generators• Micro-programming.• .,un(LSI! A,IE.EAMPL.fllR'GUTI'mI,Dual-In-Line Package..I,....IIUIIORV"...."..eM".. ----~--~ ~+4-------- EI,uLEMODE-COIIIT«OL --------1'--'1"'IN'UTA3INPUT"!INPUT A,OUTPUTB,OUT'UTI2ounUTllout,u,l.OUTPUT 15OUTPUT~OUT'UT8,OUTPUT IsV"I_PUlA.II'UTA1INPUT A..V"".. ..CONTROLCHI'ENAILE1Z INPUT A,TOPVUWtypical application256 x 8 Bit ROM Showing TTL InterfaceOperating Modes-12V+fZV"V-{_toTTL GATESt I,l' CHIPlUlU..t MOO£COlLraUl... .. IIu.- ..I,v .... II.. U...II tov ....II"....I, II .._31tJWm1D.."n I,ItC.v".. I," ""..U.U •"V}-256.8 ROM connectionMode Control - Logic ·'0"A. - Logic "'"5'2.4 ROM connectionMode Control - Logic •• ,,,A. - Logic "0" Enables the odd(B,. 8, ... B.) outputs- Logic ."" Enables the even(B,. B4 ... B.) outputs .The outputs are ··Enabled" when a logic "'" isapplied to the Chip Enable line.The outputs are connected to V DO through aninternal MOS resistor when "Disabled.".".87

absolute maximum ratingsVGG Supply VoltageVoo Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4230MM5230Vss-30VVss-15V(Vss -20)V < VI N< (Vss +O.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsT A within operating temperature range, Vss = + 12V ±5% and V GG = -12V ±5%, unless otherwise specified.PARAMETER CONDITION MIN TYPOutput Voltage LevelsMOSto MOSLogical "1"1 Mn to GND Load (Note 1)Logical "0" Vss -1.0MAXVss -9.0UNITSVVMOSto TTLLogical "1"6.8 kn to VGG Plus OneLogical "0" Standard Series 54/74 Gate Input +2.4+0.4 VVInput Voltage LevelsLogical "1"Logical "0" Vss -2.0Vss -8.0VVPower Supply Current TA = 25°CVss 24VGG (Note 1)I nput Leakage V IN = Vss -12VI nput Capacitance f = 1.0 MHz V IN = OV 5Access Time (Notes 2, 3) TA = 25°CT ACCESS (See Timing Diagram) 150 500Vss = +12V VGG = -12V40 mA1 pA1 pApF725 nsOutput AND ConnectionMOS LoadTTL Load38Note 1: The VGG supply may be clocked to reduce device power without affecting access time.Note 2: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram.)Note 3: The access time in the TTL load configuration follows the equation: T ACCESS = thespecified time + (N-1) (50) ns where N = number of AND connections. The number of AND ties inthe MOS load configuration can be increased at the expense of MOS "0" level.88

performance characteristicsGuaranteed Access Timevs Supply VoltagesTypical Access Time vsSupply Voltages100011 1TA • 125'CTA'~1000800 800~ --~c~ 600 ~ 600u~ tl400 .... 400...."200 200;It ... f1~5~CH{f70°C 1j 5 r--;- 1110.8 12.0 13.2 10.8 12.0 13.2Vss & VGG (V)Vss & VGG (V)Power Su pply Cu rrentPower Supply Currentvs Voltagesvs Temperature60TA ' 25'CVss = +12.0V40 ~Ak 50VGG ·-12.0VMAX-3640 l""'-o;< 32 """;< I--tVPICAL.§. .§. 30r-00......-E 28 ..... TVPICAL - 1-1-24-Er-t--.". 2020 10010.8 12.0 13.2 -50 -25 0 25 50 15 100 125 150Vss & VGG (V)TEMPERATURE (OC)timing diagram/address time+3JLOV+5V 3.0KI+l v+5V+ INPUT AN OUTPUT 8M +DMBB10EIN/T~10PF~MM4230lMM5230IIJv10PF~ANY DTlr~ ...I.. 15 pF6.BK GATE IEOUT+12VE'NEOUTOV+12VOV+3V0+3VOVEITHERVss - 9.0OR~I- '-",1.5V1.5VItime89

MOS ROM program formatThe memory contents for individual requirements must be submitted on a tape or card format as shownbelow. An 8·1/2" X 11" size pattern selection form is also acceptable. For copies of the MM4230/MM5230selection form, write or call any National sales office or National, Santa Clara.Punched Paper Tape or Cards. (See Note 5.1COLUMN NO.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1888 87 B6 85 B4 83 82 81A 0 0 0 ., 1'" '"0 1 0 1 0 1 0 4'" &'A 0 0 1 ~ § 1 1 1 1 1 1 0 0 § 6~A 0 0 2 "C'l C'l 1 0 1 1 0 0 1~.0 4 -n1 1 1 1 0 0~ " li.~ ~1 1 1 1~1 1 1 11 1 1 1A 2 5 5 0 1 1 1 1 1 0 5T B 8 0 0 8 (NOTE 41 ZT 8 r1 7 1 ~T 8 6 1 6 2 !o!I I I I I I~I I I I I 1I I I Ii I I II I I &' I I IT 8 1 ~ 0 3 0Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with25 or more "RUBOUT" punches.Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.Note 3: The total number of "1 's" bits in the output word.Note 4: The totel number of "1 's" bits in each output column or bit position.Note 5: The punched card format is as shown except that col umns 17 and 18 are not necessary.Program one address per card. All columns beyond those specified may be used by the customer.90

~12V-----_""' _____________ROMsMM42311MM5231 2048-bit read only memorygeneral descriptionThe MM4231/MM5231 is a 2048-bit static readonly memory. It is a P-channel enhancement modemonolithic MOS integrated circuit utilizing lowthreshold voltage technology. The device is a nonvolatilememory organized as a 256-8 bit words or512-4 bit words. Programming of the memorycontents is accomplished by changing one maskduring the device fabrication.features• Bipolar compatibility• High speed operation+5V, -12V operation640 ns typo• Static operation No clocks required• Common data busing Output wire ANDcapability• Chip enable output controlapplications• Code conversion• Random logic synthesis• Table look-up• Character generator• Micro-programmingblock and connection diagramsDual-In-Line PackageINPUTSr___ 1-___ ~S(NSEAMPUFIEIIS OUTPun tIliPUTA3 24v",INPUtA2A,INPUT A,A,I,OUTPUTS,IN'UTA.OUTPUT 82INPUT AsMEMOIIYADOIIESSDECODEII~~OUll'UTB3OUTPUT I."INPUT~INPUT A,A,B,OU1'U185OUTPUT 8.INPUTA.v"I...DUTPUTB,OUT,UT8.v .."MODECONTROLCHIPENABLEINPUT A,MOOECONYIIOL-----L,,)tTbtolitputsll'llcon_ttdtoVDDth'G~gh.niate".lMOSl'llsi"orwIIenOiubled.*T•• outpv.ti$EnlbledbYlpplyingaLo~"I"toth.C.ipEn.b"lin •.typical application256 x 8 Bit ROM Showing TTL Interface-ITTL GATES1tseeap.rlt,ngllllHlanotti..""'''''--,A,t CHIPENABLE ..t MOOECONTIIOl..v".. I,..A,B,AoA,1"""..B,MM42311MM5231v" ,. A,,I,A,A,1].-Operating Modes256x8 ROM connection (shown)Mode Control - Logic "0"Ag - Logic ","512x4 ROM connectionMode Control - Logic ","Ag - logic "0" Enables the odd(8 1,83 , .. 89 ) outputs- Logic "," Enables the even(B 2, 84 ... Ba) outputs.The outputs are "Enabled" when a logic" 1" isapplied to the Chip Enable line .Logic levels are negative true MOS logic.Mode Control should be "hard wired" to Voe(Logical "1") or Vss (Logical "0").91

absolute maximum ratingsVGG Supply VoltageVoo Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4231MM5231Vss - 20VVss - 20V(Vss - 20)V < V 1N < (Vss + 0.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristicsPARAMETERCONDITIONSMINTYPMAXUNITSOutput Voltage LevelsMOS to TTLLogical "1"Logical "0"6.8 kn ±5% to Voo Plus OneStandard Series 54/74 Gate2.4+0.4 VVOutput Current CapabilityLogical "0"V OUT = 2.4V2.5mAInput Voltage LevelsLogical "1"Logical "0"Vss - 2.0Vss - 4.2VVPower Supply Current100IGG (Note 1)TA = 25°CVss = +5VVGG = Voo = -12V1530 mA1 p.AInput LeakageV 1N = -12V1 p.AInput Capacitancef = 1.0 MHz, V 1N = OV5pFV GG Capacitancef = 1.0 MHz, V 1N = OV15pFAddress Time (Note 2)TAccEssSee Timing DiagramT A = 25°C Vss = +5.0VVGG = Voo = -12.0V640950 nsOutput AND Connections(Note 3)6.8 kn ±5% to Voo Plus OneStandard Series 54/74 Gate8Note 1: These specifications apply for VSS = +5V ±5%, VGG = VOO = -12V, ±5%, and T A = -55"Cto +125°C (MM4231), T A = -25°C to +70oC (MM5231) unless otherwise specified.Note 2: The VGG supply may be clocked to reduce device power without affecting access time.Note 3: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.Note 4: The address time in the TTL load configuration follows the equation:T ACCESS = The specified limit + (N -1) (50) ns.Where N = Number of AND connections.Note 5: Capacitances are measured on a lot sample basis only.92

performance characteristicsGuaranteed Access Time IT AIvs Power Supply VoltageTypical Access Time IT AIvs Power Supply Voltage1400 1400VDO = VGGVOD = VGG12001-0 +!2~Ot1200I1000 +71rC 1000+25°'CBOOBOO +125°C-;;;-!oS ..+70~C.. 600 ... 600...+25~C400 400200 2000 016.0 17.0 lB.O 16.0 17.0 lB.OVss- VOG (V)Vss - VGG (V)Power Supply Current vsPower Supply VoltagePower Supply Current vsAmbient Temperaturea32 4028~TA = 25'C36-1~AXIMUM32Vss=+5.0v'4.... VOD = VGG = -12V24 GUARANTEEDI I2B20a24MAXIM~.. .. IIGUARANTEED..5 16 ..5 20.E12.E 16TYPICAL12"++J.J.8TYPICAL84 4I III0 0II16.0 17.0 18.0 -50 -25 0 +26 +50 +75 +100 +125VSS-VGG (V)TA ('C)timrng diag rami address timeE'NEITHER \~~~ '-~1.5VEOUT1.5VItime+5V+5VIvss+3TL*"MM42311MM5231OV E~ANY TTL/OTL 'N 10 pfUKGATE VDDIto•INPUT Ao OUTPUT a..•-lTv+5V10 Pf..l.. ANY TTL/OTL ..l.. 15 pf~ GATE ~-- EOUT93

MOS ROM program formatThe memory contents for individual requirements must be submitted on a tape or card format as shownbelow. An 8-1/2" x 11" size pattern selection form is also acceptable. For copies of the MM4231/MM5231selection form, write or call any National sales office or National, Santa Clara.Punched Paper Tape or Cards. (See Note 5.1COLUMN NO.1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18B8 B7 B6 B5 B4 B3 B2 BlA 0 0 0 en en 1 0 1 0 1 0 1 0 en 4&' c~ " ~I4 i" ...0~~:u !~A 0 0 1 1 1 1 1 1 1 ~ 0 0 6 ~A 0 0 2 n n 1 0 1 1 0 0 1 0I I I II I I II I I I~3I I I IA 1 2 7 0 1 1 1 1 1 0 5T B 8 0 0 8 (NOTE 4) ZT B 7 1 7 1 ~T B 6 1 6 2 !o!I I I en I I II I I I I II I I ~ I I InI I I 0 I I IT B 1 ~ 0 3 0Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tape should begin and end with25 or more "RUBOUT" punches.Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.Note 3: The total number of ·'l's" bits in the output word.Note 4: The total number of "l's" bits in each output column or bit position.Note 5: The punched card format is as shown except that col umns 17 and 18 are not necessary.Program one address per card. All columns beyond those specified may be used by the customer.94

ROMsMM4232/MM5232 4096 -bit static read-only memorygeneral descriptionThe MM4232/MM5232 4096-bit static read-onlymemory is a P-channel enhancement mode monolithicMOS integrated circuit utilizing a low thresholdvoltage technology to achieve bipolar compatibility_TRI-STATETM outputs provide wire ORedcapability without loading common data lines orreducing system access times. The ROM is organizedin a 512 word x 8-bit or 1024 word x 4-bitmemory organization that is controlled by themode control input. Programmable Chip Enables(CE, and CE 2 ) provide logic control of up to 16Kbits without external logic. A separate outputsupply lead is provided to reduce internal powerdissipation in the output stages.Customer programs may be submitted for productionin a paper tape or punched card format.features• Bipolar compatibility No externalcomponents requ ired• Standard supplies +5V, -12V• BusORableoutput TRI-STATEoutputs• Static operation No clocks required• Multiple ROM control Two-programmableChip Enable linesapplications• Character generator• Random logic synthesis• Micro-programming• Table look-uplogic and connection diagramsA, A,Dual-In-Line PackageA. 1--~--oB,A,A,A,A,A,A"CON~~~~ o---..JCE,o----------ICE,o----------IMEMORYARRAYI--~-:I:-o B,1---Dt:~-oB,I---Dt:=-f-o B.B,B,B,1--~-+-oB,MODE CONTROL 1 24 V"CE, 2l V"CE," B,A" •21 B,A,, 20 B,A, I 19 B,A, 7 18 B.A, 17 B,A, 16• B,A,15 B,A, " 11V~ 12 " ..13 A,TQPVIEWtypical applicationsTTL/MOS InterfaceFIGURE 1_ Power Saver forSmall Memory ArraysFIGURE 2. Power Saver forLarge Memory ArraysA,A,A,A,A,A,v"MM42321MMS232B... ..B,--,IIIIIL ___ .Jr----,I'::' IIII II IVGGL ___ .JCE,o----.JCE,o------I512 x 8 ROM connectionMode Control - logic HIGHAl0 - logic lOWASSUME IIVlL IIMIN ~ II-JV IIVGG - Vu MIN R (1.6 rnA) (N) where N ""4 lor 1024 x 4 organizationN ~ 810r 512 x 8 organizationOperating Modes1024 x 4 ROM connectionMode Control - Logic LOWA10 - Logic HIGH enables the odd(8, ... 8 7 ) outputsLogic LOW enables the even(8'2 ... 8a) outputsWhen eE 1 = 1. CE 2 :: 1 the outputs are enabled when a logic LOW is applied to the chip enable line. The outputs are in the thirdstate when' disabled. The logic states of the chip enables are specified on the program tape. Mode Control must be hard wired toVGG or V LL for a logic LOW or to Vss-for a logic HIGH.95

absolute maximum ratingsVGG Supply VoltageV LL Supply VoltageInput VoltageStorage Temperature RangeOperating Temperature Range MM4232MMS232Lead Temperature (Soldering. 10 sec)Vss - 20VVss - 20V(Vss - 20) v < V IN < (V SS + .03)V-6SoC to +1S0°C-SSoC to +12SoC- 2SoC to +70°C300°Celectrical characteristicsTA within operating temperature range, Vss = +5V ±5%, VGG = Voo = -12V ±5%, unless otherwise noted.PARAMETER CONDITIONS MINOutput Voltage LevelsLogical LOWIL = 1.6 mA SinkLogical HIGH IL = 100 IlA Source 2.4Input Voltage LevelsLogical LOWLogical HIGH Vss - 2.0Power Supply CurrentIss (Note 4) Vss = 5, VGG = -12, V LL = -12, TA = 25°CIss (Note 4) Vss = 5, VGG= -12, VLL = -3, TA = 125°CI nput LeakageInput Capacitance (Note 2)Output Capacitance (Note 2)Y'N = Vss - 10Vf = 1.0 MHz, Y'N = OVf = 1.0 MHz, Y'N = OVAddress Time (Note 1) T A = 25°C, Vss = 5 150T ACCESS VGG = V LL = -12VOutput AN 0 Connections (Note 3)TVP231254MAXVss -4.0UNITS.4 VVVV37 mA20 mA1 IJA10 pF10 pF1000 ns20Note 1: Capacitances are measured periodically only.Note 2: Address is measured from the change of data on any input or chip enable line to the outputof a TTL gate. (See Timing Diagram.)Note 3: The address time follows the following equation: T ACCESS = The specified limit + (N-l1 x25 ns where N = Number of AND connections.Note 4: Outputs open.96

performance characteristicsGuaranteed Access Time vsSupply Voltage1600 1600VLL = VGG14001400I I'Z5~ClZ00 TA =10°ClZ00Z5°ClZ5°C! 1000 1000 TA=10°CZ5°C~ BOO :! 800~600 .... 600400 400Typical Access Time vsSupply VoltageVLL = VGGZOOZOO0 016.Z 11.0 I1.B 16.Z 11.0 I1.BVss + IVGGI (V)Vss + IVGG I (V)Power Supply Current vsTemperaturePower Supply Cu rrent vsVoltageBOBOVss= 5.0VTA= Z5°C-10 VGG = VLL = -IZV 10 VLL = VGG60 6050 50<

punch tape format(Program a "1" or "0")2 SpacesNote 2MM4?3?CEI=OCE2=0AOOO 00000000 ---.....--Note 3ADOI OO(JOOOOOADO? 00000000AD03 01010101 41 SpaceA004 00111111 6ADOS 00011100 3A006 OOOOOOO!) 0A007 00 III 100 4AOOR ooonoooa 0A;,II 01010101 4TBR 140 ---------i-- Note 4TS? 150T86 250TR5 401)T84 DInTfl3 100T82 299TBI 197'------------+--1 SpaceNote 1: The code is a 7 bit ASCII code on 8 punch tape. The tapeshould begin and end with 25 or more "RUBOUT" punches.Note 2: The ROM input address is expressed in decimal form and ispreceded by the letter A.Note 3: The total number of "1's" bits in the output word.Note 4:, The total number of "1's" bits in each output column orbit position.The MMS232 can be programmed as a 512 )( 8 or a 1024 )( 4. Thetape would print out as shown for the 512 x 8 code.98

ROMsMM4240/MM5240 2560-bit static character generatorgeneral descriptionThe MM4240/MM5240 2560-bit static charactergenerator is a P-channel enhancement modemonolithic MOS integrated circuit utilizing a lowthreshold voltage technology. Six character addressand three row address input I ines provideaccess to 64-8 x 5 characters. Customer-generatedsingle or multiple package character fonts are easilyprogrammed by completing a pattern selectionform. A standard 7 x 5 raster scan font is available byordering the MM4240AA/MM5240AA. (See page102.)The MM4240/MM5240 may be used as a512 x 5-bit read only memory for appl icationsother than character generation.connection diagramfeatures• Bipolar compatibility• High speed operation-600 ns max.• ± 12 volt power suppl ies• Static operation-no clocks required• Multiple ROM logic application-chip enableoutput control• Standard fonts available-off-the-shelf deliveryapplications• Character generation• Random logic synthesis• Micro-programming• Table look-upADDRESSINPUTSDATAOUTPUTSrROWl2L,N'N'N'r8,BJ8,8,v"101112TOP VIEW" v"" N'" N'ZI A,A,"" A, 6 LINEINPUTS" A,11 A,"A," v""CHIPENAILE" N' +12Vtypical application8,8 8,8,101.":8,,-+-+-+-...-,..R ~6.IKLOAD/RECIRCULATE MM5016', LOAD/RECIRCULATECONTROLCONTROLL, -I2VVeeCLOCK"-------~ ---~PAGE REFREStiLINE REFRESHMEMORVMEMORYNote: FOlldodilion.linformllionllftf to AN"'"99

absolute maximum ratingsVGG Supply VoltageV D D Supply VoltageInput VoltageStorage TemperatureOperating Temperature MM4240MM5240Lead Temperature (Soldering, 10 sec)Vss - 30VVss - 15V(Vss - 20)V < V 1N < (Vss +0.3)V-65°C to +150°C-55°C to +125°C-25°C to +70°C300°Celectrical characteristics (Note 1)PARAMETERCONDITIONSMINTYPMAXUNITSOutput Voltage LevelsMOSto MOSLogical "1"Logical "0"IMD to GNDVss - 1.0VSS - 9.0VVMOSto TTLLogical "1"Logical "0"6.8 kD to VGG Plus OneStandard Series 54/74 Gate+2.5+0.4VVOutput Current CapabilityLogical "0"V OUT = VSS - 6.0V2.5mAInput Voltage LevelsLogical "1"Logical "0"Vss - 2.0Vss - 8.0VVPower Supply CurrentIDDIGG (Note 2)25401mApAInput LeakageV 1N = VSS - 12V1pAInput CapacitanceVGG Capacitancef = 1.0 MHz, V 1N = OVf = 1.0 MHz, V 1N = OV525840pFpFAddress Time (Note 3)TACCESSSee Timing DiagramTA =25°C150450600nsOutput AND Connection(Note 4)MOS LoadTTL Load410Note 1: These specifications apply for VSS = +12V ±5%, VGG = -12V ±5%, and T A = -55°C to+125°C (MM4240), T A = -25°C to + 70°C (MM5240) unless otherwise specified.Note 2: The V GG supply may be clocked to reduce device power without affecting access time.Note 3: Address time is measured from the change of data on any input or Chip Enable line to theoutput of a TTL gate. (See Timing Diagram). See curves for guaranteed limit over temperature.Note 4: The address time in the TTL load configuration follows the equation:T ACCESS = The specified limit + (N - 1) (50) nsWhere N = Number of AND connections.The number of AND ties in the MOS load configuration can be increased at the expense of MOS "0"level.100

performance characteristics1200Guaranteed Access Time (T A)vs Supply Voltage12~0~1000 .100070~800 8001200Typical Access Time (T A) vsSupply Voltage25°C .... ... .... ~ 125°C 70°C.. .. -...- ..s 600 .s 600.... ....400 400 ,200 20025°C f-0 010.8 12.0 13.2 10.8 12.0 13.2Vss & -VGG (V)Vss & -VGG (V)Power Supply Current vsVoltageTA = 25°CVOO Power Supply Current vsTemperatureVss = +12.0V50 50 MA~ VGG =-12.0Vj40i-' 40 J""..~TYPICAL;;;;;;r-r-..f-""".. - --.5 30 ApicAL.5 30 0 I- 0.E """- - 20 20 ..E10 1060--010.8 12.0 13.2 -50 -25 0 25 50 75 100 125 150Vss & -VGG (V)TEMPEflATURE (OC)timing diagram/address time+12VE,.EOUTEITHEROV~+12VOV+lVW~T ACCESS1.5V0J+lV ,OV1.5Vtime+lTLDV+5V l.OKI+l V+5V~INPUT AN OUTPUT lit.MM4240/MM5240•E,.-!. _.OMB810T 'OPF~IIJv6.8K*'10 Pf..l.. ANY OTlITTl ..L'*'EOUT15 pfGATE101

MM4240AA/MM5240AA character fontROWADDRESS001010011100101110111OUTPUTS8, 82B3B4 BsI. I•••I•I•••• • •••• •••••••••••• •••••••••• I.·· .. I :1 • I II I I.·a::••.: :.•• : : ::..••••••• ·.1.· I I .1••• ••••• .1••• I .... I •••• 100 M n..~ M H000000 000001 GOGon 000011 Il00100 000101 000110 000111"i···i .,. :: .. : 1·.·1 I·. II··'I :.:: .:: :.1. ••..1 I·:·. L .. ::111••• 1u 13 ,. 15 16 1711001000 " 01)1001•••• ••• •••• •••I •••• · i·· : I. ••••• .. ·001010 001011 001100 l1li1101 001110 001111•••••• •• •• •i i P •• II iI·.· I· ••••I•20••21••22• •••i :•••: .,. i···123 2. 25 26 n010000 010001 010010 010011 011111111 01111111 II10TtO 010111• ••• • ••••••••: .1..:.:. ·1· ••••· . . .......i ••. • ··1 • •• •I ·1···30 31 32 33 • •••lS • •31011000 011001I011010 011011 "i i J i. .:::.011100 011101 1111110 " 011111• ••• ••••• : I •• :I..100000 100001• ·11· ..:..• •:• :: ..... • ••u 45" l00lno " 100011 "• • •••( ·1..:. .4fI 47100100::1·. ··1··..100101 1001111 11111111:•••••.. • • 51• • :1 :I I·52 53 5456101000 101001 1011110 101 lin 101100 101101 " 101110 101111 ":••: ·1 .•••:....: .·i I::· ••••••••I I I •••• ••• : •• 1. I i··· ........ .:. I .... ••••• I ••••• ..... In 54 85 66 67..110000 110001"... ..110010 " 110011 110100 1101111 110110 110111:: •:••• 1 ' ••• 1 I:•••••••••••••• :: ..... .:..••::••• ••70 71111000 111001 1110111 "••II111011 111100 "15111101••16111110•11111111I~put add, .... 1t in six bit ASCII co .... ~d.re dlown In !h. s.quaneaAs. A....... nlis.lsodiownlorrtfelillCeAo;lh. OCUlI/CIUI-102

ROMsMM42411MM5241 3072-bit static read-only memorygeneral descriptionThe MM4241/MM5241 3072-bit static read-onlymemory is a P-channel enhancement mode monolithicMOS integrated circuit utilizing a low thresholdvoltage technology to achieve bipolar compatibility.TRI-STATETM outputs provide wire ORedcapability without loading common data' lines orreducing system access times. The ROM is organizedin a 64 x 6 word by 8-bit memory organization.Programmable Chip Enables (CE 1 and CE 2 )provide logic control of mUltiple packages withoutexternal logic. A separate output supply lead isprovided to reduce internal power dissipation inthe output stages.Customer programs may be submitted for productionin a paper tape or punched card format.logic and connection diagramsfeatures• Bipolar compatibility• Standard supplies• Bus ORable output• Static operation• Multiple ROM controlapplications• Character generator• Random logic synthesis• Micro-programming• Table look-upNo externalcomponents required+5V. -12VTRI-STATE outputsNo clocks requiredTwo programmableChip Enable linesA,A, A,Dual-In-Line PackageA.A,A,l,l,l,VDECODECE,o--------ICE,o--------IMEMORYARRAYB,B,B,B.B,B,B,B,NC 24 v"CE," v"NC 4 21 B,A, 20 ..A, IB ..CE, l 12 ..A, IB.. , '.11 B,A,• " B,A, 10 15 B,l, 11 14 l,v§ 12" l,TDPVIEWtypical applicationsTTL/MOS Interfacev§FIGURE 1. Power SaverforSmall Memory ArraysFIGURE 2. Power Saver forLarge Memory ArraysANY TTL/OllDEVICE.,....MM4241/..l,l,MM5241CE,----'CE,-----'B,B.B,..B,ANY TTL/OlLDEVICEr- --, r----,I I I -::- II I I II I I II Iv" L ___ ..JI IL ___ ..JASSUME IIVLL IIMIN '" 11-3V IIVOG - VLL MIN = R 11.& mAl (N) 1/I'here N = 1 fot 5 x 1lont.N= "oraIl8tont.When CE 1 '" 1, CE2 '" 1 the outputs are enabled when a logic LOW is applied to the chip enable line. The outputs are in the thirdstate when disabled. The logic states of the chip enables are specified on the program tape.103

absolute maximum ratingsVGG Supply VoltageV LL Supply VoltageI nput VoltageStorage Temperature RangeOperating Temperature RangeMM4241MM5241Lead Temperature (Soldering, 10 sec)Vss - 20VVss - 20V(Vss - 20) v < V 1N < (V SS + .03)V-65°C to +150°C-55°C to +125°C_25°C to + 70°C300°Celectrical characteristicsTA within operating temperature range, Vss = +5V ±5%, VGG = Voo = -12V ±5%, unless otherwise specified.PARAMETER CONDITIONS MIN TYPMAXUNITSOutput Voltage LevelsLogical LOWIL = 1.6 mA sinkLogical HIGH 'L = 100llAsource 2.4Input Voltage LevelsLogical LOWLogical HIGH Vss -2.0Power Supply CurrentIss (Note 4) Vss = 5. VGG = -12. V LL = -12, TA = 25°C 23Iss (Note 4) Vss = 5, VGG = -12, VLL = -3, TA = 125°CInput LeakageY'N = Vss - 10VInput Capacitance (Note 1) f = 1.0 MHz, Y'N = OV 5Output Capacitance (Note 1) f = 1.0 MHz, V,N = OV 4Address Time (Note 2) TA = 25°C, Vss = 5 150 700T ACCESS VGG = VLL = -12VOutput AND Connections (Note 3)Vss - 4.0.4 VVVV37 mA20 mA1 IlA10 pF10 pF900 ns20Note 1: Address is measured from the change of data on any input or ch ip enable line to the outputof a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.Note 2: Capacitances are measured periodically only.Note 3: The address time follows the following equation: T ACCESS = The specified limit + (N-l) x25 ns where N = Number of AND connections.Note 4: Outputs open.104

performance characteristicsTypical Access Time vsSupply Voltage1400 1600VLL = vGG1200I140010001200 125'e'MeTA= 70'eTA=70'e 1000 25'eg 800 25'e ].... " 600.... " 800600400200400200Guaranteed Access Time vsSupply VoltageVLL = VGG16.2 17.0 17.8 16.2 17.0 17.8Vss + IVGG I (V)Vss + I VGGI (V)60 60" IL I ,G'I_50 50CiCiE.s 40 MAXIMUM - 40JiJi.30 30TYPICAL20 2010 10Power Supply CurrentPower Supply Currentvs Temperaturevs Voltage80 80Vss = 5.0VTA=25°e-70 VGG = VLL = -12V 70 V -V ,-MAXIMUM-T~PlbAll-50 -25 0 25 50 75 100 125 16.2 17.0 17.8TEMPERATURE (OC)Vss + IVGG I (V)timing diagram/address timeJ:SL54/74GATE+rE'NMM42411 MM5241T 'OPF-~10pF-:r-+5V+54/74GATEEOUTr '5PFE'NEOUT,1\ \, Vss-4EITHER ORf Vss-2---11.5~I v:-TIME105

punch tape formatChip EnableMM4241(Program a "'" or "0") _=::I::-_CE I =0CE2=0COO LOLIL20 11111001000001DID 111012Sp~es--~--------~L~3;'-L4LSNote 2 ---+---CO I LoLIL2L3L4L5C77 LoLIL2L3L4L5TBI 100Tfl2 ?9RTB3 319TB4 107TB5 239TB6 318Tfl7 291TB6 2490101010100011110000000000111111000001001000010010000100101111110000000000000001000000001010100010000100100000110000000006aII32P.0b,boNote 3'S~Note 4L-______ -=====================:i---,sp~Note 1: The code is a 7 bit ASCII code on 8 punch tape. The tapeshould begin and end with 25 or more "RUBOUT" punches.Note 2: The ROM (nput address is expressed in octal form and ispreceded by the letter C, the row or- line is 8ICpressad in decirrial"form and is preceded by the letter L. There are 78 octal (64 decimal)locations.Note 3: The total number of "1's" bits in the output word.Note 4: The total number of "1's" bits in each output column orbit position.106

RAMsMM1101/MM11011/MM1101A/MM1101A1/MM1101A2256-bit fully decoded static random access memorygeneral descriptionThe MMll0l family of fully decoded 256 word xl-bit random access memories are monolithic MaSintegrated circuits using silicon gate low thresholdtechnology to achieve bipolar compatibility_ Theyare static, require no clocks, and hold informationindefinitely, subject to the integrity of the powersupply to the RAM plane_features• Fastaccesstimes MMll01A2 500 ns maxMM11011, MMll01AlMMll0l, MMll01A1.0 tis max1.5 tis max• Improved speed/power productMMll01A21/30f1101A• Low power operation 1.5 mW/bit• Fewer system components bipolar compatibleinput and output• Second source flexibility 1101,1101A,• TRI-STATETM output11011, 1101A 1 secondsources availablewired ORcapability• Specified ambient temperature _25°e to + 70 0 eapplications• High speed buffer memories• L?cal memory storeblock and connection diagramsAo10A, X INPUTA,9 BUFFERSA,11256 BITRAMPLANEDATA 13OUTDATA 14OUTcsR/WDATA IN161512Vo == Power to buffers, decoders, and sense circuitVDO "RAM plane power only. See Note 5.Dual-In-Line PackageINPUT AsINPUT A7INPUT A6VoINPUT A4INPUT AoVoo16 CHIP SELECT15READ/WRlTE14 DATA OUT13 DATA OUT12 DATA IN11INPUT A310INPUT At9 INPUT A2TOP VIEW107

N.-

performance curves (MM1101A/MM1101A1/MM1101A2)350~ 0rl 300Q.. >z ., 250;:::::~ 200c;II:...;: 150.,...--•Power Dissipation vs VoltageTYPICAL- • GUARANTEEDP VDD _Vss ·+ .OV ~ PVDr---TA '+25°C.......:: ::;;-"'~" .''"~' '"IPVDPVD~_I~ 400g 350a:: 300I., 2'­i c;II:~..Power Dissipation vs AmbientTemperatureI-t-t-t-- - • TYPICALI-+-+--+---- • GUARANTEED250~~~~~-f.--~_~-~PVD200 _;- _I-- Yss =- +5.DV ±5%• Pv150 t- ~D '" ~DD " 1-9.0~ ±5% .1. I DOI-- PYOD '" IIvDD x Veo) =MEMORY ARRAY -100I-- POWER DISSIPATION -I-Pvo" liVe x Vo) = ~~~~~~~:~ POWER _-8.0 -9.0 -10.0 -30-20 -10 0 10 20 30 40 50 60 70VOLTAGE (VD, VDD) (V)AMBIENT TEMPERATURE, TA (OC)17.016.0~ 15.0~I 14.0.J 13.012.011.0Operating RegionTA • _25°C to +7D°CIf- TYPICAL.1OPERATING REGION I--" I I I~I%Ic- hillUARANTEED I~ ~OPERATINGREGIONI IB.O 10.0 12.0 14.0Vss - VDD (V)16.0...!§liE:;;....=:...:;;;:::III .....700600500400300200Access Time vs AmbientTemperature_NlNlI101A2-..,.--Nl~I.!1~..,.-NlNl110~Vo '" -9.OV ±5%Voo =< -9.OV ±5%Vss"+5.DV±5%SEE SWITCHING TIMEEST SET UP~. ,:,.: 1~ !Al--·TYPICAL_. GUARANTEED-30 -20-10 0 10 20 30 40 50 60 70AMBIENT TEMPERATURE (OC)1500 ~1400 g; ...1300 ~1200 ~;;:1100 ;;:;;:1000 ~!li900 ;:;~BOO] 500...:Il;::: 400III~ 300~200Access Time vs Supply Voltage-7.0 -8.0 -9.0 -10.0 -11.0VD (V)1500 1::C")m1400 !II:::!1300 iii1200 ~;;:1100 ;;1000 ~!li900 ;:;~test circuitOUTPUTCONDITIONS OF TESTInput pulse amplitudes: ov to +5.0VInput pulse rise and f.11 times~ 10 nsSpeed measurements are referenced to the 1.5V level (unless otherwise noted), at the output ofthe TTL gate (tpel::;: 10 ns) CL ~20 pF.Test Setup for MM1101 and MM1101A Speed MeasurementNote 1: All inputs ofthe MM11 01 A accept standard TTL outputs with Vee = +5.0V ±5%.Note 2: Access time degradation as a function of load capacitance may be determined from thefollowing equations:a) ta (T A = +25°C) = t0 1 + 0.32 CL nsb) ta (T A = +70°C) = t0 2 + 0.35 CL nsWhere t01, t02 = access ~imerespectlvelv.andCL = pFin ns for 1 TTL load at TA = +25°C, and TA = +70°C109

definition of timing parametersta Access Time: The time required for the outputto be valid from the initiation of an addresschange.twd Address Input to Write Pulse Delay: Theminimum time required after the initiation of anaddress change and the start of the Write mode ofoperation.twp Write Pulse Width: The minimum pulse width

RAMsMM1103 1024-bit fully decodeddynamic random access read/write memorygeneral descriptionThe MM1103 fully decoded dynamic 1024 wordx 1-bit per word readlwrite random access memoryis a monolithic MaS integrated circuit using silicongate low threshold technology. This device providesa non-destructive read out memory cell withchip enable for easy selection when many outputsare "OR"ed. Low power is achieved by the use ofdynamic logic and power dissipation occurs primarilyduring precharge. The MM 1103 is used formain memory applications where large bit storage,high performance and low cost are important.• Refresh cycle• Fully decoded• Easy memory expansion• Device protection• "OR"ing outputcapability• Low power dissipation• Small package size2 msChip enable inputAll 1/0 lines haveprotection againststatic charge250mW18 pin DIPfeatures• Fast access time• Fast cycle time300 ns max480 ns read cycle580 ns write cycleapplications• Mainframe memory• Large buffer memoryconnection diagramDual-I n-Line PackageA, 1- -18 READ!WR1TEA, 2- ,..-17 VssA, 3- _16 CHIPENA8LEAo 4- I--l~ A,PRE-CHARGE ~- 1-14 DATAOUTPo" 6- 1--13 A.As 7- fo-12DATAINA; 8- 1--11 VDDA, 9- 1- 10 v ••TOP VIEW111

absolute maximum ratingsAll Input or Output Voltages With Respectto the Most Positive Supply Voltage Vss +0.3V to -25VSupply Voltage V DD and Vss WithRespect to V ss +0.3V to -25VPower Dissipation at Room Temperature500mWOperating Temper"ture Range_25°e to + 70 0 eStorage Temperature Range-65°e to +160 o eLead Temperature (Soldering, 10 sec)300 0 edc operating characteristicsT A within operating temperature range, Vss ~ 16 ± IV; (VBB -Vss) ~ 3V to 4V, Vaa ~ OV unless otherwise specifiedPARAMETER CONDITIONS MIN TYP MAX UNITSInput Load Current (All V'N ~ OV 1 pAInput Pins) (lL')Output Leakage Current (lLO) V OUT ~ OV 1 pAV BB Supply Current (lBB) 100 pAAverage Supply Current (I DD AV) Cycle Time ~ 580 ns precharge width 20 mA~ 240ns, TA ~ 25°CStandby Supply Current Precharge ~ Vss , Chip Enable ~ Vss, 100 pATA ~ 25°CInput LOW Voltage (V'L) Vss - 17 Vss - 15 VInput HIGH Voltage (V'H) Vss - 1 Vss + 1 VOutput HIGH Current (I OH ) TA ~ 25°C RL ~ lOOn 600 4000 pAOutput HIGH Voltage (V OH ) TA ~ 25°C RL ~ lOOn 60 400 mVac operating characteristics TA ~ o°c to 70°C, Vss ~READ, WRITE, AND READ/WRITE CYCLE16 ± 5%. (VBB - Vss ) ~ 3.0V to 4.0V. V DD ~ OVPARAMETER CONDITIONS MIN TYP MAX UNITSTime Between Refresh (t REF ) 2 msAddress to Cenable Set Up Time (tAd Note 1 115 nsCenable to Address Hold Time (tCA) 20 nsPrecharge to Cenable Delay (tpc! Note 1 125 nsPrecharge & Cenable Overlap. LOW (tOVL ) 25 75 nsCenable to Precharge Delay (tcp) 85 nsPrecharge & Cenable Overlap, HIGH (tOVH) 140READ CYCLEPARAMETER CONDITIONS MIN TYP MAX UNITS}Precharge to End of Cenable (tpov) tACmin + tOVLmin tT ~ 20 ns 165 500 nsRead Cycle (tRc! Note 1480 ns+ tpomax + 2 tTEnd of Precharge to Output Delay (tPD)CLOAD ~ 100 pF 120 nsAddress to Output Access (tAcer! Note 1RLOAD ~ lOOntpcmln + tOVLmin300 nsV REF ~ 40 mVPrecharge to Output Access (tAce2) Note 1 + tpomax + 2 tT 310 nsWRITE OR READ/WRITE CYCLEPARAMETER CONDITIONS MIN TYP MAX UNITSWrite Cycle (twc) Note 1 tT ~ 20 ns 580 nsRead/Write Cycle (tRWC ) Note 1 tT = 20 ns 580 nsPrecharge to Read/Write Delay (tpw) 165 500 nsRead/Write Pulse Width (twp) 80 nsRead/Write Set Up Time (tw) 80 nsData Set Up Time (tow) 105 nsData Hold Time (t DH) 10 nsEnd of Precharge to Output Delay (tpo) CLOAD = 100 pF 120 nsR LOA D = lOOnTime to Next Precharge (tp) V REF ~ 40 mV 0Note 1: These times will degrade by 40 ns (worst case) if the maximum values for VIL (for precharge,cenable and read/write inputs) go to VSS - 14.2V @O"Cand VSS - 14.5V@ 70°C.112

ac operating characteristics (con't)'CAPACITANCEPARAMETERCONDITIONSAddress Capacitance (CAD)Precharge Capacitance (CPA)Cenable Capacitance (C eE )Read/Write Capacitance (CAW)Data Input Capacitance (C ,N1 )Data Input Capacitance (C ,N2 )Data Output Capacitance (C OUT )Y'N = VssY,N = VssY'N = VssY'N = VssCenable = OVY'N = VssCenable = VssV ,N = VssV OUT = OVf = 1 MHzAll UnusedPins Areat AC GND*This parameter is periodically sampled and is not 100% tested. They are measured at worst caseoperating conditions. Capacitance are for plastic packages only.switching time waveforms" I100I1S0IWRITE CYCLE OR REAO!WRITE CYCLETIMING ILLUSTRATED FOR MINIMUM CYCLE200I250I300I3S0I400I ." 5"I I550 580I IADDRESS CAN CHANGE1--r-~~~~~~~~~~~~~-(W,ORtRwc~~~~~~~~~~~~~~~-IADDRESSPRECHARGEv" ~~--"1V1H --f:CENABlEAEAD!WRITEDATAIN!lATAOUTv"VOL --I+-------/'READ CYCLEADDRESS CAN CHANGEADDRESSPRECHARGECENABlEREADIWRITEvoc--H------.jVREF - 40mVRLDAO -loonClDAD -100 pFNoteNoteNoteNoteG) VDD +2V} . d f· d .. .(1l Vss _ 2V tT IS e me as the tranSitions between these two POints.3 tow is referenced to point ® of the rising edge of cenable or read/write whichever occurs first4 tOH is referenced to point CD of the rising edge of cenable or read/write whichever occurs first113

RAMsMM5260 1024-bit fully decodeddynamic random access memorygeneral descriptionThe MM5260 fully decoded dynamic 1024 word x1-bit word read/write random access memory is amonolithic MOS integrated circuit using silicongate low threshold technology to achieve bipolarcompatibility on all I/O lines except the prechargeand read/write lines. This provides an efficientapproach to memory design using this systemsoriented device. The MM5260 is used for mainmemory applications where large bit storage andimproved operating performance are important. ATRI·STATETM output is utilized to allow wired"OR" capability and common I/O data busing inmemory applications.features• Fast access time 350 ns• Fast cycle time 450 ns read cycle min600 ns write cycle min• Low overhead circuit count Fully decoded• Systems-oriented design Bipolar compatible(address lines, chipenable data I/O)Common data I/O lineTRI-STATE output• Refresh cycle 2.0 ms• Easy memory expansion Chip enable• Device protection All I/O lines haveprotection againststatic charge• Standard power supplies +5V, -12V• Low power dissipation 400 mW• Small package size 16 pin dual-in-line packageapplications• High speed mainframe memory• Mass memory storagetypical applicationMain Memory Module Storing 4096 16-Bit Words" " / >--I+---tr

absolute maximum ratingsAll I nput or Output Voltages withRespect to Most Positive Supply Voltage VssPower DissipationOperating Temperature RangeStorage Temperature RangeLead Temperature (Soldering, 10 sec)+0.3V to -20V600mW-25°C to +70°C-65°C to +150°C300°Cdc operating characteristicsT A within operating temperature range, Vss = +5V ±5%, V DO = -12V ±5%, unless otherwise noted.PARAMETERCONDITIONSMIN TVP MAXUNITSInput Voltage (Address input,chip enable and data input)Logic "0" (VIH )Logic "1" (V IL )Vss - 2.0Vss - 4.0VVI nput voltage (Precharge andReadlWrite)Logic "0" (V IH )Logic "1" (VIL )V ss -l.5Vss - 15VVOutput VoltageData OutputLogic "0" (V OH)Logic "1" NodI L = 200 fJA SourceIL = 1.6 mA Sink2.40.4VVAverage Supply Current (lDD)t cycle = 450 ns and tpc = 300 ns20mAac operating cha racteristicsT A within operating temperature range, Vss = +5V ±5V%, V DO = -12V ±5%, unless otherwise noted.Read Cycle (T ReiWrite Cycle (T weiRead/Write Cycle (T RWe!Access Time (T A)Address to Chip Enable (T Ae! Note 2Address to Precharge Delay (T APL) Note 2Address to Write Pulse Delay (T AWD)Write Pulse Width (T wp)Precharge Off Time (T pp)Read Write to Precharge Delay (T WRP)Refresh Interval (T REF)Address to Precharge Trailing Edge (T APT)450600I I(600 + T D See Note 1)350oo3502501505035050502nsnsnsnsnsnsnsnsnsnsmsnsca pacitance cha racteristicsAddress Capacitance (CA )Chip Enable Capacitance (CCE )Precharge Capacitance (Cpe!ReadlWrite Capacitance (CRW )Data Input/Output Capacitance (CIN/OUT)IN - SS f = 1 MHzV VIN = -V Vss 1All unusedVIN =Vss .Inputs areVIN = Vssat AC GroundVIN = Vss5525107pFpFpFpFpFNote 1: TD = Output data to input data delay in read-modify-write cycle.Note 2: Characteristic max limits to achieve T A specifications. An increase in these times will cause T Ato increase directly.115

switching time waveformsREAD CYCLEt-------'"'----~.,I------,~,-----II------,,--~--WRITE CYCLEt--------~,~---------I------,~,-1-------,,------1'M----~~--------------------,1------ T~,,----_iDAT.: __ -'--! ___________________ ....NDII: ............................. ....connection diagramDual-In-Line Package.. ' ".,.. " ..REAOI 3" ..WRITE. 13 CKPA,ENAILE.,..12 OATAI.'OUT11 !'RECHARIiE.. ".. • VaV~TOPVIfW116

MH0007/MH0007C dc coupled MOS clock driverClock Drivers3::I:o..............3::I:o......(')general descriptionThe MH0007 is a voltage translator and powerbooster designed for interfacing between conventionalTTL or DTL voltage levels and those levelsassociated with inputs or clocks of MOS FET typedevices. The design allows the user a wide latitudein selection of supply voltages, and is especiallyuseful in normally "off" applications, since powerdissipation is typically only 5 milliwatts in the"off" state.features• 30 volts (max) output swing• Standard 5V power supply• Peak currents in excess of ±300 mA available• Compatible with all MOS devices• High speed: 5 MHz with nominal load• External trimming possible for increased performanceschematic and connection diagramVee 9---... - ......r---.--lD V'R'3kfl10 Pin TO-100 PackageINPUT I -~"""'--fV'INPUT 2 - ...... ~...-..... -- 7 OUTPUTGND4 --.... ---trTOP VIEW'------.... ----- 6 V-typical applicationsSwitching Time Test ConfigurationHigh Speed Operation2K+5.0 VOLTSINPUTINPUT-or-.......INPUTINPUTJ-"'--OUTPUT>-------~ ..... -OUTPUTlon::: 50ns} Cl =200pFtoft=: 75 85ton == 30 ns}40 CL = 200 pFtoff~ n$1........,.,,..,...-41.----_17 VOLTS117

(.)r-.oJ::E~oJ::Eabsolute maximum ratingsVee Supply VoltageV- Supply VoltageV+ Supply Voltage(V+ - V-I Voltage DifferentialInput VoltagePower Dissipation (T A = 25°C)Peak Output CurrentStorage Temperature RangeOperating Temperature Range MH0007MH0007CLead Temperature (Soldering, 10 sec)electrical characteristics (Note 1)SV-40V+2SV30V5.5VSOOmW±500mA-65°C to +150°C-55"C to +125°CO°C to +S5"C300°CPARAMETERCONDITIONSTYPMIN (Note 2)MAXUNITSLogical "1" Input Voltage Vee = 4.5V2.2VLogical "0" Input Voltage Vee = 4.5VO.SVLogical "1" Input Current Vee = 5.5V, V IN = 5.5V100 IJALogical "0" Input CurrentVee = 5.5V, V IN = O.4V1.01.5 rnALogical "1" Output VoltageVee = 5.5V, lOUT = 30 rnA, V IN = O.SVVee = 5.5V, lOUT = 1 rnA, V IN = O.SVV+ - 4.0V+ - 2.0VVLogical "0" Output Voltage Vee = 4.5V, lOUT = 30 rnA, V IN = 2.2VV- + 2.0 VTransition Time toLogical "0" Output C L = 200 pF (Note 3)50nsTransition Time toLogical "1" Output C L = 200 pF (Note 3)75nsNote 1: MinImax limits apply across the guaranteed range of -55°e to +125°e for the MHOOO7, andfrom oOe to +85°e for the MH0007e. for all allowable values of V- and V+Note 2: All typical values measured at T A = 25°C with Vee = 5.0 volts, V- = -25 volts, V+ = 0 volts.Note 3: Transition time measured from time VIN = 50% value until VOUT has reached 80% offinal value.Allowable Values for V- and V+Maximum Power Dissipationy- -40VOLTSV/•REGIONy.VOLTS ..1.2,._ 1.0e20CdSE~ 0.8;::« [""..10...ti 0.6Qa:~......AMllENT~ 0.4 ............"-... r--..... ........-10 0.2"'" ............-20 00 25 50 75 100 125 150-3QTEMPERATURE rC)-40118

Clock DriversMH0009/MH0009C dc coupled two phase MOS clock drivers:::I:oCD........s:::I:oCD(")general descriptionThe MH0009/MH0009C is high speed, DC coupled,dual MaS clock driver designed to operate inconjunction with high speed line drivers such asthe DM8830, DM7440, or DM7093. The transitionfrom TTL!DTL to MaS logic level is accomplishedby PNP input transistors which also assure accuratecontrol of the output pulse width.features• DC logically controlled operation• Output Swings - to 30V• Output Currents - in excess of ±500 nA• High rep rate - in excess of 2 MHz• Low standby powerschematic and connection diagrams9, BIAS l 2 ¢,INPUT A12 91 OUTPUT12·Lead TO-S Package¢, INPUT Arf;, INPUT B 4V- 511 V·V-IfJ:2 INPUT B 6-¢2 BIAS 1 8 ¢2 INPUT A10

u0')oooJ:~........0')oJ:~absolute maximum ratingsV- Supply Voltage: Differential (Pin 5 to Pin 3) or(Pin 5 to Pin 7)V+Supply Voltage: Differential (Pin 11 to Pin 5)Input Current: (Pin 2, 4, 6 or 8)Peak Output CurrentPower Dissipation (Note 2 and FigLlre 2)Storage TemperatureOperating Temperature: MH0009MH0009CLead Temperature (Soldering, 10 Sec.)-40V30V±75 rnA±500 rnA1.5W-65°C to +150°C-55°C to +125°CO°C to 85°C300°Celectrical characteristics (Note 1)PARAMETER CONDITIONS MINTYPMAXUNITStON CIN = .0022 pF C L = .001 pFt rise CIN = .0022 pF C L = .001 pFPulse Width (50% to 50%) CIN = .0022 pF C L = .001 pF 340t fall CIN = .0022 pF C L = .001 pFtdelay CIN = 600 pF C L = 200 pFt rise CIN = 600 pF C L = 200 pFPulse Width (50% to 50%) CIN = 600 pF C L = 200 pF 40t fall CIN = 600 pF C L = 200 pF1040400801015704035 ns50 ns440 ns120 nsnsns120 nsnsNote 1: Characteristics apply for circuit of Figure 1. With V- = -20 volts; V+ = 0 volts; VCC = 5.0volts. Minimum and maximum limits apply from _55°C to +125°C for the MH0009 and from O°C to+85°C for the MH0009C. Typical values are for T A = 25°C.Note 2: Transient power is given by P = fCl (V+ - V-I 2 watts, where: f = repetition rate, Cl = loadcapacitance, and (V+ - V-I = output swing.Note 3: For typical performance data see the MH0013/MH0013C data sheet.1.50] z 1.250;::1.0~;;;5 0.75~'"0.50..0.2500 25 50 75 100 125 150TEMPERATURE (OC)FIGURE 2. Maximum Power Dissipation120

MH0012/MH0012C high speed MOS clock driverClock Drivers3:J:oo....aN........3:J:oo....aN(")general descriptionThe MH0012/MH0012C is a high performanceclock driver that is designed to be driven by theDM7830/DM8830 or other line drivers or bufferswith high output current capability.· It will providea fixed width pulse suitable for driving MOSshift registers and other clocked MOS devices.features• High output voltage swings....:12 to 30 volts• High output current drive capability-1000 mApeak• High repetition rate-10 MHz at 18 volts into100 pF• Low standby power-less than 30 mWschematic and connection diagramsv'-8~912·lead TO·S PackageR9"0COMP 6R1250!NPUT2 3-'W."....~R21K.AS R6-- v·." jOUTPUT"'-+~~+-Ol1TOP VIEWtypical application (ac test circuit)timing diagramr-------\ 'J, OM1830/[)M8830v-" ov...-........ OUT200liFv' = 20V121

...(..)Noo::I:~........N...oo::I:~absolute maximum ratingsv- Supply Voltage: Differential (Pin 1 or 2 to Maximum Output Load-See Figure 2Pin 5) -40V Power Dissipation-See Figure I 1.5WV+ Supply Voltage: Differential (Pin B or 9 Storage Temperature _65°C to +1 50°Cto Pin I or 2) 30V Operating Temperature: MHOOl2 _55°C to +125°CInput Current: (Pin 3 or 7) ±75mA MHOOl2C O°C to +B5°CPeak Output Current ±IOOOmA Lead Temperature (Soldering, 10 sec) 300°Cdc electrical characteristics (Note 1)PARAMETER CONDITIONS MIN TYP MAX UNITSLogic "I" Input Voltage V+ - V- = 20V, VOUT r-... '"--wI -:; 15.5 i ~~ ~ ~ r--...;::-10 w!!! 10a:~5 .. -t-00 25 50 75 100 125 150 175 0 400 800 1200 16002QO 400 600 800 1000AMBIENT TEMPERATURE (OC) MAXIMUM OUTPUT LOAD (pF) LOAD CAPACITANCE, C L (pF)Figure 1. Figure 2.applications informationPower Dissipation Considerations W~ere: The transient power incurred during switching isON TimeThe power dissipated by the MHool2 may begiven by:DC = Duty Cycle = ON Time & OFF Timedivided into three areas of operation = ON, OFFPAC = (V+ - V-)2 Clf (3)and switching. The OFF power is approximately .. Y,N - V BE3and equation (I) For V' = OV, V- = -20V, Cl = 200 pF, and30 mW and is dissipated by R2 when Pin 3 is inl,N IS gIven by R,f = 5.0 MHz, PAC = 400 mW.the logic "I'" state. The OFF power is neglible and becomes:will be ignored in the subsequent discussion. TheThe total power is given by:ON power is dissipated primarily by 0 3 and Rg [(V IN - V BE3)IV-1 (V+ V-)2] PT = PAC + PON (4)PON = R, + --- DC (2)and is given by:RgPT ~ PMAX(V+ _V-)2 For Y,N = 2.5V, V BE3 = 0.7V, V+ = OV, V- = -20V, For the above example, PT = 600 mW_PON ;" [IV-II'N +---1 DC (I)Rgand DC = 20%, PON '" 200 mW.122

MH0013/MH0013C two phase MOS clock drivergeneral descriptionThe MH0013/MH0013C is a general purpose clockdriver that is designed to be driven by DTL orTTL line drivers or buffers with high output currentcapability. It will provide fixed width clockpulses for both high threshold and low thresholdMOS devices. Two external input coupling capacitorsset the pulse width maximum, below whichthe output pulse width will closely follow theinput pulse width or logic control of output pulsewidth may be obtained by using larger value inputcapacitors and no input resistors.featuresClock Drivers• High Output Voltage Swings-up to 30V• High Output Current Drive Capability-up to500 rnA• High Repetition Rate-up to 5.0 MHz• Pin Compatible with the MH0009/MH0009C• "Zero" Quiescent Powers:J:oo...aW........s:J:oo...aWC')schematic and connection diagrams02....--+.__ t-12 OUTPUT A12-Lead TO-8 PackageINPUT A1INPUT A, 4 ----+-..... --r01V- 5-----~ __ .---. ...---...--11 v'03INPUT 8, 6 ---~-..... -r'--........... -.-10 OUTPUT 804INPUT 82TOP VIEWtypical applicationsR'Nr-­II+VccC'NV-C'NR'NINPUTPULSEIIOUTPUT i :PULSE-U----;Ur-----INPUTPULSEOUTPUT I IPULSE------;U.. -----Lr-123

(.)M....o~:E.......M....o~:Eabsolute maximum ratings(v+ - v-, Voltage Differential30VInput Current (Pin 2. 4, 6 or 8)±75mAPeak Output Current±600mAPower Dissipation (Figure 7) 1.5WStorage Temperature-6SoC to +l50°COperating Temperature MHOO13_55°C to +125°CMHOO13CaOc to +85°CLead Temperature (Soldering, 60 sec 1116" from Case) 300°Celectrical characteristics (Note 1 and Figure 8)PARAMETER COND1T1DNS MIN TYP MAX UNITSLogical "0" Output Voltage lOUT = -50 rnA liN = 1.0 rnA V+ -3.0 V·-l.0 VlOUT = -lOrnA liN = 1.0 rnA V+-O.7 V· -0.5 VLogical "'" Output Voltage lOUT =50mA liN = lOrnA V- + 1.5 V- + 2.0 VVPower Supply Leakage Current (V· - V-I - 30V 1.0 100 IlAIOUT=IIN =OmANegative Input Voltage Clamp IIN=-10mA V- - 1.2 V- - 0.8 VtdON 20 35 nstds" 35 50 nsC'N - 0.0022 ~Ftd OFF (Note 2130 60R,• - onnstf811 (Note 2)CL - 0.001 ~F40 50 80 nsttall (Note 3) 40 70 120 nsPulse Width (50% to 50%) (Note 3) 340 420 490 nstrisa CIN = 500 pF 15 nstfal' R,• - on 20 nsPulse Width (50% to 50%1 (Note 31 CL - 200 pF 110 nsPositive Output Voltage Swing V+ - O.7V VNegative Output Voltage Swing V- + 0.7V VNote 1: Min/Max limits apply over guaranteed operating temperature range of _55°C to +125°C forMH0013 and O°C to +85°C for MHOO13C, with V- = -20V and V+ = OV unless otherwise specified.Typical values are for 25°C.Note 2: Parameter values apply for clock pulse width determined by input pulse width.Note 3: Parameter values apply for input pulse width greater than output clock pulse width.TABLE I. Typical Drive Capability of One Half MHOO13 at 70°C Ambient(V3 -Vz} FREQUENCY PULSE WIDTH TYPICAL R'N TYPICAL C'N OUTPUT DRIVE RISE TIMEVQLTS MHz ns !l pF CAPABILITY IN pF' LIMITns228 50 -20 4.0 100 0 750 200 716 350 1028 100 520 2.0 200 10 1600 400 1416 700 1928 400 1920 1.0 200 0 2300 1000 3416 1700 4528 2800 13020 0.5 500 10 4000 5500 18316 9300 248Note 1: Output load is the maximum load that can be driven at 70°C without exceeding the packagerating under the given conditions.Note 2: The rise time given is the minimum that can be used without exceeding the peak transientoutput current for the full rated output load.performance characteristicsFIGURE 1. Output Load vs Voltage FIGURE 2. Transient Power vs Rep. FIGURE 3. Transient Power vs Rep.Swing RatevsCL Rate vsCLt, -10 ns''''1r; "50;Y J5H'~,1 I .....IV· - V-I = 16V I, ... i IV' - V-I - 2DV10010Dl000pfI50, ••__i" II "oJ •• V600600.5 I J PDQPf3D\\ \\~ 1/ V500 ... 500~,\JOO pf I:\.\...coco~ V / /200 Pf20 406...l-400l-... II/ 't/ ./v/ / ./300...u;u; 3001"-.. ..... z~ ~OV 1/,rr-...co:..,;zco:,....,~ '" V ~ '" I /~ [\. JI / /I:- \\,,, ~..10 "4'"z20 ns 30 ns 40 ns 50 n. 60 ns '" ZOOrt V,/~~ ~ V ~ ... '" 200 IJ~ ~100I-"I~ ~-I- I-..- ,...., ~1001000 2000 30UO 0 1.0 2.0 3.0 4.0 5.0 6.0 1.0 0 I.D 2.0 3.0 4.0 5.0 6.0 1.DMAXIMUM OUTPUT LOAO IpFI REPETITION RATE IMHz) REPETITION RATE IMHzlk,r,f124

typical performance (cont.)FIGURE 4. Average Internal Power vsOutput Swing vs Duty Cycle30~,> 20 I~FIGURE 5. Typical Clock Pulse Variationsvs Ambient TemperatureTEST CIRCUIT (FIG. 8)C'N = 2200 pF -C L = 1000 pF --......V"60010% 20% 30% 40%~J / :z:I-V /'" ~0 500V 0 ~ V/ v: f% y -\50%3Ew'" ....:::0400"" r-FOR TYPICAL APPLICATION~ I--I'" ... DM7830/8830 DRIVER10lit. ~ ...FIGURE 6. RIN vs CIN vs Pulse Width~3000 I-+-+--+-t---Y~~i""-iw...ZI-...... ~ I--"" ~ 2000 ~++-tfB4..A~:J;;..."'9l-I-- ~l/f-300 r- e'N = 4300 pF CI--L = 1000 pF.....I­~ 1000 1-+---v+.J~b""'F---t-.,---i~3::xoo~w........3::xo~w(")100 200 300AVERAGE POWER (mW)400 -55 -35 -15 5 25 45 65 85 105 125AM81ENT TEMPERATURE (OC)100 200 300 400PULSE WIDTH (ns)FIGURE 7. Package Power Deratingf'f'.5"-1"\1.5~ 1.0a:w;:0...25 50 75 100 125 150 115AMBIENT TEMPERATURE eC)pulse widthMaximum output pulse width is a function of theinput driver characteristics and the couplingcapacitance and resistance. After being turned on,the input current must fall from its initial valueII N peak to below the input threshold currentliN mi n """ VB E /R 1 for the clock driver to turnoff. For example, referring to the test circuit ofFigure 8, the output pulse width, 50% to 50%, isgiven bycircuit operationInput current forced into the base of 01 throughthe coupling capacitor CIN causes 01 to be driveninto saturation, swinging the output toV- + VeE (SAT) + VDIODE.When the input current has decayed, or has beenswitched, such that 01 turns off, 02 receives basedrive through R2, turning 02 on. This suppliescurrent to the load and the output swings positiveto V+ - V BE.It may be noted that 01 always switches offbefore 02 begins to supply current; hence, highinternal transient currents from V+ to V~ cannotoccur.liN peak+ ROC IN In --- == 400 ns.liN minFor operation with the input pulse shorter thanthe above maximum pulse width, the output pulsewidth will be directly determined by the inputpulse width.Typical maximum pulse width for various CI NandRIN values are given in Figure 6.ac test circuittiming diagram- .8_ Input put ..... dth 91)% V ..~)t.. Ud.tpul. 111%"CLOCk PULSE ,;: 0" It 1.0 0" II, ~ OilounUTIIOUTV,,,-lItoSVpulse,t-500Uh.DC'50%,t,ollllt,,, Ian.Figure 8125

UM....oo::I:~.......M....oo::I:~fan-out calculationThe drive capability of the MH0013 is a functionof system requirements, i.e., speed, ambient tem·perature, voltage swing, drive circuitry, and straywiring capacity .The following equations cover the necessary calculationsto enable the fan·out to be calculated forany system condition. Some typical fan-outs forconditions are given in Table 1.Transient CurrentThe maximum peak output current of the MH0013is given as 600 mAo Average transient current requiredfrom the driver can be calculated from:C L (V+ - V-,I =TR(1)This can give a maximum limit to the load.Figure 1 shows maximum voltage swing andcapacitive load for various rise times.1. Transient Output PowerThe average transient power (P A cI dissipated isequal to the energy needed to charge and dischargethe output capacitive load (C L) multiplied by thefrequency of operation (F).PAC = C L x (V+ - V-)2 xF (2)Figures 2 and 3 show transient power for two dif·ferent values of (V+ - V-, versus output load andfrequency.2. Internal Power"0" StateNegligible «3 mW)"1" State(V+ - v-)2PINT = R2 X Duty Cycle. (3)Figure 4 gives various values of internal powerversus ouptut voltage and duty cycle.3. Input PowerThe average input power is a (unction of the inputcurrent and duty cycle. Due to input voltageclamping, this power contribution is small and cantherefore be neglected. At maximum duty cycle of50%, at 25° C, the average input power is less than10 mW per phase for R IN CI N controlled pulsewidths. For pulse widths much shorter thanRINC IN , and maximum duty cycle of 50%, inputpower could be as high as 30 mW, since II N peak ismaintained for the full duration of the pulsewidth.4. Package Power DissipationTotal Average Power = Transient Output Power +Internal Power + InputPowerTypical Example Calculation for One HalfMH0013CHow many MM506 shift registers can be driven byan MH0013C driver at 1 MHz using a clock pulsewidth of 400 ns, rise time 30-50 ns and 16 voltsamplitude over the temperature range 0-70°C?Power DissipationFrom the graph of power dissipation versus temperature,Figure 7, it can be seen that anMH0013C at 70°C can dissipate lW without a heatsink; therefore, each half can dissipate 500 mW.Transient Peak Current LimitationFrom Figure 1 (equation 1), it can be seen thatat 16V and 30 ns, the maximum load that can bedriven is limited to 1140 pF.Average I nternal PowerFigure 4 (equation 3) gives an average power of102 mW at 16V 40% duty cycle.Input power will be a maximum of 8 mW.Transient Output PowerFor one half of the MH0013C500 mW = 102 mW + 8 mW+ transient output power390 mW = transient output powerUsing Figure 2 (equation 2) at 16V, 1 MHz and390 mW, each ha'lf of the MH0013C can drive a1520 pF load. This is, however, in excess of theload derived from the transient current limitation(Figure 1, equation 1), and so a maximum loadof 1140 pF would prevail.From the data sheet for the MM506, the averageclock pulse load is 80 pF. Therefore the numbero f d eVlces· d'riven.IS 801140or 14registers..For nonsymmetrical clock widths, drive capabilityis improved.126

MH0025/MH0025C two phase MOS clock drivergeneral descriptionThe MH0025/MH0025C is monolithic, low cost,two phase MOS clock driver that is designed to bedriven by TTL/DTL line drivers or buffers such asthe DM932, DM8830, or DM7440. Two inputcoupling capacitors are used to perform the levelshift from TTL/DTL to MOS logic levels. Optimumperformance in turn-off delay and fall time areobtained when the output pulse is logically controlledby the input. However, output pulse widthsmay be set by selection of the input capacitorseliminating the need for tight input pulse control.featuresClock Drivers• 8-lead TO-5 or 8-lead dual-in-line package• High Output Voltage Swings-up to 30V• High Output Current Drive Capability-up to1.5A• Rep. Rate: 1.0 MHz into> 1000 pF• Driven by DM932, DM8830, DM7440(SN7440l• "Zero" Quiescent Power3::x:ooN(J1,3::x:ooN(J1(')connection diagramsMetal Can PackageDual-In-Line PackageN.C 1 8 N.C,INPUT A 2 ---II...--C>o---+- 7 OUTPUT Av- , 6 v'v-Note: Pin 4 connected to case,TOPVIEWMH0025H, MH0025CHINPUT B 4:>0---+- 5 OUTPUT BTOP VIEWMH0025CNtypical applicationac test circuittiming diagramIllputwavefolm"PRR '" 0.5 MHlVp_p = 5.0V1,=I,

(.)LonNo::t~"'­LonNo::t~absolute maximum ratings(v+ - V-) Voltage DifferentialInput CurrentPeak Output CurrentPower DissipationStorage TemperatureOperating Temperature MH0025MH0025CLead Temperature (Soldering, 10 sec)30V100 mA1.5ASee Curves-65°C to +150°C-55°C to +125°CO°C to +85°C300°Celectrical characteristics (Note 1) See test circuit.PARAMETER CONDITIONS MIN TYP MAX UNITSTdON '" 15T rlse CIN = .001 /IF 25TdoFF (Note 2)>-RIN = OD30T fall (Note 2) C L = .001 /IF 60 90T fall (Note 3) 100 150P.w. (50% to '50%) (Note 3) ..) 500Positive Output Voltage Swing VIN = OV, lOUT = -1 mA V+ - 1.0 V+ - 0.7VNegative Output Voltage Swing liN = 10 mA, lOUT = 1 mA V- + 0.7V30 ns50 ns60 ns120 ns250 nsnsVV- + 1.5V VNote 1. Min/Max limits apply across the guaranteed operating temperature range of -55°C to +125°Cfor MH0025 and O°C to 85°C for MH0025C. Typical values are for +25°C.Note 2. Parameter values apoly for clock pulse width determined by input pulse width.Note 3. Parameter values apply for input pulse width greater than output clock pulse width.performance characteristics~Z0;::~~Qa:~:;;::;:::>:;x«:;Package Power Derating Transient Power vs Rep. Rate DC Power (PDC) vs Duty Cycle400160_o-MH0025H &MH0025CH STILL AIR CL e 20110 pF I. Ir C "1000 JlFCL ~ 1500 pF Ilv' - V- = 20V/X1.4140- MH0025CN SOLDERED INTO PCV CL=;SDPF §:BDARD WITH 8 Cu CONDUCTORS §"/ / V1.2 300 -S 120~~~]16V2 OZ •. 03 IN. WIDE -Sza: 'I V /0/ V 71.0;:: 100~r"\ ~ :;;: /11/4~~/ V /...... V0.8 ~ 200 0; 80I ....,....::'\.~ 1/ / / V CL = J50 pF '" Q/ /0.61./;;, -V-= 12V-0;a: 602:'~« r// V ./ .... ~~ V V0.4a: 100 :;;: 40...."~ ~ V k::::::: ~ ~=200pF J. ~ Vu0 20~ p- v+ - v- ~ 16VIP0.20-25 0 25 50 75 100 125 150 0 .5 1.0 1.5 2.0 0 10 20 30 40 50 60 70 85TEMPERATURE (OC) PULSE REPETITION RATE (MHz) DUTY CYCLE (%)PAC = (V' - V-)2f CLP De ;::(V' - V-)2 (DC)lk3200~ 2800u~ 2400~ 2000....~ 1600~ 1200Q~ 800400oMaximum Load Capacitance\\ '

applications informationCircuit OperationInput current forced into the base of Q 1 through thecoupling capacitor CIN causes Q, to be driven intosaturation, swinging the output to V- + V CE(sat) +VDiode'When the input current has decayed, or has beenswitched, such that Q, turns off, Q 2 receives basedrive through R 2 , turning Q 2 on. This suppliescurrent to the load and the output swings positiveto V+ - VBE .It may be noted that Q, must switch off beforeQ2 begins to supply current, hence high internaltransients currents form V- to V+ cannot occur.INPUTR1250 .4~Ol,---.....-ov·:~; J~2:.--j.............-O OUTPUTiL---+--~-----ov-FIGURE 1. MH0025 Schematic (One-Half Circuit)culations to enable the fan-out to be calculatedfor any system condition.Transient CurrentThe maximum peak output current of the MH0025is given as 1.5A. Average transient current requiredfrom the driver can be calculated from:Typical rise times into 1000 pF load is 25 nsFor V+ - V- = 20V, I = O.SA.Transient Output PowerThe average transient power (Pac) dissipated, isequal to the energy needed to charge and dischargethe output capacitive load (Cd multiplied by thefrequency of operation (fl.(nPAC = C L x (V+ - V-)2 X f (2)For V+ - V- = 20V, f = 1.0 MHz, C L = 1000 pF,PAC = 400 mW .Internal Power"0" State Negligible «3 mW)"1" States:~oN(J1........s:~oN(J1("')Fan-Out CalculationThe drive capability of the MH0025 is a functionof system requirements, i.e. speed, ambient temperature,voltage swing, drive circuitry, and straywiring capacity.= 80 mW for V+ - V- = 20V, DC = 20%Package Power DissipationTotal average power = transient output power +internal power(3)The following equations cover the necessary calexampIe calcu lationHow many MM506 shift registers can be driven byan MH0025CN driver at 1 MHz using a clock pulsewidth of 200 ns, rise time 30-50 ns and 16V amplitudeover the temperature range 0-70°C?Power Dissipation:At 70°C the MH0025CN can dissipate 630 mWwhen soldered into printed circuit board.Transient Peak Current Limitation:From equation (1 L it can be seen that at 16V and30 ns, the maximum load that can be driven islimited to 2800 pF.Average I nternal Power:Equation (3), gives an average power of 50 mW at16V and a 20% duty cycle.For one half of the MH0025C, 630 mW","" 2 can bedissipated.315 mW = 50 mW + transient output power265 mW = transient output powerUsing equation (2) at 16V, 1 MHz and 250 mW,each half of the MH0025CN can drive a 975 pFload. This is, less than the load imposed by thetransient current limitation of equation (n andso a maximum load of 975 pF would prevail.From the data sheet for the MM506, the averageclock pulse load is 80 pF. Therefore the number975of devices driven is 00 or 12 registers.129

(.)

absolute maximum ratings (Notes 1 & 2)V+ -V- Differential VoltageInput CurrentInput Voltage (V IN - V-)Peak Output CurrentPower DissipationOperating Temperature RangeMH0026MH0026CStorage Temperature RangeLead Temperature (Soldering, 10 sec)22V100 mA5.5V1.5ASee curves-55°C to +125°CO°C to 85°C-65°C to +150°C300°C~J:ooNen" ~J:ooNenndc electrical characteristicsPARAMETERCONDITIONSMINLIMITSTYPMAXUNITSLogic "1" Input Voltage V OUT = V- + 1.0V 2.51.5VLogic "1" Input Current VIN - V- = 2.5V, V OUT = V- + 1.0VLogic "0" Input Voltage V OUT = V+ - 1.0V100.615OAmAVLogic "0" Input Current VIN - V- = OV, V OUT = V+ - 1.0VLogic "0" Output Voltage V+ = +5.0V, V- = -12.0VVIN=-11.6 4.0-0.0054.3-10IlAVLogic "0" Output Voltage VIN - V- = OAV V+ - 1.0V+ - 0.7VLogic "1" Output Vol1:ageV+ = +5.0V, V- = -12.0VVIN = -9.5V-11.5-11.0VLogic "1" Output Voltage VIN - V- = 2.5VV- + 0.5V- + 1.0V"ON" Supply Current V+ - V- = 20V, VIN - V- = 2.5V3040mA"OFF" Supply CurrentV+ - V- = 20V, VIN - V- = O.OV10100IlAac electrical characteristics (Notes 1 & 2, AC test circuit)Turn·On Delay (tON)5.07.512nsTurn·Off Delay (tOFF )5.01215nsRise time (t r ) - Note 3V+ - V- = 17V, C L = 250 pF12nsV+ - V- = 17V, C L = 500 pF1518nsC L = 1000 pF2035nsFalltime (t!) - Note 3V+ -V-= 17V,C L =250pF10nsV+ -V-= 17V,C L =500pF1216nsC L = 1000 pF1725nsNote 1: These speci fications apply for V+ - V- = 10V to 20V, CL = 1000 p F, over the temperaturerange -55°C to +125°C for the MH0026 and O°C to +85°C for the MH0026C.Note 2: All typical values for the T A = 25°C.Note 3: Rise and fall time are given for MOS logic levels; i.e., rise time is transistion from logic "0" tologic "1" which is voltage fall. See waveforms on page 133.131

oCDNo::x:::E........CDNo::x::Etypical performance characteristicsTO-5 & DIP Power Ratings1.2MH0026CN SOLDERED TO PCBOARD WITH 8 cu. CONDUCTORS1.0 - 2 oz., .OJ IN. WIDEa: 0.4~~0.23.02.5~z1:1 2.0;::::;;; 1.5'" Cia:l:1:1"-1.00.5TO-S Package Power RatingMH0026G AND MH0026CG INSTILL AIR WITH CLIP-ONHEAT SINK (THERMALLOYTYPE 215-1.9 OR EOUIV.!;:..§a:l:1:1"-400DC Power (PDC) vsDuty CycleTA : 25°C./360 CL : 0V320V· - V-: 20V-----,./ V2BOV'-V-:17~:-:--:,240 V· - V-: 12V ILIX /'200160.12 ./"120V l.Y/y VBO40~, [.' (V' _ V-1 2Poe: ~(DCI25 50 75 100 125 15025 50 75 100 125 15010 20 3D 40 50 60 70 BOAMBIENT TEMPERATURE (OC)AMBIENT TEMPERATURE (OCIDUTY CYCLE (%1;:900BOO700..§a:w600;:1:1 500"-I-~ 400;;;z 300"" a:I- 200100Transient Power (PAC) vsFrequencyCL =2000 pFJ V t - V-: 17VIVCL = 1000 pfII II I I V-iCL = 500Pj..VIII V1II II VI I/ VCL200~ I---Z V -~~ ~ l- I I1.0 2.0 3.0 4.0 5.0 .crB.5B.O..§I-~ 7.5a:a::0...,7.0::ll:.,:06.5Supply Current vs TemperatureDUTY CYCLE: 20%f: 1 MHzICL : 0I--'I-"V+-v : 20V~v' -V-: 17VI- V6.0-75 -50 -25 0 25 50 75 100 125cr..§I-~a:a::0...,I- :0"-~16141210Input Current vs Input VoltageTA:25°Cv t = 20VV- = ov1/l/V./~ ~0.5 1.0 1.5 2.0 2.5FRE~UENCY (MHz)TEMPERATURE (OCIINPUT VOLTAGE (V)!~;::w'" a:25201510Rise Time vs Load Capacitancev· - V- = 20~~t:I;.:V~~ 10-'1"-V V· - V-= 17V~ Ro : 50ilTA = 25°C200 400 600 BOD 1 DOD 12002520!w:;;;:: 15~~~10Fall Time vs Load CapacitanceIV· - V- = 15V to 20VV "l-"" ............ ~/ '"Ro = 501lTA = 25°C5o 200 400 600 BOD 1 DOD]::cl- eiw~~I-~I-:01:1BOD700600500400300200100Optimum Input Capacitance vs.Output Pulse WidthV· - V- = 20VCL = 1000 pfTA : 25°C/ .......... " I'",-/200 400 600 BOO 1000 1200LOAD CAPACITANCE (pflLOAD CAPACITANCE (pf)INPUT CAPACITANCE, C'N (pf)14~ 13'"~ 12;::"-"-1:1Za::0I-'" Z1:1Za::0I-II10Turn-On & Turn-Off Timevs TemperatureIt 1_ I I-V -V =204C'N : CL : 1000 pf- Ro = 50HI' V./tON1/~ V./ ~.......ton J"... .....-/'--75 -50 -25 0 25 50 75 100 125TEMPERATURE (OC)]:g;::., u.oRise Time vs Temperature25V· - V-: 20VCL - 1000 pf20~CL~~15 -10a: CL - 0-75 -50 -25 0 25 50 75 100 125TEMPERATURE (OC)!:g;::~~25201510Fall Time vs Temperaturer-- V! - V: = 2~VIICL \000 ~f-L -i-" r-CL ~ 500'pf--'V-I--'r-1 VCL : 0- l..-rI-75 -50 -25 0 25 50 75 100 125TEMPERATURE eC)132

typical applicationsIfOP~T"IfOPUT"DC Coupled MOS Clock DriverTransistor Coupled MOS Clock Driver}'""'''REGISTERS3:J:oN0)........3:J:oN0)(")Logically Controlled AC Coupled Clock Driver}TO ~OOITIOII"'"SHIFTAEGISHRS'O_----1~CUICKINPUT_2Io• b O~'SHOT OUTPUT _ ADJPUL$EWIOTHPHASE ONE OUTPUTPIIASE TWO OUTPUTPrecharge Driver for MOS RAM Memories."",,""'---l-.l---"'"-----------'--------jac test circuitswitching time waveforms~ltF ==~VMH'I'W=U",~= ~ ,len,133

uCDNoJ:~........CDNoJ:~application information1.0 IntroductionThe MH0026 is capable of delivering 30 wattspeak power (1.5 amps at 20V needed to rapidlycharge large capacitative loads) while its package islimited to the watt range. This section describesthe operation of the circuit and how to obtainoptimum system performance. If additional designinformation is required, please contact your localNational field application engineer.2.0 Theory of OperationConventional MOS clock drivers like the MH0013and similar devices have relied on the circuitconfiguration in Figure 1. The AC coupling of aninput pulse allows the device to work over a widerange of supplies while the output pulse widthmay be controlled by the time conStant - RJ X CJ.a simplified diagram, OJ (Figure 3) provides 0.7Vdead zone so that Q3 is turned ON for a risinginput pulse and Q 2 OFF prior to QJ turning ON afew nanoseconds later. O 2 prevents zenering of theemitter·base junction of Q 2 and provides an initialdischarge path for the load via Q3' During a fallinginput, the stored charge in Q3 is used beneficiallyto keep Q3 ON thus preventing Q 2 from conduct·ing until QJ is OFF. QJ stored charge is quicklydischarged by means of common-base transistorQ4'The complete circuit of the MH0026 (see schematicon page 130 basically makes Darl ingtons outof each of the transistors in Figure 3....---+-ov·,..--..... -ov·EXTERNALClIN~ r-o"-"""'-0 OUTEXTERNALClIN~ r-o01RlOUTt-4~-+-... o v-L-..... -.... -ov-FIGURE 1. Conventional MOS Clock DriveFIGURE 3. Simplified MH0026O 2 provides 0.7V of dead-zone thus preventing QJand Q 2 from conducting at the same time. Inorder to drive large capacitive loads, QJ and Q 2are large geometry devices but COb now limitsuseful output rise time. A high voltage TTL outputstage (Figure 2) could be used; however, duringswitching until the stored charge is removed fromQJ , both output devices conduct at the same time.This is familiar in TTL with supply line glitches inthe order of 60 to 100 mAo A clock driver builtthis way would introduce 1.5 amp spikes into thesupply lines....--..... -ov·When the output of the TTL input element (notshown) goes to the logic "1" state, current issupplied through CIN to the base of QJ and Q 2turning them ON, and Q 3 and Q 4 OF F when theinput voltages reaches 0.7V. Initial discharge ofthe load as well as E-B protection for Q 3 and Q 4are provided by Oland D 2 . When the inputvoltage reaches about 1.5V, Q 6 and Q7 begin toconduct and the load is rapidly discharged by Q7'As the input goes low, the input side of CIN goesnegative with respect to V- causing Q 8 and Q 9 toconduct momentarily to assure rapid turn-off ofQ 2 and Q7 respectively. When Q 1 and Q 2 turnOFF, Darlington connected Q 3 and Q 4 rapidlycharge the load toward V+ volts. R6 assures thatthe output will reach to within one V SE of theV+ supply.EXTERNALClIN~ r-o01OUTThe real secret of the device's performance isproper selection of transistor geometries and resistorvalues so that Q 4 and Q 7 do not conduct atthe same time while minimizing delay from inputto output.L-..... ~-~-t-ov-FIGURE 2. Alternate MOS Clock DriveUnique circuit design and advanced semiconductorprocessing overcome these clasic problems allow·ing the high volume manufacture of a device, theMH0026, that delivers 1.5A peak output currentswith 20ns rise and fall times into 1000pF loads. In3.0 Power Dissipation ConsiderationsThere are four considerations in determiningpower dissipations.1. Average DC power2. Average AC power3. Package and heat sink selection4. Remember-2 drivers per package134

application information (con't)The total average power dissipated by the MH0026is the sum of the DC power and AC transientpower. The total must be less than given packagepower ratings.Since the device dissipates only 2mW with outputvoltage high (MaS logic "0"), the dominatingfactor in average DC power is duty cycle or thepercent of time in output voltage low state (MaSlogic "1 "). Percent of total power contributed byP De is usually neglible in shift register applicationswhere duty cycle is less than 25%. PDe dominatesin RAM address line driver applications whereduty cycle can exceed 50%.3.1 DC Power (per driver)DC Power is given by:PDe = (V+ - V-) X (IS(Low») X( ON time )OFF time-ON timeor PDe = (Output Low Power) X (Duty Cycle)+ _ Vswhere: IS(Low) = Is@V -V = 20VExample 1: (V+ = +5V, V- = -12Vja) Duty cycle = 25%, thereforePDC = 17V X 40mA X 17/20 X 25%P DC = 145mW worst·case, each sidePDC = 109mW typicallyb) Duty cycle = 5%PDC = 21mWc) See graph on page 132The above illustrates that for shift register applica·tions, the minimum clock width allowable for thegiven type of shift register should be used in orderto drive the largest number of registers per clockdriver.Example 2: (V+ = +17V, V- = GNDj:a) Duty cycle = 50%P De = 290mW worst-casePDe = 218mW typicallyb) Duty cycle = 100%PDC = 580mWThus for RAM address line applications, packagetype and heat sink technique will limit drivecapability rather than AC power.3.2 AC Transient Power (per driver)AC Transient power is given by:P =AC(V+ - V-)2 X f X Cwhere: f = frequency of operationCL = Load capacitance (includ ing allstrays and wiring)Example 3: (V+ = +5V, V- = -12VjPAC = 17 X 17 X f(MHz) X 10 6 XC L (nF) X 10- 9PAC = 290mW per MHz per 1000pFThus at 5MHz, a 1000pF load will cause any driverto dissipate one and one half watts. For long shiftregisters, a driver with the highest package powerrating will drive the largest number of bits for thelowest cost per bit.3.3 Package SelectionPower ratings are based on a maximum junctionrating of 175°C. The following guidelines aresuggested for package selection. Graphs on page 132illustrate derating for various operating temperatures.3.31 TO-5 rH") Package: Rated at 600mW stillair (derate at 4.0mWtC above 25°C) and 900mWwith clip on heat sink (derate at 6.0mWtC above25° C). This popular hermetic package is recommendedfor small systems. Low cost (about 10¢)clip-on-heat sink increases driving capability by50%.3.32 8-Pin ("N") Molded Mini-DIP: Rated at600mW still air (derate at 4.0mWtC above 25°C)and 1.0 watt soldered to PC board (derate at6.6mWtC). Constructed with a special copperlead frame, this package is recommended formedium size commercial systems particularlywhere automatic insertion is used. (Please note forprototype work, that this package is only rated at600mW when mounted in a socket and not onewatt until it is soldered down.)3.33 TO-8 ("G") Package: Rated at 1.5 wattsstill air (derate at 10mWtC above 25°C) and 2.3watts with clip on heat sink (Thermalloy type215-1.9 or equivalent-derate at 15mWtC).Selected for its power handling capability andmoderate cost, this hermetic package will drivevery large systems at the lowest cost per bit.L~J:ooNm.......~J:ooNm(')135

()coNoJ::E........CONoJ::Eapplication information (con'tl3.4 Summary-Package Power ConsiderationsThe maximum capacitative load that the MH0026can drive is thus determined by package type, heatsink technique, ambient temperature, AC power(which is proportional to frequency and capacitiveload) and DC power (which is principally determinedby duty cycle). Combining equations previouslygiven, the following formula is valid forany clock driver with negligible input power andnegligible power in output high state:10-3C L (max in pF) = -n- XP max(mW) (T A ,pkg) X Req - (v+ - V-,' X (Dc) X 10 3(VT _ V )' X Req X f(MHz)C L (max in pF) = .5 X 10- 3 XPmax(mW) X 500- Vs ' X DcX 10 3Vs ' X 500X f(MHz)Where: n = number of drivers per pkg. (2 forthe MH0026)Pm ax( mW) (T A' pkg) = Package powerrating in milliwatts for given package,heat sink, and max, ambient temperature(See graphs)Req = equivalent internal resistanceReq = (V+ - V-)/IS(LOW) = 500 ohms (worstcase over temperature for the MH0026 or660 ohms typically)Vs = (V+ - V-) = total supply voltage acrossdeviceDc = Duty Cycle =Time in output low stateTime in output low + Time in output high stateTable I illustrates MH0026 drive capability undervarious system conditions.4.0 Pulse Width ControlThe MH0026 is intended for applications in whichthe input pulse width sets the output pulse width;i.e., the output pulse width is logically controlledby the input pulse. The output pulse width is givenby:) _ tr +t f _(PW OUT - (PW)IN+ - PW IN+25nsTwo external input coupling capacitors are required to perform the level translation betweenTTL!DTL and MOS logic levels. Selection of thecapacitor size is determined by the desired outputpulse width. Minimum delay and optimum performanceis attained when the voltage at the inputof the MH0026 discharges to just above thedevices threshold (about 1.5V). If the input isallowed to discharge below the threshold, to F Fand t f will be degraded. The graph on page 132shows optimum values for CIN vs desired outputpulse width. The value for CIN may be roughlypredicted by:CIN = (2 X 10- 3 ) (PW)OUTFor an output pulse width of 500ns, the optimumvalue for C 1 N is:C 1 N = (2 X 10- 3 )(500 X 10- 9 ) == 1000pF5.0 Rise & Fall Time Considerations(Note 3)The MH0026's peak output current is I imited to1.5A. The peak current limitation restricts themaximum load capacitance which the device iscapable of driving and is given by:dvI = C l dt .;;; 1.5AThe rise time, t r, for various loads may bepredicted by:tr = (LW)(250 X 10- 12 + C l )Where: f-,.V = The change in voltage across Cl== V+ - V-CL = The load capacitanceFor V+ - V- = 20V, CL = 1000pF, tr is:tr == (20V)(250 X 10- 12 + 10- 12 )= 25nsTABLE 1. Worst Case Maximum Drive Capability for MH002S*TO·8WITH TO-8 MINI-DIP TO-S AND MINI·DIPPACKAGE TYPE HEAT SINK FREE AIR SOLDERED DOWN FREE AIRMax.Max. AmbientOperatingFrequency I ~Duty Cycle60°C 85°C BO°C 8SoC BO°C 85°C 60°C 8SoC100kHz 5% 30 k 24 k 19 k 15 k 13 k 10k 1.Sk 5.""500kHz 10% 6.5k 5.1k 4.1k 3.2k 2.7k 2k 1.5k 1.1klMHz 20% 2.9k 2.2k 1.8k 1.4k 1.1k 840 600 4302MHz 25% 1.4k 1.1k 850 650 550 400 280 1905MHz 25% 620 470 380 290 240 170 120 8010MHz 25% 280 220 170 130 110 79 - -·NOTE: Values in pF and assume both sides in use as non-overlaping 2 phase driver; each sideoperating at same frequency and duty cycle with (V + - V -) = 17 V136

application information (con't)For small values of C L , equation above predictsoptimistic values for t r. The graph on page 132shows typical rise times for various load capacitances.The output fall time (see Graph) may be predictedby:tf = 2.2R(Cs + ~6.0 Clock OvershoothF E + 1The output waveform of the MH0026 can overshoot.The overshoot is due to finite inductance ofthe clock lines. It occurs on the negative goingedge when Q 7 saturates, and on the positive edgewhen Q 3 turns OFF as the output goes throughV+ - Vbe . The problem can be eliminated byplacing a small series resistor in the ouput of theMH0026. The critical valve for Rs = 2VLCL whereL is the self-inductance of the clock line. Inpractice, determination of a value for L is ratherdifficult. However,Rs is readily determined emperically,and values typically range between 10 and51 ohms. Rs does reduce rise and fall times asgiven by:7.0 Clock Line Cross TalkAt the system level,voltage spikes from ¢l may betransmitted to 1>2 (and vice-versa) during thetransition of 1> 1 to MaS logic "1". The spi ke isdue to mutual capacitance between clock lines andis, in general, aggravated by long clock lines whennumerous registers are being driven. TransistorsQ3 and Q4 on the 1>2 side of the M H0026 areessentially "OFF" when 1>2 is in the MaS logic"0" state since only micro-amperes are drawnfrom the device. When the spike is coupled to ¢2,the output has to drop at least 2 VB E before Q 3and Q 4 come on and pull the output back to V+A simple method for eliminating or minimizingthis effect is to add bleed resistors between theMH0026 outputs and ground causing a current ofa few milliamps to flow in Q4. When a spike iscoupled to the clock line Q 4 is already "ON" witha finite hfe' The spike is quickly clamped by Q4'Values for R depend on layout and the number ofregisters being driven and vary typically between2k and 10k ohms.8.0 Power Supply DecouplingPower supply decoupling is a widespread andaccepted practice. Decoupling of V+ to V- supplylines with at least 0.1 /IF non inductive capacitorsas close as possible to each MH0026 is stronglyrecommended. This decoupling is necessarybecause otherwise 1.5 ampere currents flow duringlogic transition in order to rapidly charge clocklines.3::x:oN0).........3::x:oN0)"137

Clock DriversMH0027C dual high speed MOS interface drivergeneral descriptionThe MH0027C is a dual high current active pull-updesigned to operate with a high current sink suchas the DH0034 or LM7541 A and thus provides fullyTTL compatible DC coupled inputs. The partitioningof current sinks and sources into separatepackages provides higher overall power drive capabilitywhile minimizing system cost. The device isintended for use as a driver for MOS RAM memoriessuch as the MM1103. The MH0027C is capable ofsourcing over 1 ampere peak current with a risetimeof 25 ns into 600 pF loads.features• Fast rise times - 25 ns into 600 pF load• Peak output current in excess of 1 ampere• Fully compatible with DH0034 dual level shifterand LM75450 series peripheral drivers.• Wide operating supply range -• Output voltage clamp5V to 25V• Low power dissipation - 1 mW typical inlogic "1" stateThe MH0027C operates over an ambient temperaturerange of O°C to +85°C and is supplied in aminiature 8-pin molded dual-in-line package.schematic and connection diagramsDual-In-Line Package6INPUT ANC2., .2~ ~ 031k ~~ 01 1kINPUT AINPUT B~ 011 4".!.OUTPUT A~,. 0' 07,j" 06• ~O,o~.... ....7•~ 02,j" 09OUTPUT B,V-"'>----+!-- OUTPUT AV- V'INPUT 8OUTPUT BTOP VIEWtypical applicationsTTL to MM1103 High Speed Memory InterfaceTTL to Negative level Interface(DC Coupled MOS Clock)m "I' .,INPUTS 8TT~lAINPUTS'S"I~ToMM1IG34kl>y16b,t mfmO'Y"'·y·R;".ndfaurim•• reZ5 nI'ypi.,.6II0pFI.,dm!AINPUTSIBJINPUTS ml' B 13I .-..~1 I Oulpu, Mlnr- -I1V'0 4V. dofaylirnl- 2901¢.,jR" •• ndfalilfme-25 n,'O,Cl .600 PFNOb, Minimiztmov lHIon! copoo:itln .. on ;o,.,,'''""..'i......._LM75451A Ind MH0027CN.Oplio"'.>

absolute maximum ratingsContinuous Supply VoltagePeak Supply Voltage (10 ms)Input VoltageOutput VoltagePeak Output Current (each side)Power Dissipation (Note 1)Operating Temperature RangeStorage Temperature RangeLead Temperature (Soldering, 10 sec)25V30V25VVee1.2A1.0WO°Cto 85°C-65°C to +150°C300°C~J:oN.....(")electrical characteristics (T A = +25°C, v+ = 24V, VeL = 21V; unless otherwise specified)PARAMETERCONDITIONSLIMITSMIN TYP MAXLow Level Input Current (IlL) V IN = OV 18 25 32 mAHigh Level Output Voltage (VOH ) IOH = 4 mA 20.75 21.0 21.25 VLow Level Output Voltage (Vod IOL = 100 mA 0.7 1.0 VTurn-On Time (t dON ) CL = 600 pF 5 15 nsTurn-Off Time (tdOFF ) CL = 600 pF 5 15 nsRise Time (t,) CL = 600 pF 20 45 nsFall Time (tf) CL = 600 pF 15 35 nsNote 1: Rating applies for device soldered to a printed circuit board with 8 copper conductors.03 inches wide. For ambient temperatures above 25°C, derate linearly at 6.7 mwtC.UNITSFor specifications on other National MOS clockdrivers and interface circuits, see the followingdata sheets:MOS Clock DriversSingle Phase, TTL Input DC Coupled -Two Phase DC Coupled - MH0009Single Phase, High Speed DC Coupled -Two Phase AC Coupled - MH0013Two Phase Low Cost - MH0025Two Phase High Speed AC Coupled -MH0007MH0012MH0026MOS Interface CircuitsDual Voltage Translator - DM7800/DM8800Dual High Speed Translator - DH0034/DH0034CQuad 2-lnput NAND TTL/MOS Interface -DM8810,DM8811Quad 2-lnput AND TIL/MOS Interface - DM8810Hex Inverter TTL/MOS Interface - DM8812Dual Peripherial Drivers - LM350,LM351/LM 75450A, LM 75451 AAnalog Comparator to MOS - LM 111 seriesDual Analog Comparator to MOS - LH2111 series139

Analog SwitchesMM450/MM550, MM451/MM551MM452/MM552, MM455/MM555 MOS analog switchesgeneral descriptionThe MM450, and MM550 series each containfour p channel MOS enhancement mode transistorsbuilt on a single monolithic chip. The fourtransistors are arranged as follows:MM450, MM550MM451, MM551MM452, MM552MM455, MM555Dual DifferentialSwitchFour ChannelSwitchFour MOS TransistorPackageThree MOS TransistorPackageThese devices are useful in many airborne andground support systems requiring multiplexing,analog transmission, and numerous signal routingapplications. The use of low threshold transistorsschematic and connection diagrams(VTH = 2 volts) permits operations with large analoginput swings (± 10 volts) at low gate voltages(-20 volts). Significant features, then, include:• Large Analog Input Swing ±10 Volts• Low Supply Voltage V SULK = +10 Volts• Low ON Resistance V INV 1N• Low Leakage Current• Input Gate Protection• Zero Offset VoltageVGG = -20 Volts-10V 150D.+10V 75D.200 pA @ 25°CEach gate input is protected from static chargebuild-up by the incorporation of zener diode protectivedevices connected between the gate inputand device bulk.TOP VIEWN.C.TOPYIEWOUTPUT(SOURCEIBULKDRAIN'TOPI/IEW" SOURCE4GATE 4TOPI/IEWGATE 2GATE 1SOURCE 1SOURCEJDRAIN 2GATE JGATE 2DRAIN 3BULKBULKSOURCE 2NOTE; Pin 5 connected to tlse and device bUlle.MM450, MM550NOTE: Pin 5 connected to case and device bulk.MM451, MM551NOTE 1: Pins 1 and 8 connected to case anddevice bulk. Drain and Source may beinterchanged. MM452f, MM552F.typical applicationsNOTE 2: MM452D and MM552D (dual-in-linepackages) have same pin connectiong asMM452F and MM552F shown above.BULKNOTE: Pin 5 connected to case and device bulk.Drain and Source may be interchanged.MM455. MM555EQUIVALENTCIRCUIT~pTOGGLEo--i-+--+-"-+~I--+.....IINPUT 0--;-+--+---+--'I L ______ _SWITCH ifIOUTPUTI1IIII_J1MM451~------'.---__..,11r---+II1OUTPUTINTElLIGENCEDPDT Analog Switch4-Channel Multiplexer**Expansion in the number of data input lines ispossible by using multiple level series switchesallowing the same decode gates to be used forall lower rank decoding.DPST Hi h-Frequency Switch141

ininin::?i::?iabsolute maximum ratingsMM450, MM451, MM452, MM455MM550, MM551, MM552, MM555Gate Voltage (VGG) +10V to -30V +10V to -30VBulk Voltage (V BULK) +10V +10V.........Analong Input (V IN ) +10V to -20V +10V to -20VininPower Dissipation 200 mW 200 mWlilt Operating Temperature _55°C to +125°C _25°C to 70°CStorage Temperature _65°C to +150°C _65°C to +l50°C::?i::?i~Nininelectrical cha racteristicsSTATIC CHARACTERISTICS (Note 1)PARAMETER CONDITION MIN TYP MAX UNITS::?i Analog Input Voltage ±10 V::?i Threshold Voltage (V GS(T)) VOG = O. 10 = 1 pA 1.0 2.2 3.0 V.........NON Resistance V IN = -10V 150 600 ninliltON Resistance V IN = Vss 75 200::?in::?i OFF Resistance 10 10 nGate Leakage Current (IGSS) VGS = -25V. VSS = O. T A = 25°C 20 pAinin Input (Drain) Leakage Current::?i MM450. MM451. MM452. MM455 TA = 25°C .025 100 nA~..-::?i TA = 85°C .002 1.0 pA...........-TA = 125°C .025 1.0 pAinlilt Input (Drain) Leakage Current::?i MM550, MM551, MM552, MM555 T A = 25°C 0.1 100 nA::?i T A = 70°C .030 1.0 pA~0 Output (Source) Leakage Currentinin::?iMM450. MM451. MM452, MM455 T A =25°C .040 100 nAOutput (Source) Leakage Current::?i MM450 TA = 85°C 1.0 pA.........0 MM451 TA = 85°C 1.0 pAin MM452. MM455 T A = 85°C 1.0 pAlilt MM450. MM451. MM452. MM455 TA =125°C 1.0 pA::?i::?i142Output (Source) Leakage CurrentMM550 T A = 70°C 1.0 pAMM551 T A = 70°C 1.0 pAMM552. MM555 TA = 70°C 1.0 pADYNAMIC CHARACTERISTICSLarge Signal TransconductanceCAPACITANCE CHARACTERISTICS (Note 2)Vos = -10V, 10 = 10 mAf = 1 kHz4000 pmhosPARAMETER DEVICE TYPE MIN TYP MAX UNITSAnalog Input (Drain) Capacitance (Cos) ALL 8 10 pFOutput (Source) Capacitance (C SB )Gate Input Capacitance (CGs)MM450. MM550 11 14 pFMM451. MM551 20 24 pFMM452. MM552 7.5 11 pFMM455. MM555 7.5 11 pFMM450. MM550 10 13 pFMM451. MM551 5.5 8 pFMM452. MM552 5.5 9 pFMM455. MM555 5.5 9 pFGate to Output Capacitance (CGs) ALL 3.0 5 pFNote 1: The resistance specifications apply for -55°C :s; T A :s; + 85°C, VGG = -20V, VSULK =+10V, and a test current of 1 mAo Leakage current is measured with all pins held at ground exceptthe pin being measured which is biased at -25V.Note 2: All capacitance measurements are made at 0 volts bias at 1 MHz.

typical dynam ic input ch aracteristics (TA = 2SOC Unless Otherwise Noted)CONDITION 1:ANALOG INPUT VOLTAGEAT +10 VOLTSv •• = +10VRon vs VGG10,000== ZETA= 55"C - I----zr=TA =25°Cg,rTA =85°C1000I ~VBB +10V=:,V'N -+10VI..ccz:100"' l~ ~~;;:oSzDynamic Rons:s:~UIo........s:s:UIUIoCONDITION 2:ANALOG INPUT VOLTAGEAT 0 VOLTSV.B+l0V!.s..ccz:10,00010+81000100Ron vs VGG~ VB. - +10V= - f:::V'N OV'-8VGG (V)-16 -22r-TA =85°~=~TA 25°C'b~TA - 55°C..-:::".-0,6 -02 +02 +0,6 +1.0t,v'N (V)Dynamic Ron10 r--~~~-'--'-~~~--'r->I8s:s:~UIN........s:s:UIUIN10o -4 -8 -12 -16 -20-0,6 -02 +02 +0,6 +1.0VGG (V)t,v'n (V)CONDITION 3:ANALOG INPUT VOL TAGEAT -10 VOLTSV •• +10Vw--- -10V OUTT"" r ,100,0001000Ron vs VGGV •• - +10VV1N - 10V100-16 -17TA =85°C ~b=TA =25°C =~+=TA=-55°C=~-18-19--:::!!!!-204Dynamic Ron-9,6 -02 +0,2 +0,6 +1.0VGG (V){, V,N (V)..,j.s..cz:Ron vsVGG10,0001000100~ V •• = OVF V •• = 2,5Vf--- -[ IV •• = 5VV •• =7,5V-r; V •• = 10V...!! ~101o -4 -8 -12 -16 -20VGG (V)-50-45... -40zw -35cz:a:::::> -3~...z -25;;:cz: -200I-15.E -10-50Typical Drain Characteristics_IVG~ = ~15V1 '.J VBS = OV...-8~ F-''/' -13.5 l::::::: i==="~~ F:J ~~I/.,e.~ -=/~ -!-.... i""""'/ -~r- I-'"-61 I-'"7' -4,5-20 -40 -60 -80 -100Vos - DRAIN TO SOURCE VOLTAGE - VOLTS~zwa:...a:::::>z;;:a:0I.E108.0Drain Current vsGate To Source Voltage-J os ! -2~V II-V.s=OV6,0 11/4,02,0/V-1.0 -2,0 -3,0 -4.0 -5,0VGS - GATE TO SOURCE VOL TAGE - VOLTSI143

typical input capacitancesMM450, MM550CIN vs V 1NMM451, MM551C 1N vs V 1NMM452, MM552 , MM455, MM555C 1N vs V 1N50 v •• = +10. 50 v •• = +lOV4030-20... ...10..'"VGG - -20VI I ,..4-;-,.FVGG=-lOV I(...403020VGG = -20V. .....::/,:-V1GG i-liOV I.ez 10oSVGG = OVVGG = OV5~/-4\ ,-VGG - +lOV3I=='I'"'- I- VGG = +lOV-1-10 -6 -2 +2 +6 +10 -10 -6 -2 +2 +6 +10Y'N (V)Y'N (V)....e..'"5040302010543VB. - +lOV-VGG = -20V, \ ,JVGG = 10Vi VGG OV_ ..,.' ../VGG - +lOV1 'J j-10 -6 -2 +2 +6 +10Y'N (V)144

Analog SwitchesMM454/MM554 four-channel commutatorgeneral descriptionThe MM454/MM554 is a four-channel analog commutatorcapable of switching four analog inputchannels sequentially onto an output line. Thedevice is constructed on a single silicon chip usingMaS P Channel enhancement transistors; it containsall the digital circuitry necessary to sequentiallyturn ON the four analog switch transistorspermitting multiplexing of the analog input data.The device features:• High Analog Voltage Handling ±10V• High Com mutating Rate500 kHz• Low Leakage Current (T A = 25°C)(T A = 85°C)• All Channel Blanking input provided• Reset capability provided• Low ON Resistance200 pA50 nA200.12In addition, the MM454/MM554 can easily beapplied where submultiplexing is requ ired since a4:1 clock countdown signal is provided which candrive the clock input of subsequent M M454/M M554units.schematic and connection diagramsANALOGINPUTS4ANALOGOUTPUTCLOCKINPUTCPAQAOUTPUT4:1COUNTOOWNRESET---.... -----------'NO CONNECTION .....:.-----, 14 Voo1--------r-:13- OUTPU14:1 COUNTDOWNCLOCK INPUTRESETFOUR BITCOUNTERANDDECODERI .-_____ -+':!o'_ NO.1 ANALOG INPUTr-___ ~"'"""- NO.2 ANALOG INPUTAll CHANNEL BLANKINGNO.3 ANALOG INPUTNO CONNECTIONNO.4 ANALOG INPUTBULKVss 1L-__ -!._ANAlOG OUTPUTNOTE: Pin 7 connected to case and to device bulk, Nominal Operating Voltages: VGe ~ -24V;Voo ~ OV; Vss = t12V. RESET BIAS = +12V (DV for RESET), All CHANNelBLANKING BIAS" +12V (OV lor BLANKING)145

"litIt)It):?!:?!......."litIt)"lit:?!:?!absolute maximum ratings (Note 1)Gate Voltage (V GG) +10V to -30VBulk Voltage (Vss ) +10VAnalog Input (V IN) +10V to -20VPower Dissipation200mWOperating Temperature MM454-55°C to +125°CMM554-25°C to +70°CStorage Temperature-65°C to +150°Cstatic characteristics (Note 2)PARAMETER CONDITION MIN TYP MAXAnalog Input Voltage ±10ON Resistance VIN=-10V 170 600ON Resistance V IN = Vss 90 200OFF Resistance 10 10Analog I nput Leakage Current MM454 -T A = 25°C .050 100MM454 T A = 85°C .006 1.0MM554 T A = 25°C .0001 100MM554 T A = 70°C .030 1.0Analog Output Leakage Current MM454 T A = 25°c 0.100 100MM454 T A = 85°C 30 1.0MM554 T A = 25°C .0001 100MM554 T A = 70°C .030 1.0Vss Supply Current Drain Vss = +12V 3.8 5.5VGG Supply Current Drain VGG = -24V 2.4 3.5UNITSVnnnnAJJ.AnAJJ.AnAJJ.AnAJJ.AmAmAcapacitance characteristicsPARAMETER CONDITION MIN TYP MAXAnalog Input Capacitance Channel OFF liN = 0 4 6Analog Input Capacitance Channel ON liN = 0 20 24Analog Output Capacitance liN = 0 20 24Clock Input Vel = +12V 2.0Reset Input VRESET = +12V 2.0Blanking Input VBlANK = +12V 2.0UNITpFpFpFpFpFpFclock characteristics (Note 3)PARAMETER CONDITION MIN TYP MAXClock Input (HIGH)(4) Vss - 2 VssClock Input (LOW) -5 0 +5Clock Input Rise Time (POS GOING)No requirementClock Input Fall Time (NEG GOING) 20Countdown Output (POS) V OH Vss -2 VssCountdown Output (NEG) VOL 0Maximum Commutation Rate 0.5 2.0Vss +10.0 +12 +14UNITVVJJ.secVVMHzVNote 1: Maximum ratings are limiting values above which the device may be damaged. All voltagesreferenced to VDD = O.Note 2: These specifications apply over the indicated operating temperature range for V GG = -24V,VOO = OV, VSS = +12V, VRESET = +12V, VSLANK = +12V. ON resistance measured at 1 mA,OFF resistance and leakage measured with all analog inputs and output common. Capacitance measuredat 1 MHz.Note 3: Operating conditions in Note 2 apply. VSS to VOO (OV) voltage is applied to counting andgating circuits. VGG is required only for analog switch biasing. An logic inputs are high resistance andare essentially capacitive.Note 4: Logic input voltage must not be more positive than VSS.146

typical performance characteristicswuzco:I- enC;;wa:~jC>.c,,- : "u c!::~~'"~co:zco:260220180RON vs Analog Voltage1\ I-I"-TA : +85"CVoo: OV -V. ULK : +12VVGG: -24V-Vss : +12V -140i'... ...... i'oo.. _ TA : +25"C l-f-I' j'.. ~ r ......r---.100TA : -55"C'"-t'-1'00.-t- r- r--60-10 -8 -6 -4 -2 0 +2 +4 +6 +8 +10Von ANALOG INPUT VOL TAGE (V)wuZ;:..Uco:co:u~u:.. .e!: z" u ..I-~'" C>...co:zco:30282624222018161412108642oCHANNEL "ON" ....I-" ,....CHANNEL "OFF';';" ~-10 -8 -6 -4 -2 0 +2 +4 +6 +8 +10V;n ANALOG INPUT VOLTAGE (V)~..i.. '" -'>"1413121110Plus VIN (max) vs VBULKvVVVV+9+9 10 11 12 13Von MAXIMUM POSITIVE GOINGANALOG EXCURSION (V)14~>"-30-28-24-20-16-12-8-4oMinus V(N (max) vs VGGVIL4/-- TA : +85°C I/b;0Iloo, W'I.I'JIl~ ~TA:+25"C-!!==:;-TA : -55°C-~~~~~o -2 -4 -6 -8 -10 -12 -14 -16 -18 -20V;n MAXIMUM NEGATIVEANALOG EXCURSION (Ron: 1 KU) (V)timing diagramCLOCK 0IN 1CHI O~: --fI___--In'--__--In...___... n~ ___CH2 O~~--.... n'----.... n n r-L-CH30~: n n n rLCH4 O~: _____..... rl ...___....... n ...___.... rl ..___...... rOUTPUT "0" ~COUNTDOWN "I"--,INOTE: "0" LEVEL: +12V"I" LEVEL: OV (GND)147

enQ)...Q)fJ)oCD-o:I:«oIJ')-o:I:«o~"lit-o:I:«o~M-o:I:«oN-o:I:«AH0120/ AH0130/ AH0140 / AH0150/ AH0160series analog switchesgeneral descriptionThe AH0100 series represents a complete familyof junction FET analog switches. The inherentflexibility of the family allows the designer totailor the device selection to the particular application.Switch configurations available include dualOPST, dual SPST, OPOT, and SPOT. rds(ON) rangesfrom 10 ohms through 100 ohms. The series isavailable in both 14 lead flat pack and 14 leadcavity 01 P. I mportant design features include:• TTLIOTL and RTL compatible logic inputs• Up to 20V p-p analog input signal• rds(ON) less than 10D (AH0140, AH0141,AH0145, AH0146)• Analog signals in excess of 1 MHz• "OFF" power less than 1 mWschematic diagramsDUAL DPST and DUAL SPSTAnalog Switches• Gate to drain bleed resistors eliminated• Fast switching, tON is typically .4l1s, tOFF is1.0 I1S• Operation from standard op amp supply voltages,±15V, available (AH0150/ AH0160 series)• Pin compatible with the popular OG 100 series.The AH0100 series is designed to fulfill a widevariety of analog switching applications includingcommutators, multiplexers, 0/ A converters, sampleand hold circuits, and modulators/demodulators.The AH0100 series is guaranteed over the temperaturerange -55°C to +125°C; whereas, theAH01 OOC series is guaranteed over the temperaturerange -25°C to +85°C.DPDT (diff.} and SPDT (diff.}Note: Dotted line pOltionsare not appliuble to the dualSPST.Note: Doneelline portinns ire not applitable to tbe SPOT (differential).logic and connection diagramsDUAL DPSTDUAL SPSTDPDT (Diff}SPDT (Diff}HIGH LEVEL ('10V)AH0140 (IOn)AH0129 (30n)AH0126 (son)HIGH LEVEL ('10V)AH0141 ClOn)AH0133 (30n)AH0134 (BOn)HIGH LEVEL ('10V)AH0145 (Ion)AH0139 (30n)AH0142 (son)HIGH LEVEL (,10V)AH0146 (Ion)AH0144 (30n)AH0143 (son)MEDIUM LEVEL (±7.5V)AH0153 (15n)AHOl54 (50n)MEDIUM LEVEL (±7.5V)AH0151 (15n)AH0152 (50n)MEDIUM LEVEL (±7.5)AH0163 (15n)AH0164 (50n)MEDIUM LEVEL (±7.5V)AH0161 (15n)AH0162 (50n)148

absolute maximum ratingsHighLevelMediumLevelTotal Supply Voltage (V+ - V-I 36V 34VAnalog Signal Voltage (V+ - V A or V A - V-I 30V 25VPositive Supply Voltage to Reference (V+ - VR) 25V 25VNegative Supply Voltage to Reference (V R - V-I 22V 22VPositive Supply Voltage to Input (V+ - VIN) 25V 25VInput Voltage to Reference (VIN - VR) ±6V ±6VDifferential Input Voltage (VIN - V IN2) ±6V ±6VInput Current, Any Terminal 30mA 30mAPower DissipationSee CurveOperating Temperature Range AH0100 Series _55°C to +125°CStorage Temperature RangeAH0100C Series-25°C to +85°C-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristics for "HIGH LEVEL" Switches (Note 1)PARAMETERLogic "I"Input CurrentLogic "0"Input CurrentPositive Supply CurrentSwitch ONNegative SupplyCurrent Switch ONReference Input(Enablel ON CurrentPositive SupplyCurrent Switch OFFNegative SupplyCurrent Switch OFFReference Input(Enablel OFF CurrentSYMBOLDEVICE TYPEDUAL DUAL OPDT SPOTDPST SPST (DIFFI (DIFFIIINION) All Circuits Note 2IIN(OFF} All Circuits Note 2'+(ON) All Circuits One Driver ON Note 2'-(ON) All Circuits One Driver ON Note 2I FHON ) All Circuits One Driver ON Note 2I+(OFF) All Circuits V'Nl = V'N2 = O.BV'-'OFF) All Circuits V 1N1 = V 1N2 = O.SVIRIOFF} All Circuits V1N1 = V1N2 = O.8VSwitch ON Resistance rds(ON) AH0126 AH0134 AH0142 AH0143Switch ON Resistance rdS(ON) AH0129 AH0133 AH0139 AH0144Switch ON Resistance rds(ON) AH0140 AH0141 AH0145 AH0146Driver leakage Current (10 + IsloN All Circuits Vo = Vs = -10VCONDITIONSv+ = 12.0V, V- = -IS.OV, V R = O.OVTA = 2SoCOver Temp. RanQP.TA = 2SoCOver Temp. RangeTA = 2SoCOver Temp. RangeTA = 2SoCOver Temp. RangeTA = 2SoCOver Temp. RangeTA = 2SoCOver Temp. RangeTA = 25°COver Temp. RangeTA=25°COver Temp. RangeVo = 10V TA = 25°C10= 1 mA Over Temp. RangeVo = 10V TA=25°C10= 1 mA Over Temp. RangeVo = 10V TA = 25°CIF = 1 mA Over Temp. RangeTA = 25°COver Temp. RangeSwitch Leakage IS(OFFIOR AH0126 AHOI34 AH0142 AH0143TA = 25°CVos = ±20VCurrent IO(OFF) AH0129 AH0133 AH0139 AH0144 Over Temp. RangeSwitch Leakage IS(OFFIORTA = 25°CAH0140 AH0141 AH014S AH0146CurrentVos = ±20VIOIOFF) Over Temp. RangeTYPLIMITSMAX2.0 60120.01 .12.02.2 3.03.3-1.0 -1.B-2.0-1.0 -1.4-1.61.0 1025-1.0 -1025-1.0 -10-2545 BO15025 3060B 1020.01 1100O.B 11004 101.0UNITSp.Ap.Ap.Ap.AmAmAmAmAmAmAp.Ap.Ap.Ap.Ap.Ap.AnnnnnnnAnAnAnAnAp.A»J:o.-No»J:o-wo»J:o-~o»J:o-(J'Io»J:o-~oCJ)CD~.CDenSwitch Turn-ON TimetONAH0126 AH0134 AH0142 AH0143 See Test CircuitAH0129 AH0133 AH0139 . AH0144 VA=±10V TA = 25°C0.5 0.8p.sSwitch Turn-ON Time tON AH0140 AH0141 AH0145 AH0146See Test CircuitVA = ±10V TA = 25°CO.B 1.0p.sSwitch Turn-OFF TimetOFFAH0126 AHOI34 AH0142 AH0143 See Test CircuitAH0129 AH0133 AH0139 AH0144 VA = ±10V TA = 25°C0.9 1.6p.sSwitch Turn-OFF Time tOFF AH0140 AH0141 AH0145 AHOI46See Test CircuitVA=±10V TA = 25°C1.1 2.5p.sNote 1: Unless otherwise specified these (imits apply for -55°C to +125°C for the AH0100 seriesand -25°C to +85°C for the AH0100C series. Alt typical values are for T A = 25°C.Note 2: For the DPST and Dual DPST, the ON condition is for VIN = 2.5V; the OFF conditionis for VIN = O.8V. For the differential switches and SW1 and 2 ON, VIN2 = 2.5V, VIN1 = 3.0V.For SW3 and 4 ON, VIN2 = 2.5V, VIN1 = 2.0V.149

...(I)Q)electrical characteristicsen0DEVICE TYPE CONDITIONS LIMITSQ) for "MEDIUM LEVEL" Switches (Note 1)(Q... PARAMETER SYMBOL UNITSDUAL DUAL DUAL SPOT0 V· = +15.0V. V- = -15V. V R = OV TYP MAXOPST SPST OPDT IOIFFI::I:« Logic "1"TA = 25'C 20 60 MAIIN(oN)All CircuitsNote 2Input CurrentOver Temp. Range 120 ~A0 Logic "0" TA=25'C .01 0.1 ~Ait)iIN(OFFI All Circuits Note 2Input CurrentOver Temp. Range 2 ~A...0Positive SupplyTA = 25°C 2.2 3.0 rnAI+(ONI All CircuitsOne Driver ON Note 2Current Switch ON Over Temp. Range 3.3 rnA::I:Negative SupplyT A = 25'C«~1.0 -1.8 rnA'-'ON) All Circuits One Driver ON Note 2Current Switch ON Over Temp. Range 2.0 rnAReference InputT A = 25°C ~1.0 -1.4 rnA0 I AWN)All CircuitsOne Driver ON Note 2(Enable) ON Current Over Temp. Range -1.6 rnA~... Positive Supply T A = 25'C 1.0 10 ~AI+(OFFJ All Circuits V IN1 '" V 1N2 = O.SV0 Current Switch OFFOver Temp. Range 25 MA::I:Negative Supply T A =25°C ~1.0 ~10 ~A'-(OFF) All Circuits V«IN1 = V 1N2 = O.SV---Current Switch OF FOver Temp. Range ~25~AReference InputT A =25°C ~1.0 ~10 ~AV 1N1 '" V 1N2 '" O.8V0IR(oFF)All Circuits(Enable) OFF CurrentOver Temp. Range 25 )1AM... Va = 7.5V TA = 25'C 10 15 r2Switch ON Resistance rds(ON) AH0153 AH0151 AH0163 AH0161 --10 ~--0= 1 mA Over Temp. Range ~::I:Vo=7.5V TA=25'C 45 50 r2Switch ON Resistance rdS(ON) AH0154 AH0152 AH0164 AH016210 = 1 mA ·Over Temp~~ 100 r2«TA=25'C .01 2 nADriver Leakage Current 110 + IsioN All Circuits Va = Vs=-7.5V0Over Temp. Range 500 nAN Switch Leakage 10(OFF) OR TA=25'C 5 10 nA... AH0153 AH0151 AH0163 AH0161 Vos = ±15VCurrent IS(OFF)Over Temp. Range 1.0 MA0Switch Leakage IO(OFF) ORTA = 25'C 1.0 2.0 nA::I: AH0154 AH0152 AH0164 AH0162 Vas = ±15.0VCurrent IS(OFFl Over Temp. Range 200 nA«See Test CircuitSwitch Turn-ON Time tON AHOl53 AH0151 AH0163 AH0161 V A = ±7.5V 0.8 1.0 MSTA = 25°CSee Test CircuitSwitch Turn-ON Time tON AHOl54 AH0152 AH0164 AH0162 V A =±7.5V 0.5 0.8 ~sT A = 25'CSee Test CircuitSwitch Turn-OFF Time tOFF AH0153 AH0151 AH0163 AH0161 VA =±7.5V 1.1 2.5 ~sT A = 25'CSee Test CircuitSwitch Turn-OFF Time tOFF AH0154 AH0152 AH0164 AH0162 VA = ±7.5V 0.9 1.5 ~sTA = 25'CNote 1: Unless otherwise specified, these limits apply for -55°C to +125°C for the AH0100 seriesand -25°C to +85°C for the AHOl DOC series. All typical values are for T A ~ 25°C.Note 2: For the D PST and Dual DPST. the ON condition is for VI N ~ 2.5V; the OFF conditionis for VIN ~ 0.8V. For the differential switches and SWl and 2 ON, VIN2 ~ 2.5V. VINl ~ 3.0V.For SW3 and 4 ON. VIN2 ~ 2.5V. VINl ~ 2.0V.150

typical performance characteristics500zC>~ 400iii 300CI0:~ 200...§wz100100'"~ 10iii0:ZCIPower Dissipationvs Temperature~," ~"25 50 75 100 125TEMPERATURE ('C)rdslONI vs TemperatureAH0150/AH0160 Series-AHOl53, AH0151,=AHol83, AH0161'=-~ AHOI54,AHOI52-AHOTJ1:2.4C 2.0.!~ 1.6w0:~ 1.2'" >it 0.8:::>'"~ OA1000~ 100~j0: 10CI~g~ 1.0ON Supply Currentvs TemperatureI- ~ONII Ir- -'-ION) '-'"-~ION)II-75 -50 -25 0 25 50 75 I DO 125TEMPERATURE ('C)Leakage Current vs TemperatureAH0120. AH0130. & AH0140y+ = 12.0VV- '-I •. OVVD OR V •• ±IOV== AH0140. AHOl41,= AHOl45, AHOl46~ J-..I""" J'V+. +15VV-' -15VVD' 7.5VI •• I mA1.00.10.1-75 -50 -25 0 25 50 75 100 125 25 45 65 85 105 125 25 45 65 85 105 125TEMPERATURE ('C)"EXCEPT AHOI40, AHOI4Ii §AHOl45, AHOI46TEMPERATURE ('C)§w'" ZrdslONI vs TemperatureAH0120 thru AH0140 Seriesiii0: ~ 10 ~~~~~~~~~~f=~~ v D = 10VID • I mAV+ • +12V +--+-+--+-f--lV- • -18V1000coS 100~~~ 10~gQ- 1.0-75 -50 -25 0 25 50 75 100 125TEMPERATURE ('C)Leakage Current vs TemperatureAH0150 & AH0160V+. +15Vv-· -15VVD OR V.' +7.5VFAHOl53, AHOl51,f= AHOl63, AHOl61~io"i--"LAAHOl54, AHOI52,-AHOl64, AHOI62=TEMPERATURE ('C)l>:J:o ...Nol>:J:...owo-,l>:J:o...~ol>:J:o ...CJ1ol>:J:o ...0')oenCD...CDenSingle Ended Switch InputThreshold vs Temperature2.0 I-~d---I-+--+--I-+--iAI'NI - V,N,I;;, 0.3V -if---+--i-;V.' OVv+-V-'30VOL-..I.-....I....-L--J'---'---L...--L--.J-75 -50 -25 0 25 50 75 100 125TEMPERATURE ('C)~ 2.0:lC>:z:'" w0::z:I-! 1.0>0:C>Z,;oDifferential Switch InputThreshold vs TemperatureI I I II I I~ AL~ SWltCHE~ ON'-~ ~ ~...... ~"""'- ALL SWITCHE~ @ ~ ~r- ~-75 -50 -25 25 50 75 100 125TEMPERATURE ('C)switching time test circuitsSingle Ended InputOUTPUTv,,.OUTPUTJ'"L3.0V5Vz.svIDV I II +v" I""I II II----l.~:_I IIDifferential Inputi::r.:---+--.:j:......,J. QUTI'UlOUTPUT'W,., "'W,.,151

enCD''::CDtJ)o...CDoJ:c:(o~in...oJ:c:(o...~'litoJ:c:(oM...~oJ:c:(~oN...oJ:c:(applications information1. INPUT LOGIC COMPATIBILITYA. Voltage ConsiderationsIn general, the AH0100 series is compatible withmost DTL, TTL, and RTL logic families. The ONinputthreshold is determined by the V BE of theinput transistor plus the Vf of the diode in theemitter leg, plus I x R1, plus VR' At roomtemperature and V R = OV, the nominal ON thresholdis: 0.7V+0.7V+0.2V,= 1.6V.Over temperatureand manufacturing tolerances, the threshold maybe as high as 2.5V and as low as 0.8V. The rulesfor proper operation are:V 1N - V R ~ 2.5V All switches ONV 1N - V R S; 0.8V All switches OFFB. Input Current ConsiderationsIIN(oN), the current drawn by the driver withV 1N = 2.5V is typically 20 /lA at 25°C and is guaranteedless than 120 /lA over temperature. DTL,such as the DM930 series can supply 180 /lA atlogic "1" voltages in excess of 2.5V. TTL outputlevels are comparable at 400 /lA. The DTL andTTL can drive the AH0100 series directly. However,at low temperature, DC noise margin in thelogic "1" state is eroded with DTL. A pull·up resistorof 10 kn is recommended when using DTLover military temperature range.If more than one driver is to be driven by a DM930series (6K) gate, an external pull-up resistor shouldbe added. The value is given by:where:11Rp = N _ 1 for N > 2Rp = value of the pull·up resistor in knN = number of drivers.C. Input Slew RateThe slew rate of the logic input must be in excessof 0.3V l/ls in order to assure proper operation ofthe analog switch. DTL, TTL, and RTL outputrise times are far in excess of the minimum slewrate requirements. Discrete logic designs, however,should include consideration of input rise time.2. ENABLE CONTROLThe application of a positive signal at the V Rterminal will open all switches. The V R (ENABLE)signal must be capable of rising to within 0.8V ofV1N(ON) in the OFF state and of sinking IR(oN)milliamps in the ON state (at V1N(ON) - V R >2.5V). The V R terminal can be driven from mostTTL and DTL gates.3. DIFFERENTIAL INPUT CONSIDERATIONSThe differential switch driver is essentially a differentialamplifier. The input requirements for properoperation are:IV1N1 - V 1N2 12: 0.3V2.5 -:; (V1N1 or V 1N2) - V R -:; 5VThe differential driver may be furnished by a QClevel as shown below. The level may be derivedfrom a voltage divider to V+ or' the 5V Vee ofthe DTL logic. In order to assure proper operation,the divider should be "stiff" with respect to IIN2'Bypassing R1 with a 0.1 /IF disc capacitor willprevent degradation of tON and tOF F'Alternatively, the differential driver may be drivenfrom a TTL flip-flop or inverter.Connection of a 1 mA cu rrent source between V Aand V- will allow operation over a ±10V commonmode range. Differential input voltage must be lessthan the 6V breakdown, and input threshold of2.5V and 300mV differential overdrive still prevail.,lOY ICMRANGE+12V152

4. ANALOG VOLTAGE CONSIDERATIONSThe rules for operating the AH0100 series atsupply voltages other than those specified essentiallybreakdowr:l into OFF and ON considerations.The OFF considerations are dictated by the maximumnegative swing of the analog signal and thepinch off of the JFET switch. In the OFF state,the gate of the FET is at V- + VBE + VSAT orabout 1.0V above the V- potential. The maximumVp of the FET switches is 7V. The most negativeanalog voltage, VA. swing which can be accomodatedfor any given supply voltage is:IVAI$IV-I-Vp -VBE - VSAT orIv AI~IV-I-8.0 or IV-I~lv AI+8.0VFor the standard high level switches, VA

TtilQ)'a::Q)enoCD....o:I:«oIt)....o:I:«oq-....o:I:«o('I)....o:I:«oN....o:I:«typical applications (con't){Four Channel Differential Transducer Commutator• ~,;;- 0"1'-:l,TRANSDUCER 0 1 I INO.' 0 • o?"o{.. I a-( I,NO.2 0 2 orl':"--;--7"-+-'---"""'~'"TRANSDUCER I: I,~H;;--~ 1: I,{o TR .. SOU'," 1 : I INO.3 a 6 ~ 5r~:1 I,TRANSDUCER \ I: I 1 INO.4L~ I 1Co,IIIdI1,I1I.1"I I 1 I"+15V~ I ~OM74954-8ITS/R~1I 1"CLOCK4 X 4 Cross Point Analog SwitchGain: 22Commutation R.te: 500 kHzAll CHANNElSLANKINGSwitching Time - BOO ns"ON" ResistllncB - 45n"OFF" RnistlnCl _10'0nDelta Measurement System for Automatic Linear Circuit Tester1.jAH;; - - -"I &---~--------~~---,I.1Iw: 11 IIIIIIt III ..... t.r 50 1'1 min tg .... lrin ,••"" "';I~ IL ~ 50 IlIA. SecondlM4lin. is .. on with S2 closedWiIflSl.IIIIID1htrM1·UpfoRill1functiOfllund'fCDlllpIIltfCOn1l'oI,syll,mwiHm_rttin •• ndl\NII"!lUI.lionDnvon. .... 111011, ,001111 .. i., ,ffHt CUfmlt, eMRR lAd PSAR an op Imps IS "",II a utile. ci",uil$ "quirin, nlllISU, ..m"'t01 t ... c ..... 01. pIf.mrt.twilhthllchln"DI.IDrcin.lullClionLIII I,I-r-.J____ J~-'"~15V +15V1IEOl,ITANlloglnput R.nge - !7.5VEOUT" 10x (Analog Input 2 - Anllog Input 11Error Rate - 0.01% F.S.lsecPrecision Long Time Constant I ntegrator with ResetFour Channel CommutatorI,'I, I"'''~~:~Jlh.';\~*Note: Vos adjusted to zero.L1nL'.,,'.-,.-fr--r,.I ~Integration Internal = 10 seG*Integration Error = 100 j.lVReset Time: 3D j.lS""""",,,0--,..-+0---+ ____Analog Signal Range: 15V p.pSample Rate: 1 MHzAcquisition Time: 25 j.lSDrift Rate: 0.5 mV/sec154

Analog SwitchesAH2114/AH2114C DPST analog switchgeneral descriptionThe AH2114 is a DPST analog switch circuit comprisedof two junction FET switches and theirassociated driver. The AH2114 is designed to fulfilla wide variety of high level analog switching applicationsincluding multiplexers, A to D Converters,integrators, and choppers. Design features include:• Low ON resistance, typically 75n• High OFF resistance, typically 10 11 n• Large output voltage swing, typically ±10V• Powered from standard op-amp supply voltagesof ±15V• Input signals in excess of 1 MHz• Turn-ON and turn-OFF times typically 1 IlsThe AH2114 is guaranteed over the temperaturerange -55°C to +125°C whereas the AH2114C isguaranteed over the temperature range O°C to+85°C.schematic and connection diagra~sG4Metal Can PackageC1CIICUIIII ShO'MlW,th VSl'Ilaglc "'"L-~""""IN\....--II---""--oC2TOPVlfWac test circuit and waveformsYIN2 -15VE,,., Rs = 60011.KYOUTI.Kv ..,..-__,_1SV'11%.'"+ 15V r------1-----4-ov-----VounIIII +9V IVOUT2I-___ ~___,I_.;. ov_'-;----'_ o'V£'NPKFIGURE 1.FIGURE 2.155

absolute maximum ratingsVplus Supply Voltage +25VVminus Supply Voltage -25VVplus-Vminus Differential Voltage40VLogic I nput Voltage25VPower Dissipation (Note 3) 1.36WOperating Temperature RangeAH2114_55°C to +125°CAH2114CO°C to +85°CStorage Temperature Range_65°C to +125°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristics (Notes 1 and 2)AH2114AH2114CPARAMETER CONDITIONS UNITSMIN TYP MAX MIN TYP MAXStatic Drain-Source 10 = 1.0 mA, VGS = OV, TA = 25°C 75 100 75 125 n"On" Resistance 10 = 1.0 mA, VGS = OV 150 160 nDrain-Gate Vos = 20V, VGS = -7V, T A = 25°C 0.2 1.0 0.2 5.0 nALeakage Current 60 60 nAFET Gate-Source IG = 1.01lA 35 35 VBreakdown Voltage Vos = OVDrain-Gate VOG = 20V, Is = 0 4.0 5.0 4.0 5.0 pFCapacitance f = 1.0 MHz, T A = 25°CSource-Gate VOG = 20V, 10 = 0 4.0 5.0 4.0 5.0 pFCapacitance f= 1.0MHz, TA =25°CInput 1 Turn-ON Time V 1N1 = 10V, T A = 25°C 35 60 35 60 ns(See Figure 1)Input 2 Turn-ON Time V 1N2 = 10V, TA = 25°C 1.2 1.5 1.2 1.2 Ils(See Figure 1)Input 1 Turn-OFF Time V 1N1 = 10V, TA = 25°C 0.6 0.75 0.6 0.75 Ils(See Figure 1)Input 2 Turn-OFF Time V 1N2 = 10V, TA = 25°C 50 80 50 80 ns(See Figure 1)DC Voltage Range T A = 25°C ±9.0 ±10.0 ±9.0 ±10.0 V(See Figure 2)AC Voltage Range TA = 25°C ±9.0 ±10.0 ±9.0 ±10.0 V(See Figure 2)Note 1: Unless otherwise specified these specifications apply for pin 12 connected to +15V, pin 2connected to -15V, -55°C to 125°C for the AH2114, and OoC to 85°C for the AH2114C_Note 2: All typical values are for T A = 25°C.Note 3: Derate linearly at 100oC/W above 25°C.156

AM1000,AM1001,AM1002 silicon N-channelhigh speed analog switchgeneral descriptionThe AM 1000 series are junction FET integrated circuitanalog switches. These devices commutatefaster and with less voltage spiking than any otheranalog switch presently available. By comparison,discrete JFET switches require elaborate drive circuitsto obtain reasonable performance for hightoggle rates. Encapsulated in a four pin TO-72package, these units require a minimum of circuitboard area. Switching transients are greatly reducedby a monolithic integrated circuit process. Theresulting analog switch device provides the followingfeatures:• Low ON Resistance• High Analog Signal Frequency30n100 MHzAnalog Switches• High Toggle Rate• Low Leakage Cu rrent• Large Analog Signal Swing• Break Before Make Action4 MHz250pA±15VThe AM 1 000 series of analog switches are particularlysuitable for the following applications:• High Speed Commutators• Multiplexers• Sample and Hold Circuits• Reset Switching• Video Switching»3:~oo»3:~o~»3:~oNschematic diagramequivalent circuitTO-72 PackageANAlOG~O""'OUTPUT 1 4AN~~~~ 1 3VB1ASTOP VIEWtypical applications±10 Volt Swing Analog Switch 0.5% Accuracy±15 Volt Swing Analo.g SwitchANALOG [o---,--o-.,....o--(>'---Q ~~:~g:INPUTSr-- AM100i)ANI~~~~ 2~ ~~~;~:I I I1KCHANNELSELECTINPUTtN914-10VBIAS157

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Analog SwitchesAM3705/ AM3705C 8-channel MOS analog multiplexergeneral descriptionThe AM3705/AM3705C is an eight-channel MOSanalog multiplex switch. TTL compatible logicinputs that require no level shifting or inputpull·up resistors and operation over a wide rangeof supply voltages is obtained by constructing thedevice with low threshold P·channel enhancementMOS technology. To simplify external logic reoquirements, a one·of·eight decoder and an outputenable are included in the device.Important design features include:• TTL/DTL compatible input logic levels• Operation from standard +5V and -15V suppl ies• Wide analog voltage range - ±5V• One·of·eight decoder on chip• Output enable control• Low ON resistance - 150[2• I nput gate protection• Low leakage currents - 0.5 nAThe AM3705/AM3705C is designed as a low costanalog multiplex switch to fulfill a wide variety ofdata acquisition and data distribution applicationsincluding cross·point switching, MUX front endsfor AID converters, process controllers, automatictest gear, programmable power supplies and othermilitary or industrial instrumentation applications.For information on other National analog switches,see listing on page 162.l>s:w.....oUI.......l>s:w.....oUI(")block diagram (MIL·STD-8068)connection diagramIlATA INPUTCHANNEL NO:SLhhhhhhhoOATA OUTPUTDual·ln·Line PackageDE 1 16 22Vss 2 15 21OUT 3 14 2°V,. 4s, ,13 VDDONE·OUT·OF-EIGHT DECODERS,6VooS. 1S. 8g s,2' 22 OUTPUTENABLElOGIC INPUT'"Both Vsslinesare internallyconnected;eithel one orbothmav bellsed.TOP VIEWtruth tableLOGIC INPUTS20 2' 2'L L LH L LL H LH H LL L HH L HL H HH H HX X XDEHHHHHHHHLCHANNELONS,S,S,S,S,S,S,SaOFFtypical applicationsBuffered a·Channel Multiplex, Sample and HoldWide Input Range Analog SwitchINPUTS"""'1",ANALOGOUTPUTINPUTS"""'1_ANAlOGOUTPUTCHANNELSHECTITTl)A".I.~S'9 .. IR.ou. W~~,i~~;;~"_T~~'m-V~~'A"","""T.m.-250m159

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typical performance characteristics300250200C[-;; 150oa:10050oON Resistance vs AnalogInput Voltage~UTLL1' ....Voo = -20V__ Vss=+7VTA =+25°ClouT = -100 pAI I I ITEST POINT-I'--r--!- 10--l-t--5 -3 -1 0 +1 +3 +5 +)INPUT (V)400350300_ 250~-;; 200oa: 15010050oON Resistance vsAmbient TemperatureVoo = -20VVss = +7VIOUT=-100pAIl'~/'jTiSi POINTSV'NPUT = -5V... i-' r110- Ii-' V'::UT = +7VInlli-'-75 -5~ -25 0 25 50 75 100 125TEMPERATURE (OC)2.0200C[-;; 150£100ON Resistance vs VODSupply Voltage~ TA = 25°CVss = +5V~ louT = -100 pA"- '\ I I.~ 1........r-...VOUT = -5.0V-:--.... ..:--.~ ::t-- .::--......._ VOUT - +5.0V _~':1 J VOUT=O.OV- -50.i .J.I I-10 -15 -20 -25Voo SUPPL V (V)Output Leakage Current vsAmbient Temperatureswitching time test circuit10·E VOUT - Vss - 15V~TES~-----S:/'G~OSV""~ .INPUT""V10'o 25 50 75 100 125TEMPERATURE (OC)typical applications (con't.)Differential Input MUX16-Channel Commutatora-Channel Demultiplexer with Sample and HoldA~ALOGINPUT" lDOmAOUTPUT.. ,'SmAOUTPUT161

schematic diagramanalog switch data sheetsFor specifications on other National analogswitches and analog interface circuits, see thefollowing data sheets:MOS Analog SwitchesDual Differential - MM450/MM550Triple - MM455/MM555Quad - MM452/MM552Four Channel - MM4511MM551Four Channel with Commutator - MM454/MM554Six Channel - AM2009/AM2009CTTL/OTl Compatible MOSDPDT - AH0014/AH0014CQuad SPST - AH0015/AH0015CDPST - AH0019/AH0019CTTlIOTl Compatible J-FETDual OPST )Dual SPST (Dual DPOT (DiffJ ( AH0100/AH0100C SeriesSPDT (Diffl )High Level Compatible J·FETDPST - AH2114/AH2114CUltra High Speed J-FET±10V; 30n - AM1000±15V; 50n - AM100l±10V; lOOn -. AM1002N-Channel Discrete J·FET Switches5 Ohm - 2N54327 Ohm - 2N543310 Ohm - 2N5434ANALOG SWITCH DRIVERSTTL Dual Level Translator - DM7BOO/OM8800TTL Dual High Speed Translator DH0034/DH0034CAnalog Comparator/Level Translator - LM111SeriesSAMPLE AND HOLD CIRCUITSLow Drift Precision - LH0023/LH0023CHigh Speed - LH0043/LHOD43CPlus a complete line of amplifiers comparatorsand. voltage regulators.162

NH0014/NH0014C OPDTNH0019/NH0019C(MH453 / MH553) dual DPSTOTL/TTL compatible MOS analog switchesgeneral descriptionThis series of DTUTTL compatible MOS analogswitches feature high speed with internal levelshifting and driving. The package contains twomonolithic integrated circuit chips: the MOSanalog chip is similar to the MM450 type whichconsists of four MOS analog switch transistorsconnected in dual differential configuration; thesecond chip is a bipolar I.C. gate and level shifter.The devices feature:• Large Analog Voltage Switching ±10VAnalog Switches• Low ON Resistance 200n• High OFF Resistance 10 11 n• Fully compatible with DTL or TTL logic• Includes gating and level shiftingThe devices, packaged in hermetic 14 lead flat anddual-in-line packages, are suitable for many airbornecommunication and analog signal switchingapplications.Z:I:o""'" ~........Z:I:o~ ""'"(")Z:I:oU) ""'"........Z:I:o""'" U)(")schematic and connection diagramsNH0014NH0019'« ----1~---1>------------------,Flat PackageOUTPUT INPUT INPUT INPUT INPUT OUTPUTI 81 AI ,1,2 82 2 V~lu'Flat PackageOUTPUT INPUT INPUTDVm,"", 2 A2 B2A B Vee N.C GND N.C. V",,"u,NOTE: All ;npllt~ "HIGH"B GND Vp'.' OU11'UT INPUT INPUT1 AI BlNOTE: All input$ "HIGH"Dual-In-Line PackageDual-In-Line Package, lVO'"' 4ANALOG ounUT zANALOG INPUT Al 6ANALOG INPUT Bl J '-____ ~NOTE: AII,npu,,"HIGH"163

(.)0')....ooJ:Z........0')....ooJ:Z.(.)oq-....ooJ:Z........oq-....ooJ:Zabsolute maximum ratingsVee Supply Voltage 7.0VVminus Supply Voltage -30VVplus Supply Voltage +30VVplusNminus Voltage Differential40VLogic Input Voltage 5.5VStorage Temperature Range_65°C to +150°COperating Temperature Range NH0014, NHOO19 -55°C to +125°CNH0014C, NHOO19C DoC to +70°CLead Temperature (Soldering, 10 sec) 300°Celectrical ch aracteristics (Note 1)PARAMETER CONDITIONS MINLogical "1" Input Voltage Vee = 4.5V 2.0Logical "0" Input Voltage Vee = 4.5VLogical "1" Input Current Vee = 5.5V V 1N = 2.4VLogical "1" Input Current Vee = 5.5V V 1N = 5.5VTYP(Note 3)Logical "0" Input Current Vee = 5.5V V 1N = O.4V 0.2Power Supply Current Logical" 1" input Vee = 5.5V V 1N = 4.5V 0.85NH0019, NH0019C-each gate (Note 2)Power Supply Current Logical "0" input Vee = 5.5V V 1N = OV 0.22NH0019, NH0019C-each gate (Note 2)Power Supply Current Logical" 1" input Vee = 5.5V V 1N = 4.5V 0.85NH0014, NH0014C (Note 2)Power Supply Current Logical "0" input Vee = 5.5V V 1N = OV 1.5NH0014, NH0014C (Note 2)Analog Switch ON Resistance V 1N (Analog) = +10V 75(each gate) V 1N (Analog) = -10V 200Analog Switch OFF ResistancelOllAnalog Switch Input Leakage Current V 1N = -10V T A = 25°C 0.05NH0014C, NHOO19C (Note 4) T A = 70°C 4NH0014, NHOO19 V 1N = -10V TA = 25°C 25(Note 4) TA = 125°C 25Analog Switch Output Leakage Current VOUT = -10V TA = 25°C 0.1NH0014C, NHOO19C (Note 4) TA = 70°C 30NH0014, NHOO19 VOUT=-10V TA = 25°C 40(Note 4) T A = 125°C 40Analog Input (Drain) Capacitance 1 MHz @ Zero Bias 8Output Source Capacitance 1 MHz @ Zero Bias 11Output Transition Time for TA = 25°C 200Logical "0" InputOutput Transition Time for TA = 25°CLogical "1" Input NH0019, NHOO19C 100NH0014, NHOO14C 250MAXUNITSV0.8 V5 J..LA1 mA0.4 mA1.6 mA0.41 mA1.6 mA3.0 mA200 Q600 QQ10 nA50 nA200 pA200 nA10 nA100 nA400 pA400 nA10 pF13 pFnsnsnsNote 1: Min/max limits apply across the guaranteed temperature range of -55°C to +125°C forNH0014, NH0019 and oOe to 70°C for NH0014C, NH0019C. Vminus = -20V, Vpl us = +10V and ananalog test current of 1 mA unless otherwise specified.Note 2: Current measured is drawn from Vce supply.Note 3: All typical values are measured at TA = 25°C with VCC = 5.0V. Vpl us = +1 OV, Vminus = -22Vunless otherwise noted.Note 4: All analog switch pins except measurement pin are tied to V plus.164

analog switch performance characteristics (Note 3)CONDITION 1 AT +10VDYNAMIC RON10 10,000864cc2RON vs Vminusv. 'u • = +10V III V. 'u • = +lOVY,N =+10V j ') Y'N = +10VVOUT =+10VIII';r 1000JVE...!A.. ~ Vminus= - OV TAI/! ~ ~VminU5 = -tOVFY'N Your .! 0~~+10VI...-'+10V~ ~z ",.. TA =+25 D C-2 0~ ~= +B5 D C..4 100"ION -6 TA =-55 CV' '-- Vminus = -5V-8CONDITION 2 AT OV 4V VlI'-10 10-1.0 -0.6 -0.2 +0.2 +0.6 +1.0 0 -5 -10 -15 -20 -25"V'N (V)DYNAMIC RONRON vs VminusVminus (V)10 10,000V p1us = +10V81/ V V p1us = +lDVY'N = OViV VlN =ov I6Your = OV~ 1/IP.: V t 1000cc 2...TA =+25~D C0 z TA=-55Dc=f=~ ...,.., 0..~ .....-2~ [§t-Vminus = -12V ~ ...::100TA =+85D C-4~ r?;-- Vminus = -16VVIN VOUT .!~OVI...-'0V"I~ WON -6-81 ~r- ~Vminus = -22V-10 10-1.0 -0.6 -0.2 +0.2 +0.6 +1.0 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -262:I:o-~......2:I:o-~o2:I:o-CD......2:I:o-CDoL'.V,N(V)Vminus (V)DYNAMIC RONRON vs Vminus10 100,000Vp1us = +lDV8 Vp1us = +lDVY'N = -10V 1= 1=6r-t-- Y,N - -10VYour = -10VCONDITION 3 AT -10V 4I ..... 10,000...cc 2 .,.l~ f:": tVIN VOUT .! I-0 !~-,- --;;.. 10--- Vm,nus = -lBV---10VI...-' -10V""z-2 0.. 1000 ~ TA = +B5 D C-4 I- -Vminus = -19V---~~ II; FHA =+25D CON -6--- l- I"""" Vminus = -20V - =-8 ~ I-- .- Vminus = -2tV - - - - Vmlnus = -22V - _. -TA = _55 D C 1--10 100--1.0 -0.6 -0.2 +0.2 +0.6 +1.0 -19 -20 -21 -22 -23 -24 -25 -26"V'N (V)Vminus (V)50CIN vs VIN Leakage vs VIN (Channel "OFF" RON vs Temperature75 I"" 500V p1us - +lDV V. 'u , = +10VCHANNEL "ON" - CHANNEL '~ON"- cc20 Vminus = -20V - Vminut = OV50 i' V mlnu,-NO EFFECT _V p1us = +10V~I 400 I- Vminus = -Z2V0!!-...~ ... r-...25c '" ...... ...u 3002.r cr-...zU 100 c....In ~'"r-... ..... ...:: -....in 200r-... ...c 5 -25 Y'N = -10Vz..z,~. I!. Cit.Y'N = OV~CHAN~EL "OFF"'" uP 1002~':;NEl "ON"-50Y'N = ""'" 10VVminus = -lOV Vminus = -ZOV1 -75 01-10 -8 -6 ..4 -2 0 +2 +4 +6 +8 +10 +10 0 -10 -55 -15 25 65 105 145ANALOG Y'N (V) ANALOG Y,N (V) AMBIENT TEMPERATURE eC)165

(.)0')-ooJ:Z........0')-ooJ:Z(.)"d'-ooJ:Z........"d'-ooJ:Zselecting power supply voltageThe graph shows the boundary conditions whichmust be used for proper operation of the unit .The range of operation for power supply Vminusis shown on the X axis. It must be between -25Vand -8V. The allowable range for power supplyV plus is governed by supply Vminus. With avalue chosen for Vminus' V plus may be selectedas any value along a vertical line passing throughthe Vminus value and terminated by the boundariesof the operating region. A voltage differencebetween power supplies of at least 5V should bemaintained for adequate signal swing.level shifter characteristics~w;:. '"-Io>w>a:c+10 r---~r--'--r-""-"-Vc-c-=-:5"".oV:-:--1+5 1---+---11---1+-1--1Vminus = -22VV. 'U, = lo.oV'" -10 r---t---tt---tt-t--t-+--+--lo:;;;;;! -15 I---+---It---tt-t--t-+--+--l2a:~ -20 r-----t--lF:::~ .. - ..... ~!!:-25 '---'-_'---'---'_-'--.1.---1o 0.5 1.0 1.5 2.0 2.5 3.0 3.5INPUT VOL TAGE (V)~ v+-::1510OPERATING 5v- ~ 0-25 -15 -5 -5-10-15-20-25166

MM480/MM580 series MOS logic elementsgeneral descriptionNational's line of monolithic MOS gates and flipflopsare built utilizing P channel enhancementmode transistors. Zener diodes are used on all inputsto protect against static discharge. Thesedevices are members of a family of compatiblelogic functions that feature low threshold voltagetransistors, enabling operation at a V DD supply of-10 volts and low power consumption in systemsschematic and connection diagrams10-Voo----_-------,13KOUT 1--...... -+--,13K,--i--_-OUT'GNO-t-..... + ...... -+-+-t--I---t-...J., B1 C1 A2 ., C2Note: All rlllirtOf YlIUH shown If. DomiRiI-VOGGNOTOP VIEWNOTE: Pin 5 eonlllded to e ..MM480{MM580 dual 3-input NOR gateLogic Elementsthat operate at frequencies up to 2 MHz.The JK flip-flops are particularly suited for counterand register applications in MOS systems. Bothtrue and complement outputs are buffered to preventfalse triggering from the outputs and also providethe capability to "wire AND" at the outputs.10-VOD-'--_--_----p-----,OUT1--~GND .!·+I--4 ........ -+-........ I--HH--4--

absolute maximum ratingsSupply Voltage (Vo o ) +O.5V to -25VData Inputs +O.5V to -25VOperating Temperature (MM480, MM481, MM482, MM483) -55°C to +125°C(MM580, MM581, MM582, MM583) - 25°C to +70°CStorage Temperature-65°C to +150°Celectrical characteristics (Note 1)Output VoltagePARAMETER CONDITIONS MIN TYP MAX UNITSLogic "0" V,N = -7.0V for Logic "1" -0.2 -1.0 VLogic "1" V'N = -1.5V for Logic "0" -8.0 -10.0 VInput Leakage V,N = -11.0V

typical performance characteristicsMM480/MM580Voltage Transfer Characteristic-101 I'. ~ -55°C-en -8 _.+25. o C ~,...Q2-... -6....f--..C[....Q>....:::l.......:::lQ-4-2o oI-_+125°C f'\',l'l1........ +125°C-55°C ~ ~+25°C .~-1 -2 -3 -4INPUT VOLTAGE (VOLTS)3028! 26;; 24...... 222018-5375- 350gzoa: 300...:;:...c 250....:::l~:::lQ175Propagation Delay vs TemperatureJ IT '7PD/I~ Tp~2~ i// VV ~i,...-' ".".. '"-I--""-50 -25 0 25 50 75 100125TEMPERATURE (OC)-Output Device RON vs Temperature, I' ...- !375 :::350 o-!"325300275,/ "1/~If;/j5:.URON-50 -25 0 25 50 75 100 125TEMPERATURE rC)-1.0 ,en-.9.......Q -.82-... -.7..C[....... -.6Q>-.5~u -.4~c... -.3-.2140! 130~ 120..: 110cis 100!:i 90..: 80c~ 7060Average Propagation Delay vs PowerSupply Voltage (VDD) (See Figure 1), ,~\\.'" ~...... .....-6 -8 -10-12-14-16-18-20Vee (VOLTS)Logic "0" Voltage vs Wire ANDConnections (See Figure 4)V ~/ ~+125°Cj K25°C~V/ VV. ~Vo 2 3NUM8ER OF WIRE AND CONNECTIONSMM481/MM581-10en-8 .......Q2-... -6C[........:::l.......:::l-2cVoltage Transfer Characteristicsf-:125~C!..;.. It.V ~r---55°CVr-+25°C1Ir- Va = -10.0Vc> -4i rL I II !' I '!.'2~oCI ~ ,• -55°CII I 1I IIIVa =ov1 I' 1 III I1 1I- +125~CI ~ I-1 -2 -3 -4INPUT VOLTAGE (VOLTS)..,../~125I°c-5e~1.1...uZ~ 1.0... en~ .9c....:::l~ .8:::lQ.7Output ON Resistance vs Temperature.,-10.0V 1 1 ItD=fV)IfII"V/1If-50 -25 0 +25 50 75 100 125TEMPERATURE (OC)!;: 240C[..: 220Qis 200!:i 180~ 160......~'40~ 120C[ffi 100>C[Average Propagation Delay vsPower Supply Voltage (VDD)(See Figure 2)\\I\.~"-.......... ""-6 -8 -10 -12 -14 -16 -18 -20Vee (VOLTS)160140100Propagation Delay vs Temperature~ 10""" ~JI' ~" 10""""TJI' ~ t"0~I/ ~Tp02,V /V,540520 en ......500...Q2-480 w420 f'u~400 Q...3801.61.41.2C[460 ! ....1.0Q440 j>.8.6.4Logic "0" vsWire AND Connectors (See Figure 5)~ ,~~V+125°C / V....~ ,/'+25°C·50 ·25 0 +25 50 75 100 125TEMPERATURE (OC)2NUMBER OF WIRE AND CONNECTIONS169

MM482/MM582Voltage Transfer Characteristics-10INPUT IS A. C = O.OV.~OR B. C = -10.0V... -80-55°C~...'" co: -6....0>.......:::>....-4:::>0-2 +125°C .......+25°C ho.-'-55°Co -1 -2 -3 -4 -5INPUT VOLTAGE (VOLTS)600~ 550zo~ 500...:> ...~ 450:::>........:::>o 400350Output Device RON vs TemperatureI/''/jV1/1/~-50 -25 0 +25 50 75 100125TEMPERATURE (OC)!>:3...CIz0;:co:... '" c0II:...w'" cII:...300275250225200175> 150cAverage Propagation Delay vsPower Supply Voltage VDD(See Figure 3), ,\.,I'-~I"'~-6 -8 -10-12-14-16-18Voo (VOLTS)-"Logic "0" Output Voltage vsPropagation Delay vs Temperature Wire AND Connection (See Figure 6)450400Ipo~.J ~ l..".o'\PO,.. I' ~...... "'"I~~ i.I'~I' V~V'-50 -25 0 25 50 75 100125TEMPERATURE (0 C)en ....0280 ;;:; -1.4'" co:~ -1.2o;: -1.0:::>~ -.8:::>o300 !=> -.6~ -.4o... -.2~VV ~.V~ V'I--f----+125° Vl/:25°CVV450~T.d2"""";, i""'" /IL350~ ~ ~ Tpd1, ~l..!o' I' "1NUMBER OF WIRE AND CONNECTIONS~ r/~-50 -25 0 25 50 75 100 125TEMPERATURE f'e)700~650 -:S600550170

propagation delaytest circuits (gates)MM480/MM580MM481/MM581MM482/MM5821 VOUT~"'fV .. (C"~' :~.--:1:....- VOUTYIN IC=-10VI .---~ _r_'OIlFMM480/MM580,MM481/MM581,MM482/MM582IVv,.ov---1OV ___ ---"MM480/MM580-VDD,o-O -r--r --r--r------.FIGURE 1. Ring Oscillator for MeasuringAverage Propagation OelayMM481/MM581-VDD 0-0 ~, ___,__ ~, __ ~, __---.~ ~ ~ ~ -IOV ltransient response test circuitsMM483/MM583E,.SEl OR CLEAR-IIVovOORD-lOY1-.... --0I--",--D-11V~1.IVovE,. JAU- ' ~., TI-IIV". TFovOORD ~ -IV -IV-lOY -IV -IVOyCP-lOYOy----I\,.OORD-lOYT,"NDTz

ROM Character GeneratorsMM4220N P/MM5220NP, MM4230NN/MM5230NN,MM4230NO/MM5230NO, 7x9 horizontal scandisplay character generatorgeneral descriptionThe MM4220NP/MM5220NP is a 1024-bit read-onlymemory and the MM4230NN/MM5230NN andMM4230NO/MM5230NO are 2048-bit read-onlymemories programmed to generate a font of 647x9 dot-type raster or horizontal-scan characters.The typical application shows the ASCII-addresssystem. The display refresh memory, built withMOS dynamic shift registers, and the TTL controltypical application7x9 Character Generator Systemtechniques are similar to those described in ApplicationNote AN-40. Designs for vertical·scan fonts,printer character generators, and designs for fontslarger than 7x9 are also outlined in AN-40.For full electrical, environmental and mechanicaldetails, refer to the M M 4 2 2 0 / M M 5220 andMM4230/MM5230 data sheets.3:3:~NNoZ."........3:3:(11NNoZ.."3:3:~NCo\)oz........3:3:(11NCo\)oz3:3:~NCo\)ozo........3:3:(11NCo\)oZo-r. •MM5230NN I. I• • •MM5230 NO I •.:MM5220 -----La NP•-r+ ...173

zo(W)Nan~::E........zo(W)N'-=t~:Ec..ZoNNan~~........c..zoNN'-=t~:Echaracter font....(::i.l" ,." ..r···=:I····'·1100001032000001:f· .. ·•..... 1..000011.......··-1,.....1I :"•_...e.. .......n100010! -.1100001 ".:i• 1...1000111":,i· ..·:.1......0100011 "............I :1i···.110'0110. .: IJ4DIOGOI......•• :1..J:: .. :50010011....I .:....-110000 "........-:.:..·1 •• ••110010 "35110001.::::~-:...::110011 "·1····II: I.1.••-..0"""··r·0010111".··1··.... -··1··::..001001 ".·-1.I···i·:52001011.......I •....: ....:05101000.. )21101(110. .......:~:.101001 "53101011Note: Input .ddrtmes .,e in six bit ASCII code and lIt shown in the SiHIUtlll:8 Ag. AI'" As.·1····.:i···:011000 "i. II ••..1011 " OlD.......: .:...!-:011001 ".......:1'• :....::.I.···.:.. I·····:......541111011.....: . I .....:1 ...::10711100II: ..:·.......· .23111010..111001 "..:111011 "I :I :08000100....:..:. .:0lI0110 "..I ..40000101..I I(::::56000111.....I :•• 1 ••10111011 "100110 ".:..:100101 "::...::.. ...:;:!100111 "...... I10010100.. .........::.....010110 "... ::: ...: .010101 "..: ..01!1111 "I ...:'1I ••: ..11110100rI ..21110110..·1· ...,110101.:59110111:L ...001100 ". .....28001110..1101101.........011111 ". .is :!I···'13101100•• j..:101111 "..10""101111 "i. II· •I ...:. .1111011 ",.811110..011101........011111"...:. .:I. ....I1111Q11 "·t=31111110.......1111" "..... .......111111 "174

ROM Character GeneratorsMM4240ABU/MM5240ABU hollerith character generatorgeneral descriptionThe MM4240ABU/MM5240ABU is a 64 x 8 x 5read-only memory programmed to display a 64-character subset of the Hollerith 12-line code,normally used in punching 80 column cards_ Compressionfrom 12 lines to the six needed to makeup a 64-character set may be accomplished asshown in the typical application_For electrical, environmental and mechanical details,refer to the MM4240/MM 5240 data sheet.typical applicationow1211gI-- A.B,vee -SERIALDATATHOLLERITHCODE0---0->-.d)-..N>-LINEANDPAGESTOREISH AN40lI-- A.I-- A,I-- A,I-- A,I-- A,MM424QABU/MM5240ABUB,B,l, l, l,I I IL---B..-------B •IA ~ 6.8K;-~DMB590-12V Vee C]CKLINECOUNTER12 A~. A411 Aso A.9 A3 " AoB A,No,oHolep'.,enIQ",",elosureloGNO·For ad'hllonal appllCiitlOn Information on mcorilllratmg th,s device in it display system, see AN40"A Systems Approach til Character Generators"175

:::>!XI

ROM Character GeneratorsMM4240ABZ/MM5240ABZ EBCDIC-8 character generatorgeneral descriptionThe MM4240ABZ!MM5240ABZ is a 64 x 8 x 5read only memory that has been programmed todisplay the 64 character graphic subset of EBCDIC-8, an Extended Binary Coded Decimal InterchangeCode with character assignments and locations conformingto the American Standard x 3.26-1970(see MM52300X data sheet for full EBCDIC-8table).Compression of the eight bits of EBCDIC-8 to thesix needed for a 64-character subset is accomcharacterfont••• •••••••• :...• ••••• ••••• ••••:• ...:• •••• •••• ••• • • • • • • • :.... ....••• • •••• ••• •••• • :00 01 02 03 04 05 06 07DOD 000 000001 000010 000011 DOD 100 000101 000 110 DOD 111••• ••• •• •• ••••• • ••••• • • • • • • •• 10 • ••• 11 ••• 12 •• 13 14•15 • 16 • 17001 000 001 001 001 010 001 011 001 100 001 101 0[]1110 001 111• •• • •• •• •• • •••••• ••••• : ..: : •••• ••• • •••••••• ••••• • •• •••••• • • • • ••••••• •20 21 22 23 24 25 26 27010000 (]10001 010010 01[]O11 []10 100 010101 010 110 010111••• •••• ••• •••• •• •• ••• • •• • ••••• ••• •••• •• •• • •••• • •• •• •• •••• • • • ••• • • ••30 31 32 33 34 35 36 37(]11 000 011 001 011 010 all 011 011 100 011 101 011 110 011 111• ••••• ••••• • •••••• •• • • •• • •• • • • • •• ••• • •• ••• • ••• • • • • •40 41 42 43 44 45 46 47lOll 000 100001 100 010 100011 100 100 100 101 100 110 100111• • •••••• •• • •• ••••• • •• • • • ••••• • •• • •••••50 51 • 52 • 53 • 54•• ••••• •56 • 57101 000 101 001 101 010 101 (]11 101 10055101 101101110 101 111•• •• • ••• • ••• •• • •••• ••• •••••• • •••• • ••••• •• • :.... • • • • • • ••••• • • • • •••• ••• ••••• ••• • ••• ••• •60 61 62 63 64 65 66 67110000 110001 110010 110011 110100 110101 110 110 110111... •• • • • ••••• ••• •••• ••• ••••• •• • •••• •••• ••••• • •• • ..... • • •• • • • •• • • •••••70 71 72 73 74 75 76 J7111 000 111 001 111 010 111011 111 100 111 101 111 110 111111plished by simply ignoring the two most significantEBCDIC bits, bit 0 and bit 1.The octal character address digits are then formedas shown below.For electrical, environmental and mechanical details,refer to the MM4240!MM5240 data sheet.EBCDIC BITS~MSB 234 567 LSB'-/ '-/MSD 1 2 LSD"-../DCTAL DIGITSOUTPUTSB, B2 B3 B4 B5000001.010 •• ROW all.• ADDRESS 100.101.••110. 111. •177

ROM Character GeneratorsMM4240ACA/MM5240ACA EBCDIC character generatorgeneral descriptionThe MM4240ACA/MM5240ACA is a 64 x 8 x 5read only memory that has been programmed todisplay the 64 character graphic subset of EBCDIC,an Extended Binary Coded Decimal Interchangecode typically used in I BM systems.plished by simply ignoring the two most significantEBCDIC bits, bit zero and bit one.The octal character address digits are then formedas shown below.For electrical, environmental and mechanical details,refer to the MM4240/MM5240 data sheet.Compression of the eight bits of EBCDIC to thesix needed for a 64-character subset is accomcharacterfont•. e.: ....:....:....:....• •••••• •:...:••••00 • 01 • •••• • • • ••••• •••02 ••• •03•••••:•.... ••••:04 05 06.... • ••:07000 000 000001 000010 000011 000 100 000101 001] 110 000111••• ••••••:•••:••• 10 • .1. • ••••• :•••• :: •• • •••••11 12 13 • • !14 • • :15 16 17001 000 001 001 001 OlD 001 011 001 100 001 101 001 110 001 111•••••• •: • ••: • ••.. •:•• ••• • •• ••20• •••••••••• : ..:••••••••••••: : :• ....•21 • 22 • :....:• :••: :•:• ...:•23 24 25 26 • 27010000 010001 010010 010011 010 100 010 101 010110 010111•••••••:.::-:- • •: •••••• • • • ••••••• ••30 31 32 •••••-:-. ••••• •••••• • •• ••: •••:: •• •••• •33 34 35 36 3J011 000 011 001 011 010 lilt 011 011 100 011 101 011 110 011 111• •••••••• •••• • ••••• ••• ••• •• •• 40 • 41•••••! I :.:•• •42 43 • ••• • ••44 45 • •••• •46 • 47 •100000 100001 100010 100011 100100 100 101 100110 100111• ••••••••••••..:•..•• •••50 • ..... • ••••••o •• •• ••• •••••• •51 52 • 53 •54 •• ••••••• • 56 • 57101 DOD 101 001 101 010 101 011 101 10055101 110 101 111101 101••.:•••••••• • .: :....• •••• •• • •• •60••• • • ••••••• •••• ••••••••• •••••• •••••61 62 63 64 • •••••••••••••••65•••66 • 67110000 110 001 110010 110011 110100 110101 110110 110111•••••••••• • ••••• •••••••••••••• ••••70 •• 71•• • •••• •• •:••••• •• ••72 • 73 • ••••••74 •••111 000 111 001 111 010 111 011 111 10075111 10176111 11077111111EBCDIC BITS~MSB 234 567'-/ "'-./MSD 1 2"-/OCTAL DIGITSLSBLSD, OUTPUTS8, B2 8 3 B, 8 5000001. •010.. •ROW 011 •••ADDRESS 100. • •101. •110. •111. •178

ROM Code Convertersrn"owSK0003 sine/cosine look-up table kitgeneral descriptionThe SK0003 Sine/Cosine Look-Up Table Kit consistsoffour MaS ROMs: three MM4210/MM5210'sand one MM4220/MM5220-1024 bit static readonly memories. They are P-channel enhancementmode monolithic MaS integrated circuits utilizinga low threshold technology.THE SINE FUNCTIONThe SK0003 implements the equation sinO = sinM cos L + cos M sin L. Cos L was assumed to be1 in the equation. However, it is a variable between1 and 0.99998 and is a function of round off error.Worst case error is 1-5/8 bits in LSB at address1415 (62.25°). The error increases from zero to.002% every 8 bits, therefore, the MM4220/MM5220 provides the error correction factorcos(M - 2.81°)sin L in the equation sinO = sinM +cos(M - 2.81°)sin L. The circuitry to perform thisfunction is shown in Figure 1. Additional informationis available in MOS Brief 10.THE COSINE FUNCTIONTo generate the cosine function cosO = sin (0 -90°), the input must be complemented and alogical "1" added. Figure 2A is a logic diagramof the circuitry used to provide the cosine function,as well as providing both sine and cosinefunctions in the same system. 11-bit resolutionand 12-bit accuracy ±1-5/8-bits is achieved in thisconfiguration.A reduction in logic can be achieved as shown inFigure 2B if a loss in resolution of 1/2-bit in an11-bit input or 1/4-bit in a 10-bit input is acceptable.ELECTRICAL CHARACTERISTICSRefer to the appropriate data sheet for eachdevice shown in the figures. The devices noted are:MM4210/MM5210, MM4220/MM5220, DM5483/DM7483, DM7812/DM8812 and DM5486/DM7486.logic diagramGATES~)--.--{{A.I.A~ MM5210 8JMKOOII,B,I..·" B, "z'A, Z.. " ..• AI 0117413,I.'. , ,-,.," .. •11" I,CARRY INPUT.,.. CARRYOUTPUT,. .."i·'OM'''' '. ,.,IINARY"CARRY INPUTz·,v~{ .. B.{~A,MMS210B,MKOO9 ~A,B,CARRYOUTPUTD.fCl3CARRYI.PUT",.,"Z·11R~ (TO EACH OUTI'UT)-12VFIGURE 1. SK0003 Logic Diagram (Kit Includes ROMs Only). This Circuit Provides 11-Bit Resolution and 12-BitAccuracy in a 0 to Sin 0 Converter.179

(II)o~ologic diagram+1ZYr',-SKOOO3ROMSA.DOUTPUTADDERSr',-,-,,-,2-'..2,102,11SINE/COSINEENABLE 0--4 ..... ----+--1SIGNAL"0" ~ Sine"'''=CosinlA,CARRY...__....... 1.2,12FIGURE 2A. Sine/Cosine Conversion Provides 11-Bit Resolution, 12-Bit ± 1-5/8 Bit Accuracy.+12VlSBJSINE!COSINESIGNAL"0"= Sine"'''=CosineJ'+12VJ.J',,-,z-',-,J' ,-,,-,ID11SKDOO3ROMSANDOUTPUTADDERS",-,""2,102,112,'2FIGURE 2B. Sine/Cosine Conversion with Cosine Approximated. (Cosine Conversion has 10-Bits Input Resolutionand 12-Bit ±1-5/8-Bit Accuracy.)180

ROM Code Converte rsMM4220AE/MM5220AE ASCII-7 to hollerith code converter3:3:~NNo»m.......3:3:U'INNo»mgeneral descriptionThe MM4220AE/MM5220AE 1024-bit read-onlymemory has been programmed to convert the128 entries of the American Standard Code forInformation Interchange in seven bits (ASCII-7) toHollerith code (compressed to eight bits). Theconversion performed follows the .recommendationof American National Standard ANSI x 3.26-1970, Hollerith punched card code.The typical application shows a recommendedcircuit for re-expansion of the Hollerith code totwelve lines.For electrical, environmental and mechanical details,refer to the MM4220/MM5220 data sheet.typical applicationASCII·}INPUTS~---'l-----------------------------OM8810 ~8rOM8812_I~_~~ __.-~A~'r.'-"~·~~I1~111" ..!.....j________--1rb,..b,lDti~ LeVI.OTLmL!eIlCI!ItIlMOS/ROMilllelllee)Lillie "1",+IiV,NOM,Llllic"lI"llound,NOMMOSlAOMinpllb.ndautpuU""',r r-IO ~'r""----I________--'r- ......»-----t-""""""'t Ae 20 rMt'!522DAE a 1"""----1----------'UKTYPICAL ~-1UNES" "A, • B,v..B,.. 2V-------~ .....-...:ft,~, ~.!,!-~j. ~B'~-----------J1111111-t~~4,LOIIic ",",mol1lnep1ive,logic"O", mOllplllitive·CH",ENABLEPUNCHROW,.--------------------"OM1442, 0,0__, '0--'.0--',0--,,0__'' 0--'.. j,'-------·..J0-- ,'5 1& l HOLLERITH PUNCH COMMANDS.1ZV (ACTIVE LEVEL: lOW-PUNCH)I·ChipElllble'" logic "1" to abllin DUIpUUFAN OUT AVAILABLE1 TTl lOAD1FAN OUT AVAILABLEIOTTLLOAOS181

w«oNNin::E::E.......w«oNNqo::E::Ecode conversion tablesb,'" 0.. 0NUL0000 12-0-9-8-1SCH0001 12-9-1STX0010 12-9-2ETX0011 12-9-3ECT0100 9-7ENO0101 0-9-8-5ACK0110 0-9-6-6BEL0111 0-9-8-7BS1000 11-9-6HT1001 12-9-5IF1010 10 0-9-5VTlOll 11 12-9-8-3FF"00 12 12-9-8-4CR1101 13 12-9-8-5SO1"0 14 12-9-8-6511111 15 12-9-8-7FSooOLESf'12-11-9-8-1 NQPCH 0DCI '425"28293.313233"19moo 0.1.1 00 142ROWADD_OUT,,"UT eOOEFlESS 97 86 85 84 83 82 81..43 0 0 0 I 1 1 I 0,..50" 525354565758,ft616365616.70111213"161118.. ", ;82 ".38485ROW"00_""'681..••90".3"1--"4 0125126121OUTPUT eOOEB7 a6 85 84 83 82 ·81ROW· 9 0 11 12 B182

ROM Code ConvertersMM4220AP/MM5220APBCDIC-to-ASCII code convertergeneral descriptionThe MM4220AP/MM5220AP is used for the conversionof the Binary Coded Decimal InterchangeCode(BCDIC) to the American Standard Code forInformation Interchange (ASCII).The input is a seven-bit BCDIC code with theexception of the parity (check) bit (pin 18) whichis returned to +12V dc. The alternate set of inputsymbols is also shown in the Conversion Table forreference.The output is a seven-bit ASCII code, with aneighth bit generated for even parity.device characteristicsFor full electrical, environmental, and mechanicaldetails, refer to the MM4220/MM5220 1024-bitread only memory data sheet.typical applicationconnection diagram-1ZV----------------+~._...,~V--~-------~~---~~~~-~._---~ .8!;~ 8C(NOT USED)A,A,A,A,"A,20A, "A7 183.0K,TYPICAL,JLlNESV"+12V-----4I...-....... ~ 1ZtAo24VDO·CHIPENABLE---....MM4220AP/1'IM5220APtMODE CONTROl------'VGG17B,S B,B,B.7I I,• B.B,10B.11UK,TYPICAL,a LINESGATES DM7400DTL/TTL lOGIC"V __A, N.C.A, N.C,B, A,.. A,B, ..B. A,a. 17 VGGa.,. MODE.. 11CONTROLa, ,. CHIPENAILEV"..12 N.C.TO' VIEWlogic LevelsDTl/TTL (except at MOS/ROM interface)Lup: "1", +5V, nam. LOIic "11", .. au., nOIl1.MOS/ROM Inputs & OutputLogic",",morenaptive.lDlic"O",m .. pDlitivetModl Cuntrol = Logil:"O"Aa=Logit"t"-Chip Enable ~ Lotic "I" to Dbtlin olltputs183

code conversion tableFUNCTIONCODEINPUT OUTPUT INPUT OUTPUTC0ROM SCOIC ASCII DSCOICEASCIIADDRESS SYMBOL SYMBOL E" • • , A 2 P·2 .,SPICI Space• 1 · · 1 12 2 2 1• • · 1 1 1 1 • •1 1• • 1 1 ·1•· 15 5 1•·· · · · · · 1 1 1 1 16 6 6 1 1 1 1 1 1•7 7 7 • • • • 1 1 1 1 1 1 1 1 18 8 8• • · · • ·1 • ·1 1 1 1 1111 #or m #• • ·1 1, 1•·· · 1 • • • 1 •1113 • •· •1 1 1 1 1 1> > 1 1 1,. • 1 1 1 1 1 1,f 7 • ·1 1 1 1• • 1 1 1 1 1 116 Blaok I• · 1 1 117 I I 1 1 1•,. · • 1 1 1 1 118 S S• • • 1 1 1 1T T 1• • 1 1 1 1 1 12.• ·· · ·U U 1 1 1 1 1 121 V V• ·1•· 1 1• • • --.1 1 1 122 W W 1 1 1• · 1 1 1 1 123 X X• •· , · 1 1 1 1 1 1 1 Y Y 1 12.•2 2 · · , 1 1 1•· -.1 1 128 LF• •· · •1 1 1 127• 1 1 1 1 1 1• ,128 %or(2. 1v HT · • • 1 1 1 1 03. , • ·1 1 1 1• • ·131 .. • • · 1 132 - - • · ·1 1• 1 1 133 J J• • · 1 13' K K 1 • ·1 13' L L 1 1, 1 1• ·1 138 M M 1 1 1 -.37 N N 1• •· • , ·1 1 1 1 138 0 0• · 1 1 1• • · 1 1 1 1 1,.. 3. P P 1• •· , 1 1 1 1• • • •·Q Q 1 1., R" • 1 1• •· 1 1 1 1• • , ·.2 ,· ·I 1 1 143• • 1 1• • •· • 1 1 1 1 4.· 1 1 1 1 1•45 I I · 1 1, • ·· 1 1 1 1 146 , , · · 1 1 1 1 1 1, 1•· 1.7 I• • 1 1 1 1 1 1 1 1 1 1• 148 80 or t• 1• • ·1 1 1 4. A A • 1 1 15. 8 8• • • • • 1 1 1 1., •·· ··· 1C C 1 1 1 1 1 1 1 1.2·0 0 1 1 · 1 1• • 1 53 E E , 1 •· 1 1 1 1 1 164 F F •· 1 1 1 1 1, • ·1 155 0 0•· 1 1 1 1 1 1 • ,.. 1 1 H • · •1 57 I I• • • • · 1 1 1 1 1 1 1• • 11 ,· ·· 1 1•· 1 1,1 1 ~6. Ilor)• , 1 1, •1 1., • •1 1 1 1I ( 1 1 , 1• • · 1 1 1• 62 <

ROM Code ConvertersMM4220BL/MM5220BL baudot-to-ASCII code convertergeneral descriptionThe MM4220BL/MM5220BL is used for conversionof the Communications Set Baudot code to theAmerican Standard Code for Information Interchange(ASCII).The Baudot and ASCII codes have different formats.ASCII has a unique code combination foreach alphabetic, numerical, or control character.The correct interpretation of a five bit Baudot isdependent upon knowing its previous history;whether upper or lower case was last selected, Ineffect a sixth-bit, which can be called the Case Bit,is required to uniquely identify the Baudot input.The latch circuit shown in the typical applicationcan store this information and will generate theCase Bit. If the bit is externally supplied, thefeedback and latch circuits can be deleted (asshown with the X's),The accompanying table is applicable for the codeconversion scheme as shown (or its alternate)rather than for the device itself. The input andoutput codes are defined at the TTL gates with thelogic trues high (Logic "1" = +5 volts, nominal;Logic "0" = Ground, nominal).device characteristicsFor full electrical, environmental, and mechanicaldetails, refer to the MM4220/MM5220 1024-bitread only memory data sheet.typical applicationBaudot to ASCII,INPUT GATE sAREDM881BAUDDTINPUTSBITSBIT4BIT3BIl2BIT I+12Vdc~ALl3.DKIOPTIONAL SIXTH BITFj!I.!!.~~I:!"!!'!.E~E----===:IGATES:OM8IIOOSERIESL.[:'t.12VtIc,. A, 3 12 l1B'V.--'-

code conversion tablesconnection diagramFUNCTIONINPUT OUTPUT 'NPUTCBAUDOTROM BAUDOT ASCII•ADDRESS SVMBOL SYMBOL E, •3•Blank.. ", 0,.020,. " D D 00 0 23 0 , 0 ," · 0W W J 0 , Upper ISllC. ... 0 ," 2. U U , ,00,O-'a" 0 ,BI .... k ,NULL 0·0 0CR CR 030• • ,-.034 S.~ 0 a ,."SIS as/FE a a aa 0 ,0 a ,LF LF , a., , , a 0 a.2·• aa0, ,0 ,, , a 0 a,.. ", , a a., , a 0 ,· · , , a, a , a.2 Bo" Bo", " a0 0 , ,, 0 a., , 0 a..58 Upper C~ a ,50.,7 7 , , aa.2 , , ,• E • .CODEOUTPUT..ASCII·20 0 0 0, 0, .. .. ..0 , 0, 0 00 0 00' 0 0 , 0 , ,, , 0 ,0 0 , 0 00 ,0,, , 0 0 0 0 0 f ,0 , , 0 , 00 0 0 000 0 ,0 0 ,0 0 ,a,0 0, 0 0 0a 0 a , 0 a, , , ,a 0 0 0 a, a ,0 0 a, 0 , 0,a 0,,, a , 0a a a ,, 0 0 0 ,0 , , , a0 , 0, , , , ,0 0 ,, 0 ,0 , ,0,0 00 0 , ,,0 00 0, 000000 0,00a ,, a a 0 , 0 00 ,,00 0 , ,00 0 0 ,, a 00 ,,,0 0 , 0, 0 , , a 0,0 a 0 ,, ,0 0, ,, 00 ,, ,a 0, ,0 a.,, 0 0 , , 0,0 0 ,, , 0 00 , ,0 ,00 0 0 , ,0 ,, 0 ,0 0 00, ,0 , 0 , ,0 0 0 0 ,, 00 0 ,, 0 ,00 0 0 ,0 0 ,000,0,000a,a,,a,A3- ,AZ- ZA'- 31'- 415- •IT- '018- "'-----_IZ-14-16-Z3r­ZZI-17 ~VQG'61-~g~:"OL'5 r-~:~BLE'4 r-AB......V .._ 12 131-TOP VIEWEP' Ev .... P .. itv IS1 - Info.",,,i(lnseparalor"'1LF-LineFII&d SIS ~ Siop/Sta.!CA· Carriae- flaturn 8S - 8.,;:k Sp..,.Can· Cancel186

ROM Code ConvertersMM4220BM/MM5220BM sine look-up tablegeneral descriptionThe MM4220BM/MM5220BM is a 1024-monolithicMaS read only memory that has beenprogrammed to solve for the sine value x of aknown angle 8; i.e., to obtain the solution of theequation x = sin 8.Values of 8 are defined in the look up table for0° ~ 8 < 90° (quadrant I) which has correspondingsolutions of 0 ~ x < 1. For values of90° < 8 < 180° (quadrant II), enter the complement(180° - 8) to obtain the correct solution.Solutions for quadrants III and I V differ in signwith I and II. This is summarized in Table 1.This input is divided into 128 parts for 8 in eachquadrant. Thus, the appropriate input address is(8 1 /90°)(128) to the nearest whole integer. Theactual input code to the ROM is the input addressexpressed in binary, with A1 being the mostsignificant bit.The output is the value of X expressed in binary.The output lines B 1 , B2 , ..... B8 are binary placevalues 1/2, 1/4, ...... 1/256. The sign for negativevalues of X is externally generated.The 8 bit output code has been rounded off froma larger word code, i.e., where Ag was a binary"1" it carried into the LSB of the eight bit code,where Ag was a binary "0" it was simply dropped.EXAMPLEFind the sine of 45~The input address is (45/90) 128 = 64 or1000000, as expressed in binary. The convertergenerates the output .10110101 whose decimalequivalent is 0.707131. Thus, sin 45° = 0.707.Find the sine of 210~This value is in quadrant III; therefore 8 1 = 210° -180° = 30°. The input address is then (30/90)128 == 43 to the nearest whole integer. The binaryinput to the ROM is then 0101011. The outputvalue is .10000001 or 0.503906. Thus, sin 210° =-0.504, with the sign generated by the externallogic. The solution is within 1 %; note that address43 is actually equal to 30.23°.device characteristicsFor full electrical, environmental and mechanicaldetails refer to the MM4220/MM5220 1024-bit readonly memory data sheet.typical application-I1V----__________ .-..... --,VooA,24 VooA, B,6.BI

pattern selection form",'", '" '"'1--' "a'"g,'50'"" ",'"~,,,,,,154, ,,,"16.17 ,,,r-------;";'"'"-~ ----;-~:~: '"'",eo1--- '""'"'"f---%::--- _._ 27,42 ",SO,f--::-_._'JJ,7~515'60","" 550'"'"41.48-------c"-- '---,iH:- -~ ," '"Baa, a,f--'-.a5 B, a, a, a,.. ,"""a_. 5062""""""'"'"'"CODEaa B, B, B5 B, B, B, B,,-+-f-i-49.92 ,51,3352,0354,8455,55m'"'"'"1.00658.36 \,0195906'.043\,0551.06861.67 1.08062.5850 1.1041.117"1,1541.16667.5068.2066.9169611.227W, 1.239'" 72.4273.12'"''"'"'"'"'"77.34'"78 0578.7579,45'"80.86 ,'" -~81.56 ,on f12.2782.9784.3885,08'"'" 152288,5989.301534~-P,= --'-i-connection diagramTable 1. SINEA,- ,B,- 524 _Voo23 _ N.C.22 - N.C.20 -AsQuadrantIIIIIIVINPUTOUTPUTRange Entry to ROM (0' ) Binary Value Sign::,. 0 0 < 90 0 Direct Direct Reading +> 90' < 180' 180 0 - X Direct Reading> 180' < 270' X - 180 0 Direct Reading> 270 0

ROM Code ConvertersMM4220BN/MM5220BN arctangent look-up tablegeneral descriptionThe MM4220BN/MM5220BN is a 1024-bit monolithicMaS read only memory that has been programmedto solve for the angle () whose tangentvalue x is known; i.e., to obtain the solution to theequation: () = arctan x.Values of x are defined in the Look Up table foro < x < 1 with angles corresponding from0°;; () < 45°. For values x :::: 1, the reciprocal of x(i.e., 1/x) must be entered and the output anglemust be complemented to obtain the actual value.The input is divided into 128 equal parts for x.Thus, the appropriate input address is (128)(x) tothe nearest whole integer for obtaining the appropriateROM address. The input code is the ROMaddress expressed in binary with Al being the leastsignificant bit. For input values greater than unity,the decimal reciprocal is to be taken prior to entryof the binary address.The output has been normalized for 45°. To obtainthe true angular reading, the output should bemultiplied by 45°, i.e.: () = (()output) x 45° where()output is the decimal equivalent of the output.The output code is the normalized value of theangle () expressed in binary. The output lines B 1 ,B 2 , •••• B8 are binary place values 1/2, 1/4, ....1/256. To obtain angles between 45° and 89.6°which occur when input values of x are equal to orgreater than unity, either complement the outputbinary code and add a 1, or complement theresultant angular value (i.e., subtract from 90°).The 8-bit output code has been rounded off. Thatis, if another bit of even lower significance hadbeen computed for the given arctangent value wasa bi nary" 1", it wou Id have carried over into theLSB of the eight bit code. If it was a binary "0", itwould have been dropped.EXAMPLEFind the angle whose tangent is 0.258.The input address is 128 x 0.258, or 33 to thenearest integer. Expressed in binary, this is0100001, and is the actual input code to theconverter. The converter will generate the binaryvalue .01010010, whose decimal equivalent is0.3203125.Thus, () = 0.320 x 45° = 14.4°device characteristicsFor full electrical, environmental and mechanicaldetails refer to the MM4220/MM5220 1024-bitread only memory data sheet.typical application-12v-----__________.....__4........,"v--...------------+-~+-__4......--""""""l.OK,TYPICAL,7 LINESA, VGG17A,A,A,21A,20A,"B,B,B,B,MM4220BN/ 7M~522DBNB,, B,lOj..:B:!,., ___ -1--1t12V ____ ~...._ .... --V~ss 12 l1~B;:",' ___ +-1UK,TYPICAL,B LINESGATES DM7400b,b,b,b...~,b,b.JtA,"CHIP ENABLE ___...JDTLITTllDGICtMODE CDNTROl----....Jlogic levelsDTL/TTL (ucept at MOS/ROM interface)logk: "1", +!iV, nom. logic "0", ground, nom.MOS/ROM Inputs & OutputLogic"l",mo,e negative. logic "O",more pnsitivetMudeControl = Logic "0"As= Logic "1""Chip Enable = logic "'" to obtain outputs189

zmoNNan::?!::?!........zmoNN"It::?!::?!pattern selection formo 00000000101000000210100000311100000.4 01010000500110000(,11110000701001000001010009 1 1 Tal 0 0 0101001100011 0011100012 0 1 1 1 1 0 0 013 1000010014 1100010010110010016 0 0 0 1 0 1 0 017 1 1 0 1 0 1 0 018 1 0 1 1 0 1 0 019 0 0 0 0 1 1 0 020 0 1 () 0 1 1 a 021 1 0 1 0 1 1 0 I .0.22 , 'iJ--'"iJL~~~~~~:~~25 1 1 1 1 1 1 0 0210000010'17 00100010?II 01100010290001001030 1 1 0 1 0 0 , 031 1 0 1 1 0 0 , 032 0 0 0 0 1 0 , 033 0 1 0 0 1 0 1 0340010101035 1 1 1 0 1 0 , 036100110103 1 1 0 1 lOt 038 0 1 1 1 1 0 1 0390000011040010001101 1 0 1 0 0 1 1 042 1 1 1 0 0 1 1 0OUTPUT CODE 10 OUTPUT)1281,) 88 97 96 85 84 83 82 8143 1 0 0 1 a 1 1 a44 0 a 1 1 0 1 1 045 0 1 1 1 a 1 1 04 0000111041 0 1 0 1 1 1 048 1 a 1 0 1 1 1 049 1 1 1 0 1 1 1 050 1 0 0 1 1 1 1 051 1 1 0 1 1 1 1 052 0 1 1 1 1 1 1 0530000000154 0100000155 001000015601100001570001000158 010100019 1 0 1 1 0 0 0 1o 1 1 1 1 0 a 0 T61 1 0 0 0 1 0 0 12 T 1 0 0 1 0 0 163101010014 1 1 1 0 1 0 0 15 1 0 0 1 1 0 0 1i6 1 1 0 1 1 0 0 17 1 0 1 1 1 0 0 161'- 1 lit 1 0 0 191000010170 1 1 a a 0 1 0 171 1 0 1 0 0 1 a 172 1110010173 1 0 0 1 0 1 0 11 1 0 1 0 1 0 11 0 1 1 0 1 0 176 0 1 1 1 0 1 0 177 0000110178 0 1 0 0 1 1 0 1790010110180 0 1 1 0 1 1 0 181 0 0 0 1 1 1 0 182 1 0 0 1 1 1 0 183 1 1 0 1 1 1 0 184 1 0 1 1 1 1 0 185 1 1 1 1 1 1 0 18890 """10010''02103104'0610710'09110111112113114'15'16117'18'19120121122123124'2512,1270100001100100011o t 1 0 0 0 j 11 1 1 0 0 0 1 11 0 0 1 0 0 1 11 1 0 1 0 0 1 1lOt 1 0 0 1 1o , 1 1 0 0 1 1000010111 0 0 0 1 0 I 11 1 0 0 1 0 1 11 0 1 a 1 0 1 1a 1 1 0 1 0 1 1o 0 0 1 1 0 1 11 0 0 1 1 0 1 11 1 0 1 1 0 1 11 0 1 1 1 0 1 1a 1 1 1 lOT 1000001111 0 0 0 0 1 1 11 1 0 0 0 1 1 1o 0 1 0 0 1 1 1o 1 1 0 0 1 1 11 1 1 0 0 1 1 11 0 0 1 0 1 1 1o 1 0 1 0 1 1 11 1 0 1 0 1 1 11 0 1 1 0 1 1 1o 1 1 1 0 1 1 1o 0 0 0 1 1 1 11 0 0 0 1 1 1 11 1 0 0 1 1 1 1o 0 1 0 1 1 1 11 0 1 0 1 1 1 11 1 1 0 1 1 1 1o 0 0 1 1 1 1 11 0 0 1 1 1 1 11 1 0 1 1 1 1 1o a 1 1 1 1 1 11 0 1 1 1 1 1 1o Til 1 1 1 1connection diagramA,_ ,A,- ,24 t-- VeeA,_ 38,- 420 -As19 - ..8._18s- 8B,- 9B,_ 1017 - Vaa16 -~g::ROl15 -~~:BLE88- 1114 -A8V"-L'_' _______TOP VIEW".J-190

MM4220DF/MM5220DF"quick brown fox" generatorgeneral descriptionThe MM4220DF/MM5220DF is designed forexercisingand rapid testing of ASCII and Baudotcodedkeyboards, typing mechanisms, and datacommunications links by generating the internationallyaccepted "Quick Brown Fox" messafje.ROM Code Convertersalong with an even parity bit for a binary countinput of 64 to 127.device characteristicss:s:~NNoC.""'-s:s:U'INNoC."The input is a 7-bit binary sequential count. Theoutput of a 6 stage up-counter can be used; aseventh bit selects the desired code. The messageis generated in the 5-bit Baudot CommunicationsSet code with a binary count input of 0 to 63. Themessage is generated in the 7-bit American StandardCode for Information Interchange (ASCII)The message generator is fully contained on amonolithic MOS integrated circuit chip utilizinglow threshold voltage technology for increasedDTL/TTL compatibil ity. For complete electrical,environmental, and mechanical details, refer to theMM4220/MM5220 1024-bit read only memorydata sheet.typical applicationsconnection diagram-12V-----------------... - .... -.INPUT GATESDMBB12 ORDM8Bl0A,24voF11VooA, 24 VooA,B,A, 2JCLOCKSOURCEA,B,A, 12A.B,B, A.B, 20 A,A,A,20 MM4220DF/MM5220DF1B.B,B, 19 A,B. A,A,B,B, 11 Voo10K,TYPICALJUNESB,B_B, ID ISMODECONTROLB.B. A.'A.'CHIP ENABLE ___ --IANY DlllTTL LOGICV"TOPVlfWtMOOECDNTROL-----Jlog.eLevelsOTlfTTl !exceplal MOSIROM mteriace)LogIc ",",+5V, nom. Loglt"O". lI'oond,nomMOS/RDM Inputs & Oulputsl09'c 'T',molenegat.ve.LoQ.c"O",moreposlllveOutpulSfo,c"cu,t$hll\NnBaudot: LOIIC "0"· "punch"ASCII Logltlnve,slontModeCuntrol-log,t"O'As=LotlC "'"'Ch,p Enable = lDtIc ""'Ioobll,n outputsA typical application showing the ASCII'coded testmessage as received at a computer terminal.THE QUICK BR0WN F'0X JUMPS eVER THE LAZY DOGTHE QUICK BR0WN F'ex JUMPS 0VER THE LAZY DOGTHE QU ICK BR0wN F' ex JUMPS eVER THE LAZY DOGTHE QU lCK 8R0WN Fex JUMPS eVER THE LAZY DOGTHE QUICK BR0WN F0X JUMPS eVER THE LAZY DOGTHE QU ICK 8K0WN F0X JU,"'.PS 0VER THE LAZY DOGTHE QUICK BR0\o1N Fex JUMPS 0VER THE LAZY DOGTHE QUICK BR0WN Fex JUMPS eVER THE LAZY DOGTHE QUICK BR0WN Fex JUMPS eVER THE LAZY DOGTHE QUICK BR0WN F 0X JUMPS 0VER THE LAZY DOGTHE QU ICK BR0WN F 0X JUMPS t:lVER THE LAZY DOGTHE QUICK BfH;lWN Fex JUMPS eVER THE LAZY DOG1234567890 DE1234567890 DE1234567890 DEi 234561 890 DE1234567890 DE1234561890 DE1234561890 DE1234561890 DE1234567890 DE1234561890 DE1234561890 DE1234567890 DE191

LLCoNNit):E:E........LLCoNNq-:E:Ecode conversion tableOUTPUT CODEOUTPUTBaudotADDRESS CHARACTER - - - 5, 3 21 1 1 1 0 1 ,,10 CR1 CR 1 1 1 1 0 1 1 12 LF 1 1 1 1 1 1 0 13 Ln 1 1 1 0 0 0 0 04 T 1 1 1 0 1 1 1 15 H 1 1 1 0 1 0 1 16 E 1 1 1 1 1 1 1 07 SP 1 1 1 1 1 0 1 18 0 1 1 1 0 1 0 0 09 U 1 1 1 1 1 0 0 010 I 1 1 1 1 1 0 0 111 C 1 1 1 1 0 0 0 112 K 1 1 1 1 0 0 0 013 SP 1 1 1 1 1 0 1 1ADDRESS6465666768697071n7374757677OUTPUT CODEOUTPUTPARITASClICHARACTER y b, b6 b5 b, b3 b2 b,NULL 0 0 0 0 0 0 0 0CR 0 1 1 1 0 0 1 0CR 0 1 1 1 0 0 1 0LF 1 1 1 1 0 1 0 1T 0 0 1 0 1 0 1 1H 1 0 1 1 0 1 1 1E 0 0 1 1 1 0 1 0SP 0 1 0 1 1 1 1 10 0 0 1 0 1 1 1 0U 1 0 1 0 1 0 1 0I 0 0 1 1 0 1 1 0C 0 0 1 1 1 1 0 0K 1 0 1 1 0 1 0 0SP 0 1 0 1 1 1 1 114 8 1 1 1 0 0 1 1 0788 1 0 1 1 1 1 0 115 R 1 1 1 1 0 1 0 179R 0 0 1 0 1 1 0 116 0 1 1 1 0 0 1 1 117 W 1 1 1 0 1 1 0 018 N 1 1 1 1 0 0 1 119 SP 1 1 1 1 1 0 1 120 F 1 I 1 1 0 0 1 08081.,83840 0 0 1 1 0 0 0 0W 0 0 1 0 1 0 0 0N 1 0 1 1 0 0 0 1SP 0 1 0 1 1 1 1 1F 0 0 1 1 1 0 0 121 0 1 1 1 0 0 1 1 1850 0 0 1 1 0 0 0 022 X 1 1 1 0 0 0 1 086X 0 0 1 0 0 1 1 123 SP 1 1 1 1 1 0 1 187SP 0 1 0 1 1 1 1 124 J 1 1 1 1 0 1 0 088J 0 0 1 1 0 1 0 125 U 1 1 1 1 1 0 0 089U 1 0 1 0 1 0 1 026 M 1 1 1 0 0 0 1 190M 1 0 1 1 0 0 1 027 P 1 1 1 0 1 0 0 191P 1 0 1 0 1 1 1 128 S 1 1 1 1 1 0 1 092S 1 0 1 0 1 1 0 029 SP 1 1 1 1 1 0 1 193SP 0 1 0 1 1 1 1 130 0 1 1 1 0 0 1 1 1940 0 0 1 1 0 0 0 031 V 1 1 1 0 0 0 0 195V 1 0 1 0 1 0 0 132 E 1 1 1 1 1 1 1 096E 0 0 1 1 1 0 1 033 A 1 1 1 1 0 1 0 197R 0 0 1 0 1 1 0 134 SP 1 1 1 1 1 0 1 198SP 0 1 0 1 1 1 1 135 T 1 1 1 0 1 1 1 199T 0 0 1 0 1 0 1 136 H 1 1 1 0 1 0 1 1100H 1 0 1 1 0 1 1 137 E 1 1 1 1 1 1 1 0101E 0 0 1 1 1 0 1 038 SP 1 1 1 1 1 0 1 1102SP 0 1 0 1 1 1 1 139 L 1 1 1 0 1 1 0 1103L 0 0 1 1 0 0 1 140 A 1 1 1 1 1 1 0 0104A 1 0 1 1 1 1 1 041 Z 1 1 1 0 1 1 1 042 Y 1 1 1 0 1 0 1 0105106Z 1 0 1 0 0 1 0 1Y 1 0 1 0 0 1 1 043 SP 1 1 1 1 1 0 1 1107SP 0 1 0 1 1 1 1 144 0 1 1 1 1 0 1 1 01080 1 0 1 1 1 0 1 145 0 1 1 1 0 0 1 1 146 G 1 1 1 0 0 1 0 147 SP 1 1 1 1 1 0 1 11091101110 0 0 1 1 0 0 0 0G 1 0 1 1 1 0 0 0SP 0 1 0 1 1 1 1 148 F,g 1 1 1 0 0 1 0 01121 0 1 0 0 1 1 1 049 1 1 1 1 0 1 0 0 01132 0 1 0 0 1 1 0 150 2 1 1 1 0 1 1 0 01143 1 1 0 0 1 1 0 051 3 1 1 1 1 1 1 1 052 4 1 ., 1 1 0 1 0 153 5 1 1 1 0 1 1 1 154 6 1 1 1 0 1 0 1 01151161171184 0 1 0 0 1 0 1 15 1 1 0 0 1 0 1 06 1 1 0 0 1 0 0 17 0 1 0 0 1 0 0 055 7 1 1 1 1 1 0 0 056 8 1 1 1 1 1 0 0 157 9 1 1 1 0 0 1 1 158 0 1 1 1 0 1 0 0 159 SP 1 1 1 1 1 0 1 11191201211221238 0 1 0 0 0 1 1 19 1 1 0 0 0 1 1 00 1 1 0 0 1 1 1 15P 0 1 0 1 1 1 1 10 1 0 1 1 1 0 1 160 U, 1 1 1 0 0 0 0 0124E 0 0 1 1 1 0 1 061 0 1 1 1 1 0 1 1 062 E 1 1 1 1 1 1 1 063 SP 1 1 1 1 1 0 1 1125126127SP 0 1 0 1 1 1 1 1OEC 0 0 0 0 0 0 0 0OEC 0 0 0 0 0 0 0 0B8 B'B6 B5 B4 B3 B2 B1B8 B1 B6 B5 8' B3 82 8'Baudot: Logic "0" '" "punch"ASCII" LogiC inversionSPSpdceNOTEWHEN CHIP ENABLE INPUT IS AT A LOGICAL O. ALLOUTPUTS ARE AT A LOGICAL 1192

ROM Code ConvertersMM4220EK/MM5220EKBCDIC-to-EBCDIC and ASCII-to-EBCDIC code converters3:3:~NNom~.......3:3:U'1NNom~general descriptionTheMM4220EK/MM5220EK isa 1024-bitread onlymemory that has been programmed to convertboth Binary Coded Decimal Interchange Code(BCDIC) and the American Standard Code forInformation I nterchange (ASCII) to Extended BinaryCoded Decimal Interchange Code (EBCDIC).The BCDIC-to-EBCDIC converter is located in thefirst 64 8-bit bytes of the ROM. The unused paritycheck bit (the most significant input BCDIC bit) isalways a "0".The ASCII-to-EBCDIC converter is located in thesecond 64 8-bit bytes of the ROM. Thus, the inputASCII code in addresses 64 through 127 has a "1"in the most significant (A7) bit which is used withthe selection logic. The resulting 6-bit ASCII inputis for display-only upper case and numericalcodes, since it will not accept the control commandsor the lower case characters.device characteristicsFor full electrical, environmental and mechanicaldetails, refer to the MM4220/MM5220 1024-bitread only memory data sheet.typical applicationconnection diagram-12V----------------+~t_....,b, 1b, 1.5V--+--------------I--II-4---_--A,8,6.8K,TYPICAL,B LINESGATES OM740(}A, 14 V,,A, 13A, 11b, 4A,8,8, 11 A,b, Sb, Ab, 8"CODE"A,11A,10'" "A, 18MM4220EK/MM52Z0EK8,s,s,, S,~8, 10 A,8,8, 18 A,8, 17V""8, 16A,MODECONTROLl.OK,TYPICAL,1UNESV"+12V-----.~t--"""I12tA,"CHIP ENABLE ___..J10 j.:8::.-, ------11---1111"8;;..' ---~t--IOlL/TTL LOGIC8, 10 158, 11 14 A,V" 12 13TOP VIEWCHIPENABLEtMOOE CONTROL ------'Logic LeulsDTlfTTl (except at MQS/ROM Interface)logic "l",+!iV, nom. Logic "Q",glound, nom.MOS/ROM Inputs & OutputlogIc "l",more neptive. logic "D",more positlYetMode COntrol = logic "0"AB= llJgic"l"·Chlp Enable = Logic "1" to obtain outputs193

code conversion tablesFUNCTION CODe FUNCTION CODeINPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUTCC0ROM BCOIC EBCDICBCOICEBCDIC00ROM ASCII EBCDICASCII EBCDICADDRESS SYMBOL SYMBOL E • A 8 4 2 1 0 1 2 3 4 5 6 7 0ADDRESS SYMBOL SYMBOL E b6 bS b4 b3 b2 b1 0 1 2 3 4 5 6 7@> 0 Space Space 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 64 @ 1 0 0 0 0 0 0 0 1 .1 1 1 1 0 01 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 6' A A 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1, , ,0 0 0 0 0 1 0 1 1 1 1 0 0 1 0 66 8 8 1 0 0 0 0 1 0 1 1 0 0 0 0 1 03 3 3 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 67 C C 1 0 0 0 0 1 1 1 1 0 0 0 0 1 14 4 4 0 0 0 0 1 0 0 1 1 1 1 0 1 0 0 68 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 05 5 5 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 69 E E 1 0 0 0 1 0 1 1 1 0 0 0 1 0 16 6 6 0 0 0 0 1 1 0 1 1 1 1 0 1 1 0 70, , 1 0 0 0 1 1 0 1 1 0 0 0 1 1 07 7 7 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 71 G G 1 0 0 0 1 1 1 1 1 0 0 0 1 1 18 0 0 0 1 0 0 0 1 1 1 1 1 0 0 0H H 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0• •9 9 9 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 " 73 , , 1 0 0 1 0 0 1 1 1 0 0 1 0 0 110 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 741 0 0 1 0 1 0 1 1 0 1 0 0 0 111 #0. - " "·0 0 1 0 1 1 0 1 1 1 1 0 1 1 75 K K 1 0 0 1 0 1 1 1 1 0 1 0 0 1 012 @lor' @> 0 0 0 1 1 0 0 0 1 1 1 1 1 0 0 76 , , 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1013 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 77 M M 1 0 0 1 1 0 1 1 1 0 1 0 1 0 014 > > 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 78 N N 1 0 0 1 1 1 0 1 1 0 1 0 1 0 115 J(TM) TM 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 79 0 0 1 0 0 1 1 1 1 1 1 0 1 0 1 1 016 Space Space 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 80 P P 1 0 1 0 0 0 0 1 1 0 1 0 1 1 117 , , 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 81 a a 1 0 1 0 0 0 1 1 1 0 1 1 0 0 01 1 A A 0 1 0 0 0 1 1 0 1 1 0 0 119 T T 0 0 1 0 0 1 1 1 1 1 0 0 0 1 1 83 S S 1 0 1 0 0 1 1 1 1 1 0 0 0 1 018 S S 0 0 1 0 0 1 0 1 1 1 0 0 0 1 0.,,.U U 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 84 T T 1 0 1 0 1 0 0 1 1 1 0 0 0 1 1V V 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 8' U U 1 0 1 0 1 0 1 1 1 1 0 0 1 0 0W W 0 0 1 0 1 1 0 1 1 1 0 0 1 1 0 86 V V 1 0 1 0 1 1 0 1 1 1 0 0 1 0 1"23 X X 0 0 1 0 1 1 1 1 1 1 0 0 1 1 1 87 W W 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0,.'425'6"YZf(RM)orYZAM%0000000000111111111100001001100101011,0011111111110000011011000010001001010888990919'XYZI,XYZI,111110000011111111110000100110010101110011111111000000001110100101000010110% ('9 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 93 I I 1 0 1 1 1 0 1 0 1 0 1 1 1 0 130 , , 0 0 1 1 1 1 0 0 1 0 0 1 0 1 0 94 """0. ",1 0 1 1 1 1 0 0 1 0 1 1 1 1 131 ffi 0 0 1 1 1 1 1 0 1 1 1 1 1 1 032 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0330 1 0 0 0 0 1 1 1 0 1 0 0 0 1 97,1 1 0 0 0 0 1 0 1 0 1 1 0 1 034 " K " K 0 1 0 0 0 1 0 1 , 0 1 0 0 1 0 - 98 1 1 0 0 0 1 0 0 1 1 1 1 1 1 135 , , 0 1 0 0 0 1 1 1 1 0 1 b 0 1 1 99 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 136 M M 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 100 $ $ 1 1 0 0 1 0 0 0 1 0 1 1 0 1 137 N N 0 1 0 0 1 0 , 1 1 0 1 0 1 0 1 101 % % 1 1 0 0 1 0 1 0 1 1 0 1 1 0 038 . ·0 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 102 1 1 0 0 1 1 0 0 1 0 1 0 0 0 039 P P 0 1 0 0 1 , 1 , 1 0 1 0 1 1 1 103 1 1 0 0 1 1 1 0 1 1 1 1 1 0 140 0 0 0 , 0 1,0 0 0 1 1 0 1 1 0 0 0 104 I I 1 1 0 1 0 0 0 0 1 0 0 1 1 0 1I 41 A A 0 1 0 0 0 1 1 1 0 1 1 0 0 1 105 I 1 1 0 1 0 0 1 0 1 0 1 1 1 0 1050 8 8 0 1 1 0 0 1 0 1 1 0 0 0 0 1 0 114 , , 1 1 1 0 0 , 0 , , , , 0 0 , 051 C C 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 '1552 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 0 11653 E E 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 11754 , , 0 1 1 0 1 1 0 1 1 0 0 0 1 1 055 G G 0 1 1 0 1 1 1 1 1 0 0 0 1 1 1 "' 1193 3 1 1,, 0 0, 1 , 1 0 0 , 15 5 1 1 0 1 0,1 1 1 0 0 4 4,1 0 1 0 0 1 1 0,1 0 0,6 6 1 1, , ,0,1 0, , ,1,0,1,07 7 0 1 1 0 1~ 57 , , 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1H H 0 1 1 1 0 0 0 1 1 0 0 , 0 0 0,,. . · , 1 , , 0 0 0 1 1 , , , 0 0 09 9 1 ,'"0 0 , 1 1 1 1 1 0 0 158 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1, ,'"1 0 1 0 0 1 , 0 1 059 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 123 1 1 0 , 1 0 , 0 , , 1 1 060 J:l or) 0 0 1 1 1 1 0 0 0 1 1 0 1 0 1 0 124 < < , 0 0 0 1 0 0 1 1 0 061 I I 0 1 1 1 1 0 1 0 1 0 0 1 1 0 1, ,'"1 0 , 0 , , 1 06' < < 0 1 1 1 1 1 0 0 1 0 0 1 1 0 0 126 > > 1 1 , 0 0 0 1 1 063 , 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1, 1 1 , , ,'"1 1 0 , , 0 , 1 1 ,194

MM4220LR/MM5220LR BCOIC to ASCII-7/ASCII-7 to BCOIC code convertergeneral descriptionThe MM4220LR/MM5220LR is a 128 x 8 readonly memory which has been programmed to convertthe 64 characters of the Binary Coded DecimalInterchange Code (BCDIC) to the American Standardcode for Information Interchange in sevenbits (ASCII-7).The first half of the ROM, from address 0 toROM Code Convertersaddress 63, converts the 64 character ASCIIgraphic subset to BCDIC. The tables show thecharacter assignments and their binary equivalents.For electrical, environmental and mechanical details,refer to the MM4220/MM5220 data sheet.s:s:0l=IoNNor­:tI......s:s:U'INNor­:tIconnection diagramDual-In-Line PackageA, 1 14 VooA, 2 23 NtA, J" Nt8, 0 21 A,8, 5 20 A,8, 6 19 A,8, 1 18 A,8, 8 11 Vee8, 9 168, 10 15MODECONTROLCHIPENABLE8, 11 14 A,V" 11 13 NCTOP VIEWtypical applicationsASCII to BCDICBCDIC to ASCII195

a:..JoNNIt):E:E........a:..JoNNq-:E:Ecode conversion tablesINPUTFUf'jCTlONOUTPUT,~ ASCII SCQleADDRESS SYMBOL SYMf:lOl"..."; ,·": 6lao''" ," "'"I"'"'"" ; :""n: :"":"'" ~"@ ;, ," ;0" ;" 0 ;""..~.. " ";.. ~0"'":" w~" , ~"";,00, ": :: :: :: :: :: :: :: :: :: :::: :: :: :" ..ASCII to BCOICINPUTASCIICODEMe;" " ~., "DATA: : : :: : ;; : : : :;: : ; ; ;:: ; :: : ;: : : ; :: : :: : : : : : ; ; :; ; ;;: ::: :; ;: :: ::: : ; :; ;: : ; :: ;: : ; :.. " "., " '.OUTl'UTSCDle~ . . , . ,:; ::; ; ;: ;;;; : ; : :; ; ;: : ;; : : :;: : :;;:: : :; ; ;; : ; : 1+; : : : : ; ;:: : : : : : ;; :: ::; : ;; ; : ;: ;:; : : ;: :: : :; : :: :.,: :., " " " " ";FUNCTIONINPUT OUTPUT,~ BCDie ASCIIADDRESS SYM80L SYMBOL.." """ : :" : :"'""'" "".."'.." " w0 @0~'","'" " ""..."":",",~ "'" ~'" ,~ 0 0'"'" ~'"'" , ·''" ,," '"· , ,'" ". ; ;". ; ;'" ,w0,""."'"'"'" ·~ ~'"'" ",0.: :: ::: :: :::: : :::: :: ::: :" ..BCOIC to ASCII. .. :INPUTIlCDICCODEOUTPUTASCII" " " "' " "' ": : : :; + , +- + + e+-: :: ; ;'0: : + : : ;: ; ; : : ; ; ;: :+: + -f--+- -, ;: : ; c-+.c+ : ; +--+- ,+- H-+: + ;; + +:..: ; ;: : :o·..; :;: : :; ; ;: :,. H ;; ;: : : : ;:: ; ; ; : ; : ;;; ; ,.: ; ;; : : :;:: : : : ; ;;; : : ; ; ;;: : : ; ; : :; : ; : ;: : :: : :,;: : ; ; : ; : : ;: : :;: : ;; : : :: : : ; ; : : : : :: ; ; ;; ;: : :: : :" ., ., ;: ;; ;: :" " " " " ".. "., "196

ROM Code ConvertersMM4221RO/MM5221RO ASCII-7 to EIA RS244AIEIA RS244A to ASCII-7general descriptionThe MM4221RQ/MM5221RQ is a 1024-bit readonly memory that has been programmed to convertbetween the American Standard Code forInformation Interchange, compressed to six bits,and the-- Electronic Industries Association numericalcontrol standard code, RS244A. The secondgroup of addresses; from 64 to 127, effects thereverse conversion.applications informationIn the first 64 entries, compression of ASCII-7 tosix bits has been accomplished by dropping bit b 6 ,and substituting the control codes listed for certainunused ASCII graphic symbols.In the second 64 entries, the RS244A parity checkbit, C5 is ignored. The bit Ca, used only for theend of block code (EOB) is used externally to detectexistence ofthis symbol, and to insert a redundantcode, C 4 . C2 (ROM address 74). This codewill be translated arbitrarily as an ASCII EXT.typical applicationLOWTRllE~ASCIIIII ,c. I "c,o-I------Ic,~---___lII .,1------------.--...---:--10,t-----l---l o,.,t----------..--t-+-_---'-'i!-i--l.,I----------1~-+--t--t-_...---'F-t---ilOW TRUE,-----------..-,ASCIIRS244AIc,c," I------+---lt----I-~--t-_...----'F_+-lc,.,I----_-t----lt----I-~--t-_...----'F_+-lc,c,c,o-I----Ic,c,o-----IOLl6.8Kc,c,INPUTMULTIPLEXERCODE 0 RS244A tn ASCIISELECT 1 ASCII to RS244A"lOW-GraphicHIGH-Co"u.1197

,~code conversion tab lesADDRESSI--+-:""""""'"'"~""., ...,.. ".. "".."~I ::I---{;--INPUTASCIISYMBOL"'m00'%~"':""".''"FUNCTlO"l".ASCII to RS244AOUTPUT,INPUTSYMBOL ,CODE, "I .. I .. I~ I., I.,"' :". : : , ; ;% , ,. : I". " II:11: I: I: :: 1:: I", :".. .. " " " " ..RS244A to ASCII"'. '.OUTPUT'. '. " " ":: : : : : : :; ; ;; : : : :;;; ; : ; ;: : : : :;,: : : : ,, : : ; ;0< : I"I : : : : ;: 1In" •.,.nq8,n.,,, Seque"": : : : ;: : ; ;1: ; :I: : ; ;I; : :, : I : ; ;: ;I : : : ; ;:; ;I : :;. : :I : : : :: :I : ;; ; ;" .. " .. " " ";--I--;-f-} :-1"".'''''9 8,,, ..,50" .."",,,, f-'-~198

ROM Code ConvertersMM4221RR/MM5221RR ASCII-7 to EBCDIC code convertergeneral descriptionThe MM4221RR/MM5221RR is a 1024-bit readonlymemory that has been programmed. to convertbetween the 128 characters of ASCII-7" theAmerican Standard Code for I nformation I nterchangein seven bits, and EBCDIC, an extendedbinary coded decimal interchange code. This conversionfollows the EBCDIC character assignmentsused in the IBM 1130 computer.Certain arbitrary assignments have also been madefor maximum usefulness, and in these two areasthe part differs from the MM42300Y /MM52300Y,which follows American National Standard ANSIX3.26 recommendations for character assignments.For electrical, environmental and mechanical details,refer to the MM4221/MM5221 data sheet.typical applicationASCII-7 to EBCDICMS. b,ASCII-718A,+5V12,16.,~'~'__ ~ ______________________ ~.-~19b, A,b520A521b, A,b, A,MM4221RRIMM5221RR• ,~'~O ______________________ ~,-__ r-~EBCDICBINARYHIGH TRUEOMS •.,~------------------~,---r---r-~B5~--------------~'---r---r---r-~.,~----------~~--~--~--~--~~b, A,lS. b, A,lSBlOWTRUE15,11,24S.8K 6.aK 6.BK S.aK 6.BK 6.BK 6.aK 6.aK-12V199

IXIXor-NNL('):E:E........IXIXor-NNIIQ':E:Ecode conversion tables'"SYMBOL'"'"""m'"'"'"""'"0'CONTINUING BINARYSEQUENCEoeoe, 1'1'1'1'1'1'III.."'CONTINUING BINARYSEQUENCE200

11151 ROM Code ConvertersM M 42 30 B O/M M 5230 B 0 hollerith to ASCII code convertergeneral descriptionThe MM4230BO/MM5230BO 2048-bit MOS read- used to compress the 12 Hollerith lines to eightonlymemory has been programmed to convert the line binary encoded form suitable for use by the12 line Hollerith punched card code to eight level read-only memory. This application is shownASCII. This conversion conforms to the American below.National Standard (ANSI x 3.26 - 1970). Three For electrical, environmental and mechanical de-TTL 4-input NAND gates, and three inverters are tails, refer to the MM4230/MM5230 data sheet.typical applicationconnection diagram.'U~C"EOCARDDATAINPUT."'DM14l0HPES OM.aurVPESMODEcornROL,4IN'UTIOAND~AHSARE' ..4.Jk'"... I InUlI'lITASCIH" , " " -[)o- '.~:-+ ..'r-,, ...MM!i231180Dual-In-Line Package,- Az- 2 nt-Nt" ~ ", 'r- "A,_ 1 nt-licB,- 4 211-"-4-p. " B,_ Ii 20t-~.. " 'r- '.B3- B 191'--'118.- 1 'I rA7ZONt['11 AJ 1•A.- IZ4t-- voo'r- "Is- I 11r-1I.1"" 'r- "B I_IItrVoo81 - 10 15 t- ~~::ROL" "PIINCHU ,1.- 11 14r~:~BlEivss_ ~1" "' " " "13rA.NOTUI.V .. =>U.IIVIII%,Voo.GNO.VGo--,Z.fVIII'!Z. n.Hol""'h, .."td'lIlli""'.'.lIIIhI21~ e 12/8 12/15 13/6 14/6 SO RS ACK 9/14 14/12 15/2 15/8 15/14 9-6-68-7 !CD ell , " 12/9 13/0 13/7 14/7 SI us 8EL SUB 14/13 15/3 15/9 15/15 9-8-7CD may be "I" Note: The entries of Form AlB refer to the unaS5lgned locations in the right hand side of the ASCII table (bit EB : 1)deSignated for specIalist use. (See National Bureau of Star>dards Technical Note No. 478.1®may be"'"Note: For the full ASCII-8 Code Table, see MM42300V/MM5230aV data sheet.201

ROM Code ConvertersMM4230FE/MM5230FE selectric-to-EBCDIC/EBCDIC-to-selectric code convertergeneral descriptionThe MM4230FE/MM5230FE provides for the conversionof I BM Selectric Correspondence Code toExtended Binary Coded Decimal Interchange Code(EBCDIC) in both directions. These two decodersare contained on a monolithic MOS device.The Selectric-to-EBCDIC converter is located inbinary addresses 0 through 127. Input bit A7 isused as a single line command to determinewhether upper (denoted by a "1") or a lower(denoted by a "0") case has been selected.The EBCDIC-to-Selectric converter is located inbinary addresses 128 through 255. Since not allEBCDIC control commands have Selectric codecou nterparts, it is not necessary to encode bitposition 0 (A8), which is used instead as the codeconverter selection bit. In addition to the SelectricCorrespondence output code bits there is a bit toindicate upper or lower case. The odd parity bitgenerated does not account for the case bit.device characteristicsFor full electrical, environmental, and mechanicaldetails refer to the MM42301MM5230 2048-bit readonly memory data sheet.typical applicationconnection diagram-12Vdc---____________-4I~.....__.+12Vdt:----~ ......... __.+5Vdc--+---+--+-i--------II--+-i---.--OM8812TTL GATESl.OK,TYPICAL, v" 12B LINESA,3A,2A,1A,21A,20vD:F14MM4230FE/MM5230FE16,7VGG"""""UK,TYPICAL,8 LINES1O-__ -I__A""I 6 19 91-';...' ___-1_-1k> __ ~-~A~7 18 lnl-'~'----I--IJC> __ -4~_A"ia 11-12Vdt·CHIPENABlE~~=-:'+'2Vdc"";;;;;';;':';==--Il1t-·;...· ----4..--tDM140D SERIESTTL GATESA, 14 VooA, 2l NtA, Nt""""""""V"10 15A,A,A,A,A.16 VGl;"MODECONTROlCHIP11ENABLE12 IJA'TDPVIEWLOliclev,liDTl!TTL (ellcept at MOS/ROM interflce)LOlic"I",+5V,nom.lQlic"O",ground,nom.MOSfROM Inpuu& OutputsLogic "1", more negative. logic "0", mon positive·ChipEnlble=Logic"I"toobtainoutpuh202

code conversion table-selectric-to-EBCDICFUNCTIONCODEINPUT OUTPUT INPUT OUTPUTC C0 A"OM SELECTRIC EBCDIC 0 S SELECTRIC EBCDICADDFIESS SYMBOL SYMBOL ", ", ", "2A" '2 0, .2 3, , , , 0, , 0 , 0 , ,,0w , 0 , 0 , , 0 · ·3 0 , 0 ,0 0 , , , ,0 0 0 0 0 0 0 0 , , 0 0, 0 0, 0 , 0 0 , 06 0 0 0 0 0 0 0 06 6 0 0 0 0 0 , , , 0, 0 0 0 0 0 0 0, , 0. 00 0 0 0 0,0 0 00 0 , 0 0 , 0 0 , 0 011 " , 0 0 0 0 0 , 0 , 00 0 0 0 0 0 0 0, · ·00 0 , 0 , , , , 0 0 0 00 0 0 0,0 0 , ,, , 0 0 0 0 , 0NULL 0 0 0 0 0 0 0 0 0 0NULL 0 0 0 ,0, 0 , , 0 0 0 ,NULL 0 0 0 0 0 0 0 0 0 0 0NULL 0 0 0 0 0 , , 0 0 0 0 00 0 0 0,0 0 0 , , , ,0 , 0 , 0 0 , , 0 0 00 0 0 0 0 0 0 07 7 ,0 0 , 0 , , , , , 0NULL 0 0 0 0 0 0 0 0 0 0 0NULL 0 0 0 , 0 0 , 0 0 0 0 0" 26 NULL 0 0 0 00 0 0 0 0NULL 0 0, , , 0 ,"+0 0 0 0 026 , 0 0 0 0 0 0 0,,.00 0 0 ,0,0 0 0NULL 0 0 0 0 0 0 0 00 0 0 , , , 0 , 0NULL 0 0 0 0 0 0 0 0 0 0 0 0" 33 NULL 0 0 0 0 0 0 , 0 0 0 0 0NULL 0 0 0 0 0 , 0 0 0 0 0 0NULL 0 0, 0 0 0 , 0 0 0 0 0 0 0 0 0 0 0,0,0 0,0 0, 0 , , 0 0 , 00 0 , 0 0 0 0 0 0",. , , 0 0, 0 0 , , , , , , ,0 0 0 0 0 0 0 0 00 0 , , , 0 0 , 0 0 0, 0 ,. 0 0 0 0 0, ,00 0 , , , , ,..0" '-- r+~ , 0 0 0 00 ,0 0 0 0 , ..0 0 0 0"0 0 0 0 0 0, ,, , 0 0 , 0 , , , , , , , 0NULL 0 0 0 0 0 0 0 0 0 0 0NULl 0 0 0 0 0 0 0 0 0 0" 60 NULL 0 0 0 0 0 0 0 0 0NULl 0 0 0 0 , , 0 0 0 0 00 0 0 0 0 0 0 0 00 0, ,0, 0 , 0 0 00 0 0 0,0 0 03 3 0 0 , 0 , , , 0NULL 0 0,0 0 0 0 0 0 0 0NULL 0 0 0 0 , 0 0 0 0 0NULL 0 0, , 0 , 0 ,..0 0 0 0"NULL 0 0 , · · 0 0 0 0 0 00 0, , 0 0 , 0 0 0 00 0 0 , 0 0 ,m m 0 0, , , 0 0 0,! 0 , , , , , , , 0"~ 0 , ,0 0 0 0 0, , , ,os.. ·..w0K·00 0 0 0 0 0,0w 0 0 0 , 0 0 , 0 067 , , 0 0 0 0 0 , , 0 0 0 0 0 0 0 0 0 0 ,K 0 , 0 0 0 0 , 0 ,00,0 0 0, 0, " 71 0 0 0 , , , 0 0 0 v v 0 0 0 0 0 0 , 0 H H 0 , 0 0 0 0 , 0 0 ,, , 0 0 0 0 0, , 0 0I I 0 0 0 , , 0 0 0 ,, 0 0 0 0 0 , ,00 0 0 0 , , 0 , 00 0 0 0 0 ,. "· ·0 0 0 , , , , 0 , , 0,NULL 0 0 0 0 0 0,0 0, 0NULL 0 0 0 0 0 , 0 0 0 0 0NULL 0 , 0 0 0 0 0 0 0 0 0NULL 0 0 0 , , 0 0 0 0 0"... 0 0 0 0 0 0 0 0 ,a. N N 0 0 0 , , 0 , 00 0 0 0 0 0 , 0 , 0, , , 0, , , ,a, .. ·NULLNULL'"".. NULL..t4ULLNULLNULLNULL·00 0 0 0 0 0 0 , 0 00 0 0 0 , 0 0 0 0 0NULL 0 0 0 .,0 0 0 0 0 0NULL 0 0 0 , , 0 0 0 0 03 3 0 0 0 0 0, 0.,T T 0 0 0 , , , , 0 00, 0 , , , , 0 0 0 0 0 0.. , , 0 0 , , , , ,0 0 0 0 0 0 0 0 0 , 00 , 0 0 0 0 , 0 0 0 0 00 0 0 0 0 0 0 0 00 , 0 0 0 , , 0 0 0 0'000 0 ~ 0 0 0 , ,C C 0 0 0 0 , 0 '"0"7 A A 0 0 0 0, 0 0'030 0 0, , , 0 0 0 '"0 0 0 0 0 , ,11.' , , 0 0 0 0, 0 00 0 0 , 0 0 0 ,0 0'"'" · ·0 , ,.. 0 , , 0 , , ,,,,.0 0 0 0 0 , 0 0 0110 R R 0 , , 0 , , , 0, ,0, ,»,· ·0'", ,0, , , , 0 , 0 , 0NULL 0 , 0 0 0 0 0 0 0 0 0NULL 0 0 0 0, 0 0 0 0 0'" », NULL 0 0 0 0 0 0 0 0 0NULL 0 , 0 0, , 0 0 0 0 0,,, '" , , 0 0 0 0 0 0 0U U 0 0 0, 0 0'" v v 0 , , 0,0 , , 0 0'"'" · ·0 , ,'TO NULL 0 0 0 0 0 0 0 0 0NULL 0 0 0, 0 0 0 0 0'"NULL 0 0 0 0 0 0 0 0'"NULL 0 0 , , 0 0 0 0 0'"G G 0, 0 0 0 0 0'"'" · ·0 0 , , 0 0M M 0 , 0, , 0 , 0'" ± NULL 0 , , , , , 0 0 0 0 0'" '28 .. 32 ,.. ..IAOM ADDRESS IN BINARYIlA, A, A, A3 A2 All lBa" , . 2" .. .. .., 60 ,0,0 00 000 0,0 00 000 0,, 0000 00 00 00 0,, 00,00 00 0 ,0 00 00,0 00 00 00 00 00 00,00 00 00 0,0, ,, 00 0,0 00 00 00 0, ,0, 00 ,0 00 00 00 0,, ,0 0, 0, ,, 00 00,0 000 00 00,, 00, 00 00 00 0, ,, ,0 ,, 00 00 00 00 00 00,0 00 ,0 00 00 00 00 0 ,0 0,00,, ,, 00 00 00 00 00 00 00, 000 00 00 00 0, 0, ,, ,0 0'3 .,,00,00,00000,,00000,00000,0,0000,0,00,0,0,0000,0000,0,00,00,0000,000O.,0,00000,00000,0,0,0,0000000,0000,00,,'~~~NWo."m........~~enNWo."m203

wu.o('I)NLt):E:E.........wu.o('I)N'lit:E:Ecode conversion table-EBCDIC-to-selectric.OMADDRESS".,~'"'"'"'"'"'"'"'" '"'"'"'",.,,

ROM Code ConvertersMM4230JT /MM5230JT BCOIC to EBCOIC/EBCDIC to BCOIC code convertergeneral descriptionThe MM4230JT /MM5230JT is a 2048-bit read-onlymemory that has been programmed to convert fromthe 64-entry, 6-bit Binary Coded Decimal InterchangeCode (BCDIC) to the eight-bit extendedBCD interchange code (EBCDIC) and back again.The tables show the two translations in binary.Character assignments for the EBCDIC are givento IBM 1130 specifications. All the non-alphanumericassignments in BCDIC are subject to specialistusage, and care should be taken over them.For electrical, environmental and mechanical details,refer to the MM4230/MM5230 data sheet.connection diag ramDual-In-Line Packagetypical applicationsBCDIC to EBCDIC::-:1 f'"u • ... ".6 ...'" ". ". I f'" " I """04'NA", "'''OD'"'--"'- "''"t,,"~,,"~::I "- "I",f-!:--:~-,j, -rITM?-'~,IOOTP""'""'""" m", ,,~~:~INPUTEBCDIC to BCDIC''':~======r¥=~§mm:T.. , I"'j ~"' '" ", '" "', '(.~'p-~' +-I'" -+'"'-+'";:=8,""""",--.---.-.....--+--4 G ::""-+-.... I---"-I~ "',.~' f l"" ~III"1-',"f-"I--'-+-+-+_~f__I--i-JI ~". ".I--'---~+_~f__I~~I--'---~f__I_+~~I~f--!'---4.-+-+--:-rlY----­I--'-------~~~~'f-.-'---------~-L{I Uo---::.'f--"---I,~ I: I~"'fl,~JlL--~==~-~--L'-1dP-~------------------------~205

,~-~code conversion tablesBCDIC to EBCDICFUNCTIONCODECODEIN~UT OUTPUT OUTl'UT,~ BeOle tSCQIC EBCDICADO~ESS SYMBOL SYMIIDL" ".. .. " " " "NULL NULL: : : ::: : :. .": :": :"~Sp..,': : : :" ;:w w"; ; :NULL NUU", , : :;;: : ;'" : ;"~ w"0., ..,....: ;.. w:": ;: :; : ;"..::"I-,,,'"'"NULLNULCNuLLNULLNullNULLNULLNULLNucLNULL105 NULL'"1

ROM Code ConvertersMM4230KP/MM5230KPASCII-7 to selectric code convertergeneral descriptionThe MM4230KP/MM5230KP MOSread-only memoryhas been programmed to perform the conversionbetween the American Standard Code forInformation Interchange in seven bits (ASCII)and the Selectric correspondence bail code transmittedand received by the I BM Series 7 input/output printers.application hintsThe ASCII field and Selectric bail code field asdefined do not map exactly: for instance "space"is handled as a normal 7-bit code in ASCII, but ishandled as a unique switch and solenoid pair in theSelectric printer. And even among the graphiccharacters, ± and rf. exist only for Selectric, and>and < only for ASCII. The former problem ishandled in the MM4230KP/MM5230KP by exploitingthe inherent redundancy of the bail code(see Table 2). The latter inconsistency is resolvedby making arbitrary equivalences between theunique characters. The two tables show the treatmentof both the characters wh ich have equivalentsin both codes, and those characters, and the functions,which do not. Encoding and decoding theSelectric functions that the user requires is amatter of conventional Boolean logic. A typicalexample is shown below.For electrical, environmental and mechanical details,refer to the MM4230/MM5230 data sheet.typical applicationBAilCODEINPUTSfROMSELECTRICASCII(lUTPIJTCOWlRlIEI~ INPUT,,,:=11" ,lis,-f--A HIGH ASCII I. $,1.",,, O"'~"tA lOW S.I«t"c to ASCII Inp"1I,r-+:1'

code conversion tables~b5" b4 b3 b2 b,~oI I I I Row. -0 0 0 0 0Table 1. ASCII-7 to Selectric0 0 0 0, ,,0 0 00, , ,0, ,00, , 0,0,2 3 4 5 6 7NUL OLE SP0 @ P P02 OA 62 250 0 0, , SOH DCI ,I A Q , q12 IA0 0, 0 2STX220 0, ,30022AETX DC332 3A0, 0 0 4EDT DC403 OB0, 0, 5ENO NAK13 IB0, , 0 6ACK SYNBEL23 2B2B R b3 C S , ,S 4 0 T d ,% 5 E U ,& 6 F V I ,0 I , ,733 3B 25, BS CAN0 0 0• 42 4A, 0 0, HT EM952 SA, 0, LF SUB0 A53 6A, 0, , VT ESC•,K, , FF FS 0 0 C N, , , , 51 USFETB7 G W 9 wI•H X h ,I 9 I Y yJ Z,II 1k72 7A 7F 7F\ :I72 4B 40 60 481m 153 5B 77 7763 6B 50 70 58DEL/ ? a p73 7B - 00A"-Table 2. Selectric to ASCII-7R5 0 0 0 0, , , ,T, 0 0, ,0 0, ,T,---- 0,0,0,0,S R,. R, R,K II I I I Row -- 0 , , 2 3 4 5 6 70 0 0 0 00 0 0, , y h , 0-2/0b w 9~ 4 ~4 V#I/3/0 6/C 6/F0 0, 0 2~ ~ ~ 1~~" ~ ~~ ~0 0, ,3~ ~ ~ ~ 8 W* ~ *0, 0 0 4 Q k ,6, ,2/C •0,0,5 P ,,21753/B4d 70, , 0 6 2 f3/02/E0, , ,V,!7 J , , ,9 m,2/,, 0 0 0• - B W I~ 7/v(: [j~ ~ffi, 0 0,9 Y H S I, L, 0, 0 A~ ~ ~~ ~ :f7~ ~ ~~ ~;, 0, 1 Bft ~ ~ ~1£ ~ ~ ~ ~, 1 0 0 e 0 KI,C A4/9 6/3 2/e, 1 0 1 0 P E % 0 R &"P4/F3$1 1 1 0 E,N, , , ,F J T@ F U v #2/EY.,0±IF/F Z G X M5/B. / C ASCII shown thus. Column No.JRow No.208

~BlillSROM Code ConvertersMM42300W/MM52300W hollerith to EBCDIC code convertergeneral descriptionlines to eight line binary encoded form suitablefor use by the ROM.For electrical, environmental and mechanical de-tails, refer to the MM4230/MM5230 data sheet.The MM42300W/MM5230QW 2048-bit MaS readonly memory has been programmed to convert the12 line Hollerith Code to the 8 line EBCDIC Code.Three TTL 4-input NAND gates and three TTLinverters are used to compress the 12 Hollerithtypical applicationHollerith to EBCDICconnection diagramDual-In-Line Package4 INPUT N~ND GATES AREDMJ4JOlVP!SDMi811TVPOS'»'"",;:;:::::I,-" 3'"IMODEICONrRO~UK UK HCDICOUTPUT.,~'r-8,-4 21r-.A.:-t..'r- ,6,_5 lOrA,"-,_I24f--Voo" " " , '" A,-2 2Jr-NCINPUT(..£ONE 11" "MM52l00W,M" 'f-8,-6 19r-A •.PONCHEDCARD'r-" " 'f-A,-322r-NC,8,-8 11r- ,!,.84-1 lsr-A),8._9 lGr-OGG8,_10".. 8._11..,PONCHES ,," NDTES" "L VS5~'1l DO 111%, Voo' GUO. VOG -12.0011)0/.DEVICE2. Th. H,II.",~ "pu' ,", lion" 1 'h"'ln III ",.."d...,~:=hf:~~o~~,':'~:.'::"~" .';~:; """",d, ,. ,h."" ,I •,." "r"5.iK6,i~'"'"'»I 1CHIP'00 .!,"=' lINES8T011 ENAULE~:!,::' r J '" -0HIGHTAUl'"V .. _12TOPVIEW151- ~~~~ROl14t- ~~~9LE1JI--A.code conversion tableHollerith to EBCDIC12 12 12 12 12 12 12 1211" " 11 110 0 0 0 " 0 0 " 0 " 0& SP I I 70 49 59 69 BO 90 AO BO B-1•1 A J I 1 , ISOH OCl 21 31 41 51 E1 71 9 -12 B K S 2 b k , B2 STX OC2 22 SYN 42 52 52 72 9 -23 C L T 3 , I t B3 ETX OC3 23 33 43 53 63 73 9 -34 0 M U 4 d m B4 04 14 24 34 44 54 64 74 9 -4."5 E N V 5 c , B5 HT 15 LF 35 45 55 65 75 9 -56 F 0 w 6 f 0 w B6 06 BS ETB 36 46 56 66 76 9 -67 _G P X 7 9 P , B7 DEL 17 ESC EDT 47 57 67 77 9 -7B H 0 Y B h q y BB DB CAN 2B 3B 4B 58 6B 78 9 -B9 I R Z 9 ; , , B, 09 EM 29 39 NUL OLE 20 30 9-8-1B-2 [ I \ BA 9A AA BA OA lA 2A 3A CA DA EA FA 9-8-2B-3 $ BB 9B AB BB•VT lB 2B 3B CB DB EB FB 9-8-3B-4 < % @ BC 9C AC BC FF FS 2C DC4 CC DC EC FC 9-8-4B-5 [ I - BD 90 AD BD CR GS END NAK co 00 ED FD 9-8-5. B-6 > BE 9E AE BE so RS ACK 3E CE DE EE FE 98-6B-7 !CD '(j) ,BF 9F AF BF 51 US BEL SUB CF OF FF FE 9-8-7CD may be "I"CD maybe"!"Note: Una ..,gned enlrles

code conversion table0---0 0 01---0 0 02---0 0 13---0 1 04 5 6 7~ 0 1 2I I I I Row. NUL OLE0 0 0 0 0 8000 10SOH DCl0 0 0 1 1 8101 11STX OC20 0 1 0 2 8202 120 0 1 1 3ETXOC303 130 1 0 0 4 9C 90 84HTLF0 1 0 1 5 B509 OA0 1 1 0 6 B60 1 1 1BSDEL7 877F1 0 0 0 8 971 0 0 1 9 80CANEM83ETB08 171819ESC8889lB0 0 0 0 0 10 1 1 1 1 01 0 0 1 1 01 0 1 0 1 03 4 5 6 7 890SP & -20 26 20BA C3.91 AO A9I882F 61SYNb16AI AA 82 BC6293 A2 AB B3 BO94 A3 AC B4 BE95 A4 AD B5 BF96 A5 AE B6 COc63d.EOThA6 AF B7 Cl04 6798 A7 80 88 C299 A8 81 89II,6465666860 691 1 1 10 0 0 10 1 1 01 0 1 09 A 8 CCA 01 08I7Bi - AD96A 7E 41k s 8OA6B 73 42I t CDB6C 7443m u 0DC60 7544n v EDO6E 76450 w FDE6F 77 46P . GOF70 78 47q V HEO71 79 48, z IEl72 7A491 11 10 11 00 EI \70 5CJK4AS9F4B 53L T4C 54MNU40 55V4E 580 WPQA4F 57X50 58Y51 59Z52 5A1111F03013123233343453563673783893901234567893:~.p.NWo....... > -9E + C828 . 38 3E 3DSUB,>.."C9lA 21 5E 3F 22CB 02 E2 E8CC 03 E3 E9CD 04 E4 EACE 05 E5 E8CF 06 E6 ECDO 07 E7 EDEEEFFOFlF2F3F4F5F6F7F8F9FAFBFCFOFEEOFFA8C0EFot ' "C5'-L1E- __ ~5~r. - ----, "Hexadecimal EBCDICCharacter Address--'0Location In ASCII·8 (ROM COntICharacter AssignmentIIf Any)211

ROM Code ConvertersMM4230QY/MM5230QYASCIl-8 -to- EBCDIC-8 code convertergeneral descriptionThe MM4230QY /MM5230QY is a 2048-bit readonly memory that has been programmed to convertthe American Standard Code for InformationInterchange extended to eight bits, (ASCII-8) toExtended Binary Coded Decimal I nterchange Code(EBCDIC-8). The conversion conforms to the practiceestablished by the American National StandardANSlx3.26 1970. Exact details are shown in thecode table.For electrical, environmental and mechanical details,refer to the MM4230/MM5230 2048-bit readonly memory data sheet.typical applicationconnection diagram-12\1·svINPUT AJ 14 Voo'" E,E,A,16\l GwB,68K,TYPICAL,8ltNESGATES DM7400INPUT A/ 13 NOINPUT A, 12 NOOUnUT 8, 21 INPUT A.OUTPUT B~ 10 INPUT A~E,0 E.0~z E,M"E,E, 182120"MM42JOQV!MM52l00YB,E. 11 10B.+12\1 11·CHIP ENABLE + __.JB,B,B.B,B,OlL/TTL lOGICnJ ~OUTPUT BJ"INPUT "6OUTPUT 8. lB INPUT A,OUTPUT 8~ 11 INPUT AsOUTPUT 8(, 16 VeeOUTPUTS, 10OUTPUT 88V" 11TOP VIEW""MODECONTROLCHIPENABLEINPUT 11.9MODE CONTROl+-----'LlllkLwei.OnmL lucept.t MOStROM int.rtu,)Logic "1", +5V, nom. Logic "0", ,round, nom.MOS/ROM Inputs & OutputLOllie "1", more n'lIIti, •. logic "0", mon positive·Chip Enable = LOlie "1"to obtain outputs212

code conversion tableba-O 0 0b7_0 0 01'6-0 0 1b5_0 1 0~ 0 1 2b4 b3 b2 b1 Row+NUL OLE SP•0 0 0• • •0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 91 0 1 0 A1 0 1 1 81 1 0 0 C1 1 0 1 D1 1 1 0 E1 1 1 1 F00 10 40SOH DCl !

ROM Code ConvertersMM4230RS/MM5230RS binary tomodulo-n divider code convertergeneral descriptionThe MM4230RS/MM5230RS binary to modulo·ndivider code converter is set up to generate theprogram input settings for a pair of DM7520/DM8520 modulo·n dividers, in order to divide byany binary number from one to 255. Detailedinstructions for use of the DM7520/DM8520 aregiven in its data sheet.Applying the required division ratio, in binary, tothe inputs of the ROM as shown, generates twosets of four program inputs, one for each of the2 DM7520/DM8520 dividers.For electrical, environmental and mechanical details,refer to the MM4230/MM5230 data sheet.connection diagramDual-In-Line PackageINPUTA3-124f--V"cINPU1A,-223 f-'NCINPUTA,-J22f-NCOU1PUT8,-4OUTPU18 2_521f-INPUTA.20r--INPUTAsOU1PU183-619r-INPUTA.OU1PUT8.-118f-- 1NPUTA,OU1PU185-817r-II'IPUTAaOUTPUTB6-g16f-VMOUTPU187 - 1O 151- ~g~iAOlOUTPUTBB_TlVss-1214 f-- ~~~BLE13!--INPUTA.TOP VIEWtypical applicationBinary to Modulo-n DividerBINARYDIVISORMSB 2' :::" ..-" ::-,'go vOM8810"""()o -[:;:"" ..",.o__-f>o-------........ ~---1-+--+---l'.'.'."T" L0" MODEMM52JOASCONTROl0.0,0.0,0.0.0,I---------------cf>.~ '.-::1----------_-+--,....01>---0,.CONNECTOIRECTTODM7520IDM0520PAOGAAMINPUTSHIGHTRUE214

code conversion tableSETTING -;.-BY SETTING +BY SETTING : BYDIVIDER 1 I DIVIDER 2 DIVIDER 1 I DIVIDER 2 DIVIDER 1I DIVIDER 2B, B, B, 8 s I 8 4 B, B, B, B, B, B, B5 I B, B, B, B, B, B, B, B5 I B, B, B, B,0 1 1 1 1 1 1 1 255 1 0 1 1 0 1 1 0 165 1 1 1 0 0 1 1 1 75I 0 1 1 1 1 1 1 254 0 1 0 1 1 0 1 1 164 1 1 1 1 0 0 1 1 740 1 0 1 1 1 1 1 253 0 0 1 0 1 1 0 1 163 1 1 1 1 1 0 0 1 730 0 1 0 1 1 I 1 252 1 0 0 1 0 1 1 0 162 0 1 1 1 1 1 0 0 721 0 0 1 0 1 1 1 251 1 1 0 0 1 0 1 1 161 0 0 1 1 1 1 1 0 710 1 0 0 1 0 1 1 250 1 1 1 0 0 1 0 1 160 0 0 0 1 1 1 1 1 700 0 1 0 0 1 0 1 249 1 1 1 1 0 0 1 0 159 0 0 0 0 1 1 1 1 690 0 0 1 0 0 1 0 248 0 1 1 1 1 0 0 1 158 0 0 0 0 0 1 1 1 680 0 0 0 1 0 0 1 247 1 0 1 1 1 1 0 0 157 1 0 0 0 0 0 1 1 670 0 0 0 0 1 0 0 246 1 1 0 1 1 1 1 0 156 0 1 0 0 0 0 0 1 660 0 0 0 0 0 1 0 245 0 1 1 0 1 1 1 1 155 1 0 1 0 0 0 0 0 650 0 0 0 0 0 0 1 244 1 0 1 1 0 1 1 1 154 0 1 0 1 0 0 0 0 641 0 0 0 0 0 0 0 243 1 1 0 1 1 0 1 1 153 0 0 1 0 1 0 0 0 631 1 0 0 0 0 0 0 242 1 1 1 0 1 1 0 1 152 0 0 0 1 0 1 0 0 621 1 1 0 0 0 0 0 241 0 1 1 1 0 1 1 0 151 0 0 0 0 1 0 1 0 610 1 1 1 0 0 0 0 240 1 0 1 1 1 0 1 1 150 1 0 0 0 0 1 0 1 601 0 1 1 1 0 0 0 239 0 1 0 1 1 1 0 1 149 0 1 0 0 0 0 1 0 591 1 0 1 1 1 0 0 238 0 0 1 0 1 1 1 0 148 0 0 1 0 0 0 0 1 580 1 1 0 1 1 1 0 237 0 0 0 1 0 1 1 1 147 0 0 0 1 0 0 0 0 570 0 1 1 0 1 1 1 236 1 0 0 0 1 0 1 1 146 0 0 0 0 1 0 0 0 560 0 0 1 1 0 1 1 235 1 1 0 0 0 1 0 1 145 1 0 0 0 0 1 0 0 550 0 0 0 1 1 0 1 234 0 1 1 0 0 0 1 0 144 1 1 0 0 0 0 1 0 540 0 0 0 0 1 1 0 233 1 0 1 1 0 0 0 1 143 1 1 1 0 0 0 0 1 530 0 0 0 0 0 1 1 232 1 1 0 1 1 0 0 0 142 1 1 1 1 0 0 0 0 521 0 0 0 0 0 0 1 231 0 1 1 0 1 1 0 0 141 0 1 1 1 1 0 0 0 510 1 0 0 0 0 0 0 230 0 0 1 1 0 1 1 0 140 0 0 1 1 1 1 0 0 500 0 1 0 0 0 0 0 229 1 0 0 1 1 0 1 1 139 0 0 0 1 1 1 1 0 491 0 0 1 0 0 0 0 228 1 1 0 0 1 1 0 1 138 1 0 0 0 1 1 1 1 481 1 0 0 1 0 0 0 227 1 1 1 0 0 1 1 0 137 1 1 0 0 0 1 1 1 470 1 1 0 0 1 0 0 226 0 1 1 1 0 0 1 1 136 0 1 1 0 0 0 1 1 461 0 1 1 0 0 1 0 225 0 0 1 1 1 0 0 1 135 0 0 1 1 0 0 0 1 450 1 0 1 1 0 0 1 224 1 0 0 1 1 1 0 0 134 0 0 0 1 1 0 0 0 440 0 1 0 1 1 0 0 223 0 1 0 0 1 1 1 0 133 1 0 0 0 1 1 0 0 430 0 0 1 0 1 1 0 222 1 0 1 0 0 1 1 1 132 0 1 0 0 0 1 1 0 420 0 0 0 1 0 1 1 221 1 1 0 1 0 0 1 1 131 0 0 1 0 0 0 1 1 410 0 0 0 0 1 0 1 220 0 1 1 0 1 0 0 1 130 0 0 0 1 0 0 0 1 401 0 0 0 0 0 1 0 219 1 0 1 1 0 1 0' 0 129 1 0 0 0 1 0 0 0 391 1 0 0 0 0 0 1 218 0 1 0 1 1 0 1 0 128 0 1 0 0 0 1 0 0 380 1 1 0 0 0 0 0 217 1 0 1 0 1 1 0 1 127 0 0 1 0 0 0 1 0 371 0 1 1 0 0 0 0 216 0 1 0 1 0 1 1 0 126 1 0 0 1 0 0 0 1 360 1 0 1 1 0 0 0 215 0 0 1 0 1 0 1 1 125 0 1 0 0 1 0 0 0 351 0 1 0 1 1 0 0 214 1 0 0 1 0 1 0 1 124 1 0 1 0 0 1 0 0 341 1 0 1 0 1 1 0 213 0 1 0 0 1 0 1 0 123 0 1 0 1 0 0 1 0 331 1 1 0 1 0 1 1 212 1 0 1 0 0 1 0 1 122 0 0 1 0 1 0 0 1 320 1 1 1 0 1 0 1 211 1 1 0 1 0 0 1 0 121 1 0 0 1 0 1 0 0 310 0 1 1 1 0 1 0 210 1 1 1 0 1 0 0 1 120 1 1 0 0 1 0 1 0 300 0 0 1 1 1 0 1 209 0 1 1 1 0 1 0 0 119 0 1 1 0 0 1 0 1 290 0 0 0 1 1 1 0 208 1 0 1 1 1 0 1 0 118 0 0 1 1 0 0 1 0 281 0 0 0 0 1 1 1 207 1 1 0 1 1 1 0 1 117 1 0 0 1 1 0 0 1 270 1 0 0 0 0 1 1 206 1 1 1 0 1 1 1 0 116 1 1 0 0 1 1 0 0 261 0 1 0 0 0 0 1 205 1 1 1 1 0 1 1 1 115 0 1 1 0 0 1 1 0 251 1 0 1 0 0 0 0 204 1 1 1 1 1 0 1 1 114 1 0 1 1 0 0 1 1 241 1 1 0 1 0 0 0 203 0 1 1 1 1 1 0 1 113 1 1 0 1 1 0 0 1 231 1 1 1 0 1 0 0 202 1 0 1 1 1 1 1 0 112 1 1 1 0 1 1 0 0 220 1 1 1 1 0 1 0 201 1 1 0 1 1 1 1 1 111 1 1 1 1 0 1 1 0 210 0 1 1- 1 1 0 1 200 1 1 1 0 1 1 1 1 110 0 1 1 1 1 0 1 1 201 0 0 1 1 1 1 0 199 0 1 1 1 0 1 1 1 109 1 0 1 1 1 1 0 1 190 1 0 0 1 1 1 1 198 0 0 1 1 1 0 1 1 108 0 1 0 1 1 1 1 0 180 0 1 0 0 1 1 1 197 1 0 0 1 1 1 0 1 107 1 0 1 0 1 1 1 1 170 0 0 1 0 0 1 1 196 1 1 0 0 1 1 1 0 106 0 1 0 1 0 1 1 1 161 0 0 0 1 0 0 1 195 0 1 1 0 0 1 1 1 105 1 0 1 0 1 0 1 1 151 1 0 0 0 1 0 0 194 0 0 1 1 0 0 1 1 104 0 1 0 1 0 1 0 1 141 1 1 0 0 0 1 0 193 0 0 0 1 1 0 0 1 103 1 0 1 0 1 0 1 0 130 1 1 1 0 0 0 1 192 0 0 0 0 1 1 0 0 102 1 1 0 1 0 1 0 1 120 0 1 1 1 0 0 0 191 1 0 0 0 0 1 1 0 101 0 1 1 0 1 0 1 0 110 0 0 1 1 1 0 0 190 1 1 0 0 0 0 1 1 100 0 0 1 1 0 1 0 1 101 0 0 0 1 1 1 0 189 0 1 1 0 0 0 0 1 99 0 0 0 1 1 0 1 0 90 1 0 0 0 1 1 1 188 0 0 1 1 0 0 0 0 98 1 0 0 0 1 1 0 1 81 0 1 0 0 0 1 1 187 1 0 0 1 1 0 0 0 97 1 1 0 0 0 1 1 0 71 1 0 1 0 0 0 1 186 0 1 0 0 1 1 0 0 96 1 1 1 0 0 0 1 1 60 1 1 0 1 0 0 0 185 1 0 1 0 0 1 1 0 95 1 1 1 1 0 0 0 1 50 0 1 1 0 1 0 0 184 0 1 0 1 0 0 1 1 94 1 1 1 1 1 0 0 0 41 0 0 1 1 0 1 0 183 1 0 1 0 1 0 0 1 93 1 1 1 1 1 1 0 0 30 1 0 0 1 1 0 1 182 0 1 0 1 0 1 0 0 92 1 1 1 1 1 1 1 0 20 0 1 0 0 1 1 0 181 0 0 1 0 1 0 1 0 911 0 0 1 0 0 1 1 180 0 0 0 1 0 1 0 1 900 1 0 0 1 0 0 1 179 1 0 0 0 1 0 1 00 0 1 0 0 1 0 0 178 0 1 0 0 0 1 0 189aa1 0 0 1 0 0 1 0 177 1 0 1 0 0 0 1 0 871 1 0 0 1 0 0 1 176 0 1 0 1 0 0 0 1 861 1 1 0 0 1 0 0 175 1 0 1 0 1 0 0 0 850 1 1 1 0 0 1 0 174 1 1 0 1 0 1 0 0 841 0 1 1 1 0 0 1 173 1 1 1 0 1 0 1 0 830 1 0 1 1 1 0 0 172 1 1 1 1 0 1 0 1 821 0 1 0 1 1 1 0 171 1 1 1 1 1 0 1 0 811 1 0 1 0 1 1 1 170 1 1 1 1 1 1 0 1 800 1 1 0 1 0 1 1 169 0 1 1 1 1 1 1 0 791 0 1 1 0 1 0 1 168 0 0 1 1 1 1 1 1 781 1 0 1 1 0 1 0 167 1 0 0 1 1 1 1 1 770 1 1 0 1 1 0 1 166 1 1 0 0 1 1 1 0 76215

A.a:-MNit)~~.......A.a:ROM Code Converters-M MM4231RP/MM5231RP EBCDIC to ASCII-7 code converterNq-~:t general descriptionThe MM4231RP/MM5231RP is a 2048-bit readonlymemory that has been programmed to convertfrom EBCDIC, an extended binary codeddecimal interchange code used in the IBM 1130computer, to ASCII-7, the American StandardCode for Information Interchange in seven bits.This conversion differs from the ANSI x 3.26conversion of the MM4230QX/MM5230QX in thatit follows certain earl ier IBM 1130 character assignments.Also certain EBCDIC control codes arearbitrarily preserved and translated (see translationchart on truth table).For electrical, environmental and mechanical details,refer to the MM4231/MM5231 data sheet.typical applicationEBCDIC TO ASCII-7+5VEBCDICLOW TRUE 12,15ASCIIHIGH TRUEMSBBITD17AaB,11HIGH = GraphiclOW = ControllBA,10B, ~-------------------------'---+--~~--ob,19AaB,A.0,A.MM52J1RP8,A,B,A,8,LSB A,B,16.24,136.8K 6.aK S.BK 6.0K 6.BKDM74046.8K-12V216

code conversion tablesr--ll---1--C1--r"'-Hll:--~--T-:~;------'----'--~IICONTINUING BINARYS~OUENCECONTINUING BINARY1--""'"SEOUE~CEI :;IIII--ohch l-,-h-f=":r2:: ~ggo ~,~+,'~ogl-c~,~-oi[-,--~'~SYMBOL ""'''H-:+--fi+ :f--'--f-'- -r-+- ~H:::H=r-i-rfr±=1:ftH=r:-::r-! : : : 0H--H-I-% 0 0 0, f-'-t-"--io , , 1 ,r.QNTINUING B'NAHYSEQUENCE--+--H--: : : : r+IillIIh--217

«coco~r-..:?!c........«coco~Ln:?!cDM5488/DM7488 (SN5488/SN7488)256-bit read-only memorygeneral descriptionROM Code ConvertersThe DM5488/DM7488 is a custom-programmed256-bit read-only memory organized as 32 8-bitwords. A 5-bit input code selects the appropriateword which then appears on the eight outputs.An enable input overrides the address inputs andturns off all eight output transistors.features• Organized as 32 8-bit words• Open collector outputs provide expansion togreater numbers of words• On-chip decoding• 30 ns typical access time• 250 mW typical power dissipation• Input clamp diodesconnection diagramL 151413 1211 10 9MEOUTPUT YlE0 CBINARY SELECTOUTPUTS"AOUTPUTYflY2Y3YOY5 Y6 Y71, 3,156 7I"GNOtypical applicationStUCT218

absolute maximum ratings (Note 1)Supply Voltage7VInput Voltage 5.5VOutput Voltage 5.5VOperating Temperature Range DM5488 -55°C to +125°CDM7488O°C to +70°CStorage Temperature Range-65°C to +150°CLead Temperature (Soldering, 10 sec) 300°Celectrical characteristics (Note 2)PARAMETER CONDITIONS MIN TYPMAXUNITScs:U1~COCOl>l>.......Cs:-..J~COCOl>l>Logical "1" Input VoltageDM5488 Vee = 4.5VDM7488 Vec =4.75V2.0VLogical "0" Input VoltageDM5488 V ee =4.5VDM7488 Vee = 4.75V0.8 VLogical "1" Output CurrentDM5488 V ee =5.5VDM7488 Vee = 5.25VVa = 5.5V100 I1A40 I1ALogical "0" Output VoltageDM5488 Vee =4.5VDM7488 Vee = 4.75Vla=12mA0.4 VLogical "1" I nput CurrentDM5488 Vee = 5.5VDM7488 Vee = 5.25VVI = 2.4V40 I1ADM5488 Vee = 5.5VDM7488 Vee = 5.25VVI = 5.5V1 mALogical "0" Input CurrentDM5488 Vee = 5.5VDM7488 Vee = 5.25VVI = O.4V-1.6 mASupply CurrentDM5488 Vee = 5.5VDM7488 Vee = 5.25V5080 mAInput Clamp VoltageDM5488 Vee = 4.5VDM7488 Vee ~ 4.75VII = -12 mA-1.5 VPropagation Delay to a Logical "0" from Vee = 5.0VAddress to Output, tpdOT A =25°CPropagation Delay to a Logical "0" from Vee = 5.0VEnable to Output, tpdO T A = 25°CPropagation Delay to a Logical "1" from Vee = 5.0VAddress to Output, tpd1 TA = 25°CPropagation Delay to a Logical" 1" from Vee = 5.0VEnable to Output, tpd1T A =25°CC L =15pF 32C L ='15pF 34C L =' 15 pF 28C L = 15 pF 2750 ns50 ns50 ns50 nsNote 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannotbe guaranteed. Except for "Operating Temperature Range" they are not meant to imply that thedevices should be operated at these limits. The table of "Electrical Characteristics" provides conditionsfor actual device operation.Note 2: Unless otherwise specified min/max limits apply across the _55°C to +125°C temperaturerange for the DM5488 and across the O°C to 70°C range for the DM7488. All typicals are given forVCC = 5.0V and T A = 25°C.219

«0000~.....~c.......«0000~Ln~Ctruth tablesDM5488A/DM7488A SINE LOOK-UP TABLEA pattern has been generated for the DM5488/DM7488. The AA pattern provides a sine table. The 5-bit inputcode linearly divides 90° into 32 equal segments. Each 8-bit output is therefore the sine of the angle applied.EXAMPLE: Input 11010 means 26/32 of 90 0 , or about 73 0 • The corresponding output 11110100 indicates(1/2 + 1/4 + 1/8 + 1/16 + 1/64) or about .95, which is close to the sine of 73 0 • Rounding-off has not beenemployed, since without rounding-off it is possible to extend the accuracy with additional ROMs.INPUTSOUTPUTSWORD BINARY SELECT ENABLEE 0 C A•G V8 V7 V6 V5 y, V3 V2 V,0 0 0 0 0 0 0 0 0 0 00 0 0 0, 0 0 0 0,0 0 0 0 0 , , 0 02 0 0 0 , 0 0 0 0 0 1, 0 0 ,3 0 0 0 1,0 0 0 , 0 0 1 0 ,, 0 0, 0 0 0 0 0 , , 0 0 0 15 0 0 , 0,0 0 0 , , , , 1 09 0 1 0 0 1 0 0 1 1 0 1 1 0 110 0 1 0 0 0 0 , 1 1, 0 0 00 1 0 ,"1 0, 0 0 0 0 0 1 ,12 0 1 1 0 0 0 1 0 0 0 , , ,013 0 1 0 1 0 0 0 , 1 0 0 014 0 , 1 0 0 0 0 0 0 1 0'5 0 , 1 1,0, 0,0 1 0 1,,.161711100000000,0100001,100,11011001011,000,1119 1 0 0 , 1 0 1 , 0 0, , 0 ,20 , 0 , 0 0 0 1 , 0 , 0 1 0 021 1 0 1 0 1 0,1 0 , , 0,122 1 0 1, 0 0,1 1 0 0 0 0 123 1 0 , , , 0 ·1 , , 0 0 1 1 124 , 1 0 0 0 0,1 1 0 1 1 0 025 1, 0 0 1 0 1 , , , 0 0 0 126 , 1 0 1 0 0,1 1, 0 1 0 027 , 1 0 , 1 0 1, 1 1 , 0 0 02. 1 , , 0 0 0 1 , , , , 0,130 1 1-00 1, 1 1 1 1 00 1 1 1 1 0 129 1,1, 0,, , ,31 1 , 1 1 1 0, ,1 1,1, ,1,All X X X X X 1 1 1x - Don't CareDM5488/DM7488 TRUTH TABLEThe output levels are not shown on the truth table since the customer specifies the output condition he desiresat each of the eight outputs for each of the 32 words (256 bits). The customer does this by filling out the truthtable on this data sheet, and sending it in with his purchase order.INPUTSWORD BINARY SELECT ENABLEE 0 . C A GOUTPUTSv. V7 V6 V5 V, V3 V2 V,0 0 00 0 0 0-~.--x ~1 0 0 0 0,02 0 0 0 1 0 03 0 0 0 1 1 00 0 1 0 0 05 0 0 , 0,06 0 0 , , 0 07 0 0 1, ,08 0, 0 0 0 09 0 1 0 0 1 010 0 1 0 , 0 0"0, 0 , 1 012 0 , 1 0 0 013 0 1 1 0,014 0 1 1 1 0 015 0, , , 1 016 , 0 0 0 0 017 , 0 0 0 ,018 , 0 0 , 0 019 , 0 0 , , 020 , 0 1 0 0 021 , 0 , 0 , 022 , 0 , 1 0 023 1 0 , , 1 024 , 1 0 0 0 025 1 1 0 0,026 1, 0 , 0 027 , , 0 , , 028 , , 1 0 0 029 1, , 0 ,030 1, 1, 0 031 1, ,1,0-~ - 1------ -All X X X X X , ,1, ,1,1 1Don't CareNotice: This sheet must be completed and signed by an authoriLed representative of the customer's company before an order can be entered.To be used by National only______ ~Part Number~ ______ s-o. NumberAuthorized Representatlve~ ________ Date~ ___ _Company~ _________________ _Desired Parto oDM5488DM7488220

typical performance characteristicsDelay from Enable toOutput vs TemperatureDelay from Address toOutput vs TemperatureLogical "0" Output Voltage vsSink Current.~...QZQ:i'" cC...C>...a::I I -'45 I-+-+-+--+-+--+-Vee = 5.0V-40 .....35 t-f"'t-+-~t::;pdO:.;;j~F-r-NL.L30 r~+~!~~~t;.d~'~~~~~~25 I"20 ~+--+--+-~-+-+~~r-~15 ~+--+--+-~-+-+~-r-~10 1-+-+-+-+-++++-+--15 ~+--+--+-~-+-+~-r-~o L-~~~~~~~ __ ~~-60 -40 -20 0 20 40 60 80 100120140~...czC>:i:.: '"C>...a::45403530252015105oI-+-+-+--+--+--+-~ee ~ 5.0~-. tpdl_I"""0.70.62: 0.5.. 0.4is> 0.30.2 ~~F""'"0.1Vee = 6.0V-60 -40-20 0 20 40 60 80 100 120140 4 8 12 16 20 24 28TEMPERATURE (OC)TEMPERATURE rC)lOUT (mA)ac test circuitswitching time waveforms5.0V390DM548B/~I'--------' fDM14B8 .---cc • 15 .,INPUT PULSEStr~ 10 liS1,"'10ns!:1MHz1.5V~ROD'''' -+---"",~ - - -INPUTS_ _1.5\1""1'-___ + __---- ',,,or- -''''''r-1.5\1 \. }';7vOUTPUTS1.5V\ 11.5V- ',,~ i-=- - '""221

ROM Code ConvertersDM7598AA/DM8598AA TRI-STATETMsine table look-up read only memorygeneral descriptionThe DM7598AA/DM8598AA is a 256-bit bipolarread-only memory organized as 32 8-bit words.The 5-bit input code linearly divides 90° into 32equal segments. Each 8-bit output is therefore thesine of the angle applies.EXAMPLE: Input 11010 means 26/32 of 90°, orabout 73°. The corresponding output 11110100indicates (1/2 + 1/4 + 1/8 + 1/16 + 1/64) or about.95, which is close to the sine of 73°. Roundingoffhas not been employed, since without rounding-offIt is possible to extend the accuracy withadditional ROM's.The DM8598 is identical to the SN7488 exceptthat the Enable input on the SN7488 simply placesall outputs in the logical "·1" state, whereas theEnable input on the DM8598 places the outputsin a high impedance state. This high impedancestate allows many outputs to be connected inparallel for expansion to greater numbers of wordsand/or connection to a common bus line.features• Organized as 32 8-bit words• Party line capability• On-chip decoding• Pin compatible with SN7488• Typical access time 30 ns• Total power dissipation 350 mW• Compatible with Series 74 TTL and 930 DTL• Strobe input• I nput clamp diodesconnection diagramDual-In-Line Package14 13"1110GENABLEBINARY SELECTA,GENABLEOUTPUTS.....- Y1 OUTPUT YB 0 UTPUT I-- o NORMALOUTPUTSY2 Y3 Y4 Y5 Y6 Y7Hi-ZTOP VIEWtypical system connectionI 0M8598-TT II OM8598III OM8598~T~I~l~~II I I I I IIIII 11111222

truth tableINPUTSWord Binary Select EnableE D C B A G V80 0 0 0 0 0 0 01 0 0 0 0 1 0 02 0 0 0 1 0 0 03 0 0 0 1 1 0 04 0 0 1 0 0 0 05 0 0 1 0 1 0 06 0 0 1 1 0 0 07 0 0 1 1 1 0 08 0 1 0 0 0 0 09 0 1 0 0 1 0 010 0 1 0 1 0 0 011 0 1 0 1 1 0 112 0 1 1 0 0 0 113 0 1 1 0 1 0 114 0 1 1 1 0 0 115 0 1 1 1 1 0 116 1 0 0 0 0 0 117 1 0 0 0 1 0 118 1 0 0 1 0 0 119 1 0 0 1 1 0 120 1 0 1 0 0 0 121 1 0 1 0 1 0 122 1 0 1 1 0 0 123 1 0 1 1 1 0 124 1 1 0 0 0 0 125 1 1 0 0 1 0 126 1 1 0 1 0 0 127 1 1 0 1 1 0 128 1 1 1 0 0 0 129 1 1 1 0 1 0 130 1 1 1 1 0 0 131 1 1 1 1 1 0 1All X X X X X 1 HI-ZOUTPUTSV7 V6 V5 V40 0 0 00 0 0 10 0 1 10 1 0 00 1 1 00 1 1 11 0 0 11 0 1 01 1 0 01 1 0 11 1 1 10 0 0 00 0 0 10 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 01 1 0 11 1 1 01 1 1 01 1 1 11 1 1 11 1 1 11 1 1 11 1 1 1HI-Z HI-Z HI-Z HI-ZV3V20 01 00 01 00 01 10 11 10 01 00 00 11 10 00 10 11 01 01 01 01 00 10 01 11 00 01 00 00 11 01 11 1HI-ZHI-ZV100111000110100011111011101001101HI-Zcs:-..J(IICD(X)l>l>"'­Cs:(X)(IICD(X)l>l>223

Custom MOS/LSIo...ct/)o3s:o(J)........r­(J)Custom MOS/LSI Product FlowI nterface betweenCustomer andDesign/ProductionEngineersTime Sharing ComputerSimulatesStatic and DynamicPerformance andWorst Case ParametersMacrodata FEDISLSI Design SystemProduct DefinitionPartitioningSimulationDraftingDigitizingDavid MannReticle Generator10X Reticle GenerationDavid Mann Camera6-Barrel Step & RepeatMask Making (In-House)Wafer FabricationVolume Wafer ProductionSanta Clara FacilityAssemblyVolume Assembly,WorldwideMacrodata J259, J277100,230-2 LSI Tester100% Wafer Probe Test100% Finished ProductTestQuality AssuranceInternal Spec to MIL-STD 883ReliabilityHigh Rei ProcessingAvailable on all ProductsShipping225

INTRODUCTIONWhile custom and standard MOS have advantagesover each other for specific appl ications, there is ahigh demand for both in today's electronics industry.In most cases, the true test of whether a systemcan most economically be implemented withstandard, custom, or both, can only be determinedafter partitioning. If the quantities in question donot exceed a few hundred units per year, the standardproduct approach is probably the best solution.However, if the total number of units isseveral thousand per year, then customizing isusually the best approach.Custom MOS circu its are designed to do a specificjob. You are not buying capability that is notneeded. The entire chip is devoted to performingyour specific function. Advantages are:1) Fewer Packages2) Lower Power Dissipation3) Smaller P.C. Boards4) Proprietary DesignThese advantages result in lower system costs andprotection of your system design.RESOURCESNational has brought together a group of experiencedcircuit and system designers, separate fromthe standard product group, to offer a customMOS/LSI design service to the industry. This groupis prepared to aid in the logic design of a system,partition the system into feasible LSI circuits ifthe design requires more than one chip, developthe chips, assist the customer in prototype systemcheckout, and put the design into production.National has one of the most advanced IC manufacturingfacilities in the industry. Your customdesign will go through the same production facilitieswhere National's standard MOS products aremanufactured, and thus benefit from our longexperience in MOS processing.As with its bipolar circuits, the key to National'sMOS program is volume production. We are aleading producer of shift registers, read-only memories,and random access memories. I n the lattercategory, National is supplying many second sourceand proprietary static and dynamic RAMs as wellas several advanced large-capacity RAMs. Nationalis also exploring other MOS device applications,such as MAPS (Microprogram mabie ArithmeticProcessor System). This unit contains five LSIchi'ps which, with very few added parts, can comprisea high sophisticated electronic calculator, an"intelligent" computer terminal, or even a lowcostmicroprocessor.National was the first company to offer MOS circuitsthat operate at voltage levels directly compatiblewith TTL. (Previously, level-shifters wereneeded if high-voltage MOS and low-voltage TTLwere to work together). To achieve this so-calledlow-level MOS operation, National pioneered inthe fabrication of circuits made from silicon cutalong the (1-0-0) axis of the crystal. Subsequently,other companies developed bipolar compatibleMOS circuits also. Today, National is investigatinga variety of MOS technologies to determine thebest process to use a specific function. During thepast year, National introduced the silicon gateprocess to the MOS product line; other technologiessuch as ion-implantation, N-channel andCMOS are also being investigated. The companywill use any available technology as a tool toachieve necessary performance for a given function.1-0-0 P-channel metal gate and 1-1-1 silicon selfalignedgate enhancement mode MOS technologiesare presently utilized by National in our standardMOS products. These processes have become industrystandards. All of the P-channel MOS processdevices offer bipolar compatibility.Metal gate devices operate to 3.3 MHz. This technologyis wel.l-suited to random logic and ROMapplications. Higher logic densities and operatingfrequencies approaching 10 MHz can be achievedby using silicon gate technology. This process lendsitself to RAMs, registers, and random logic applications.Static and dynamic logic is available in both metaland silicon gate devices (including ion-implants).In general, less power is dissipated if dynamic logicis employed, which also offers the advantage ofsynchronous operation and eliminates hazards dueto race conditions. In any event, power dissipationof typical LSI functions (up to 1000 gate func·tions) approach 500 mW in devices fabricated witheither metal gate or silicon gate technology.Complementary MOS (CMOS) technology is presentlybeing used on many standard products andwill soon be available for custom products. Structuredlogic, ROMs, RAMs, and registers, designedwith CMOS cannot achieve the density of P­channel MOS. However, quiescent power and dissipationsare less than one microwatt per gate.Operation to 10 MHz can be achieved. One of theadvantages of CMOS is that power dissipation is afunction of frequency, with the DC (quiescent)state consuming the least power.The N-channel process is also undergoing developmentat National. This process allows higher densityand high frequency operation than P-channel.This process is slated for production capabilitybefore June 1972.Ion implantation is a technique that can be appliedto any of the previously mentioned processes. Itallows threshold voltages to be adjusted to a desiredlevel by implanting ions in the gate region. Depletionload devices and large value ohmic resistors arealso being made with ion implantation, whichgreatly improves packing density on LSI chips.DESIGNYour custom design will benefit from National'slongtime experience in the MOS business. Extensiveuse of computer-aided design (CAD) andcomputer simulation programs assure proper operationof your circuit before it goes into production.226

All designs are verified with a circuit analysis programto assure proper operation_ Worst case signalpaths are checked to see that no signal race conditionsex ist_Circuit layouts are performed using both manualand CAD techniques_ Manual artwork generationis produced on rubylith cut and peel material. TheCAD system bypasses this step entirely and goesdirectly from a digitized layout to lOX recticleseliminating the need for rubylith and intermediatereduction steps. National's photomask generationlaboratory is one of the best equ ipped in theindustry including the Macrodata F EDIS System,the David Mann Pattern Generator, Reticle Generator,and 6-barrel step and repeat camera.TESTINGNational has a number of LSI testers that allowcomplete checkout of structured logic (ROMs,RAMs, shift registers, etc.) and random combinationallogic. The random logic testers are computerprogrammed to test to the customer's input/outputlogic specifications. On-line testers include TeradyneJ259, J277, Macrodata 230-2 LSI tester andMacrodata 100 memory system exercisors.After fabrication, each wafer is checked for thresholdvoltage, breakdown voltage, ox ide ru ptu reand sheet resistivity. The wafer then goes intofunctional test. The logic on each die is thoroughlyexercised. This 100% test of each wafer eliminatesany functional defective die from being packaged.After packaging, all devices are stressed to environmentalextremes. The packaged devices are thenreturned for another functional test. Dependingon the customer's requirement, packages can betested under a variety of environmental conditionsand can be subjected to a burn-in cycle. Full MIL­STD 883 processing is offered on all Nationalcustom and standard MaS devices.QUALITY ASSURANCENational's quality assurance department has a completeand comprehensive qual ity control programwhich effectively controls component parts andvendors at a quality level of functional, workmanshipand dimensional criteria. The QA program alsocovers in-process controls of assembled devices,final electrical test, marking and final shipment ofapproved product. All procedures are documentedat specification control and at respective qualityinspection stations. Weekly and monthly reportsare generated for quick feedback of informationfor corrective action purposes.All inspections are performed to specified internalAQL inspection levels which meet or exceed MI L­STD 883.RELIABILITYThe reliability evaluation program in effect atNational is a continuous monitor on the processstability of assembled devices on extended lifetest. Tests which are performed on a continuousbasis on each process are:(a) High Temperature Operating Life Test (extendedlife)(b) High Temperature Storage Test (extendedlife)MIL-STD 883, which specifies testing proceduresfor integrated circu its, was innovatively handled byNational. The company adopted 883 specs as itsown, rather than to set up one procedure formilitary orders and another for industrial customers.Therefore, there are no dual standards atNational. All devices are given the same qualitycontrol treatment and the company inventoriesdevices with guaranteed 883 specs.All standard devices undergo M I L-STD 883 testing.They are 100% subjected to a temperature cycleper Method 1003 Condition D, fine leak test perMethod 1014 Condition A, Helium 5 x 10- 7 , andgross leak test per Method 1014 Condition C.The company has been informed by the NationalAeronautics and Space Administration that it hasreceived line certification under M I L-M-3851 0, thenew military standard defining acceptable proceduresfor producing devices.A customer may request any special rei processingper Document NSC/0002. The intent of this documentis to provide the user with the ability toprocure any integrated circuit manufactured byNational to any class of M I L-STD 883 processing.PACKAGESNational offers a variety of dual-in-line packages(DIPs), metal cans, flat packs, and specializedpackages. Both ceramic and molded packages areavailable.All packages meet the standard JEDEC registeredoutlines. Lead finishes are available in either goldor tin. The ceramic packages meet a leakage of5 x 10- 7 std cc He/sec leak rate. National's moldedpackages are the most advanced in the industryand afford reliability which rivals the ceramicpackages.FACILITIESIn addition to its 150,000-square foot Santa Clarafacility, National has operations in Connecticut,Singapore, Hong Kong, Scotland, Germany andAustralia totaling over 300,000 square feet. Personnelis presently over 3,000 worldwide.I n Singapore, National completed its 90,000-squarefoot facility prior to fiscal 1971 but assembly andtest functions were substantially expanded duringthe past year. The Hong Kong plant doubled insize and will again expand in 1972. In Europe, testand warehousing facilities in Scotland and WestGermany continued to grow in fiscal 1971 in preparationfor future assembly operations. The establishmentof NS Electronics Pty. in Australia providesthe company with an assembly operation inthat part of the world.(")c:en~o3~ofJ)........r­fJ)227

Application NotesJUNE 1970»zI~oTHE SYSTEMS APPROACH TO CHARACTER GENERATORSA huge new market for man/machine interfaces isbeing created by the increasing availability of lowcost data processing through computer timesharing, LSI calculators, minicomputers and digitalbusiness and control systems. In tl:lrn, the pressureis on to design CRT terminals, displays and tele·printers that are at least as compact and inexpen·sive as the new data processors.MOS integrated circuit producers are in the thickof this competition. They have begun makingread only memories and shift registers with enoughstorage capacity to put an appreciable dent interminal and printer costs. Entire alphanumericcharacter fonts and CRT refresh channels now canbe fabricated as single-chip arrays. Low thresholdMOS processes and designs have been refined tomake the storage arrays more compatible withbipolar logic and standard power supplies.These developments have won MOS a place on thealphanumeric side of the readout family tree inFigure 1 (and some inroads are being made on theother side-see Appendix on Page 239. In fact,MOS has pushed beyond the state of the art.MOS/TTL assemblies can generate charactersfaster than they can be handled by moderatelypriced CRT video circuitry or printer mechanisms.However, the increased storage capacity and speedalso make higher performance systems feasible.For example, designers are considering larger fontsthat make characters more legible. Large fontshave generally been economically impractical inthe past because even a small increase in font sizecan double the memory size needed.MOS ROMS AND REGISTERSLarge capacity, high speed, and bipolar compatibilitystrike directly at the problems involved inlowering data terminal costs. To generate and updatereadouts with many characters and symbolstakes thousands of bits of storage and fast manipulationof data and control signals. If this capabilityis supplied in a central processor, it must be paidfor in the form of central system overhead andcommunications costs. Using pre-LSI memorytechniques in the terminals, however, can easilydouble the cost of each console. lStorage capacities per MOS chip have increased atleast tenfold in the past few years, with comparablereductions in assembly costs. By the close of1969, MOS/TTL character generators cost abouthalf as much as those built with bipolar devices.The newest ROMs (read only memories) for charactergeneration represent the integration of some3,000 diodes and 50 packages of IC gates. Oneterminal manufacturer who made the changeoverlate in 1969 replaced six large printed circuitboards with one plug-in card.The largest MOS ROMs mass produced last yearstored 1024 and 2048 bits-general purpose sizesused for table lookup, microprogramming andrandom-logic functions as well as character generation.A typical generator contained three 1024-bitROMs, such as National Semiconductor's SK0001and SK0002 kits (see Table 1 and Figures 2 and3). Generating the standard 64· ASCII-selectedcharacters in a 5 x 7 font requires a storage capac-»'0'0...oC»n::T....oo::TC»...C»n....(1)...G)(1)::s(1)...C»........oenNEONTUIEFILAMENTTU8ERASTER stANTVPEWRITERS·1'.tKERTAf'E"DISPLAY.THE·PRINURSDISPLAYS TERMINAU (KAMMERORBAlLtGASDISCHARGEGASREADOUTSEGMENTEDELDIGITALElPLATESSCAN·TYPE£l'ANHSIFUTURE)VERTICAL SCANDISPLAYSVECTORDISPLAYSTAPEPUNCH(S'PRINTERSTHERMAL,ELECTROSTATIC.ETCfLUORE5tUnDISPLAYLEDIODESOSCILLOSCOPESOTHEROTHERRADAR,MILITARY'ETCLE~LlGHHMITTINGEL-El£CTROLUMIIilESCEfHFigure 1. Display Family Tree229

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I, 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1.~ 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1o 0 1 1 0 0 1 1'. 0 1 0 1 o 1 0 1 o 1 0 1 0 1 0 1CHAR 0 B 4 12 2 10 6 14 1 9 5 13 3 " 7 15ROW.~ 'e1 0 i........::::: :..!.:: .. : .. ::::i:: :::.: ... :.. ...... :: .:: ....: ...: .... : .. :.... ..i·· i::: I·::·:::: .... : : ..... : ...... :: ... :.... .... . .......: :: ....... .... :::: ... = .... .Figure 3a. Raster Scan Character Font'0 0 0 -0 0 0 0 0 0 1 1 1 1 1 1., 0 0 0 0 1 1 1 1 0 0 0 0 1 1'. 0 0 1:::;. !.. i.i·::·· :..: ." 0 1 o ,. 0 1 o 1 0 1 0 1CHAR 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15ROW'. "..... : :..: :.: :...:: ::.:. : :. :.... ........:.::.: : i .. ·· i .... ;:::: : . .: r·· ! ·:i r··i J... . :. ::...... . ··i·· :::.: ........ ....... ..I ....:.:: : i ....:..:: .....:... : ...1 0 • .:.. : ••••••••• : ··.r·f::i::::: .. . ..:: .. : :... . ... :: ...:.... :..:.... ........t::. i : i i .... :......::...::.. . ... : : ... : : ........... .: ... : ..... i ... ::.: .... : ......... .Figure 3b. Vertical Scan Character Font. .. :: .... :J>Z~o....j:rCDC/)"0"0...oQ)n:rg(1:rQ)...Q)n....CD...C)CD::lCD....Q)....o ...enbits needed to select the individual lines or columnsof dots that form the characters in the6 LINE ASCII {C ~INPUT ~LINE ADDRESS 0-INPUTS ::L..--r---lCHIP ENABLE 0--_ ... 1~Of-of-o DATA1-0 OUTPUTSt-o1-0Figure 4a. MM5240 Raster Scan Character GeneratorElement6 LINE ASCII {-EINPUT ;::_0-VOGIt-o~COLUMN ADDRESS ~ ~INPUTS 0:: .....'----,.----'1-0CHIP ENABLE 0--_ ... 11-0 DATAf-o OUTPUTSFigure 4b. MM5241 Vertical Scan Character GeneratorElement5 x 7 x 64 dot matrix. The output bits formingeach dot line or column are presented in parallel.The parallel outputs are serialized by a TTL registerand used to control the CRT beam or theprinter mechanism. To simplify the selectionprocess, the ROMs are programmed to generatethe lines or columns in the correct sequence whenaddressed by the sequential outputs of a TTLcounter.As for registers, they became quite popular during1969 because a CRT refresh memory of up toabout 5,000 bits-enough for a display of morethan 800 characters-could be built less expensivelywith MaS dynamic registers than with delaylines. 2 This was achieved with registers containing200 storage stages per chip. During 1970, dynamicregisters up to 512 bits long will go into massproduction, giving rise to predictions of significantsavings in refresh memory costs. Whether savingsthat large can actually be realized will dependupon how quickly the new devices catch on and gointo volume production.Aside from cost per function, other pertinent considerationare temperature sensitivity and functionalflexibility. In a refresh memory, registeroutputs are fed back to the inputs. On each recir-231

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generates one·seventh of each character in a row ofdisplayed characters. The output is serialized bythe TTL register and used to intensity modulatethe CRT beam as it sweeps across the screen.OATAINPUT(6 BITSIM lOOPN lOOPSERIALOUTPUTSIPCONV.Figure 6. (M·N)+N Technique for Large Page DisplaysThe refresh memory registers are divided into M·Nand N sections to facilitate page displays. M is thetotal number of characters displayed in severalrows (lines of the page) and N is the number ofcharacters in each row. To form such a displaywith single·loop registers, as in Figure 5, wouldtake seven recirculations of all M data wordsduring each refresh cycle of the CRT. The techniquein Figures 6 and 7 only requires high speedrecirculation of N bits at a time, with advantagesthat will be discussed shortly.Assume that on the first sweep of the CRT beam,the ROM is being addressed by the six registeroutputs representing characters N I, N 2 , N 3 , etc.The first horizontal, 5-dot line of each character inthe display row are displayed in sequence. Thenthe line address inputs to the ROM from the controllogic change to their second state at the timethat NI has completed its recirculation to the Nregister's outputs. Thus, on the second CRTsweep, the second series of 5-dot lines are dis·played horizontally for all N characters. At theend of seven recirculations, the complete row of Ncharacters is on the display.Now, the contents of the N register are not reoturned to the input of the N register. Instead, theyare fed back to the input of the M·N register andthis register is clocked to load the N register withthe second group of N characters. The M·N registeris then held still while the N register recirculatesseven times to generate the second row of characterson the display. After all M characters are onthe display, the first group of N characters isreloaded into the N register and the entire processis repeated to refresh the display.Human factors-chiefly the eye's response timedictatethat the display be refreshed at least 30 to35 times a second for good legibility. Most de·signers prefer to refresh at 60 Hz power line fre·quency because it is generally the most convenientfrequency.Besides generating the line address inputs (that is,the number of recirculations of the N register), thecontrol logic keeps track of the number of dotsand spaces in he output bit stream. The spacesbetween characters in a display row are inserted as"0" bits when the ROM outputs are serialized bythe TTL register. The counters also control theloading and recirculations of the MaS registers inthe refresh memory subsystem.A multiple row raster scan display could be gen·erated with the M-Ioop technique in Figure 5 but,the implementation is difficult and impractical.This technique is more appropriate for single rowdisplays. Using this method of display, all M char·acters to be displayed. must recirculate seven times»zI~o-t':j'CDCJ)

......en...ocaQ)c:Q)~...Q)....CJ...caca.r:.Ug.r:.CJcao...Q.Q.«enEQ)....en>UJQ).r:.I-oqoIZ«to generate a 5 x 7 horizontal scan, so all stages ofthe registers must operate at the full characterrate. To form several rows with a single·loopmemory requires an interlaced scan rather than anordinary raster scan. The first series of 5·dot linesare generated by the first N character outputs asbefore, but the next set of N inputs to the ROMwill generate the first group of 5-dot lines in thesecond row of characters on the display. Therefore,the beam must jump to the new line position.To display four rows of 5 x 7 characters, forinstance, would requ ire a staircase generator thatwould step the beam by the height of nine scanlines (seven dot lines, plus two blank spacing linesbetween rows) three times after the initial scan.Then, as the second of the seven recirculationsbegins, the beam would have to be shifted anadditional line to start the second series of linescans-and so forth.The M-N-N technique does not require any moreregister stages than the M-Ioop technique andsignificantly reduces control and drive circuitrequirements-again producing a lower cost perfunction.REFRESH MEMORY MODULATIONThe technique employed in the M-N-N refreshmemory is called "clock modulation". In otherapplications, it has already been found to significantlyreduce total storage costs. 3 It helps minimizepower dissipation-in most terminals, theamount of power consumed is unimportant initself since line power is used, but registers arepowered by clock drivers and the cost and complexityof the drive network is certainly important.Furthermore, the technique allows long, veryhigh-density MaS circuits, produced by relativelyinexpensive low threshold (bipolar compatible)processes to operate at very high effective characterrates.As shown in Figure 7, the raster scan system usesnine clock intervals to generate a row of characterson the display. Seven are for the high-speed recirculations.During the other two intervals, thefirst N characters are fed back from the output ofthe N register to the input of the M-N registerwhile the N register is loaded from the M-N registerwith a new row's worth of characters. Sincetwo intervals are used for this operation, the registersoperate at only half the character rate. Therest of the time, the M-N register is chargequiescent.Its average clock frequency is onlyabout 11 % of the character rate.In other words, most of the refresh memory(perhaps 90% in a large display system) operates atonly half the character rate (say 1 MHz instead of2 MHz) only two-ninths of the time. The savings inthe drive network alone can be judged from thepower-frequency plot for a typical MOS dynamicregister (Figure 8)3. In addition, the designer canincrease the number of characters generated perrefresh cycle, for a larger display, or increase thenumber of dot lines, for a larger font, or both.Remember, though, that dynamic registers mustbe clocked to retain data. How long can the M-Nregister be turned off? Long enough for practicalapplications. The guaranteed minimum frequencyis temperature dependent, since temperatureaffects charge-storage time. The minimum forNational Semiconductor's MM-series registers is500 Hz at 25°e, rising to 3 kHz at 70 0 e (maximumoperating temperature is 125°e, but that isnot a display environment). At room temperature,EizC>E 0.010iiica: 0.00 I~10=TA'" 25°C-v DD" -tOVI-V q.,=-15V0.000 I10 100 1.000MAXIMUM OPERATING FREQUENCY (KHz)Figure 8. Power vs Frequency Plot of Typical MOSDynamic Registerthe registers can safely be quiescent for as long as2 msec. (The typical MM register will actually holddata for 10 msec.) Suppose the N register stores 40characters and operates at 2 MHz. The quiescentperiod can be as short as 40 x 7 x 0.5 = 140 /lS. Ifstandard TV raster timing is maintained then thequiescent period will be 7 x 63 /lS = 441 /lS.Obviously, the designer has great leeway in characterrates, operating temperatures, and registercapacities.Other applications in displays for clock modulationinclude input-output buffering of data duringdata reception and transmission,2 or during displayediting and formatting through the consolekeyboard. The register rates can be adjusted viacontrol logic to accommodate differences betweenI/O and recirculation rates .. Note that the gating inFigure 7 permits data entry under TTL controlinto either register section.CHARACTER GENERATIONThe first generally available MaS character generatorswere kits such as those in Figure 2, usingthree 1024-bit ROMs (MM521). Although singlechipgenerators were being developed in 1969,they were in very short supply. The kits cost abouthalf as much as diode generators and thus allowedterminal manufacturers to start the changeover toMOS.The kits are also a good place to begin describingcharacter generator operation in this applicationnote, because they provide an "exploded view" ofmulti-ROM generator operation. Similar techniqueswill be needed to build larger fonts with the234

new devices. The external gating functions shownin Figure 2 are not needed for these fonts whenthe MM5240 and MM5241 are used. The "assem·bly" of the dot patterns is taken care of in theprogramming of the ROMs. However, to generate alarge font, such as 8 x 10 or 12 x 16, with the newROMs will require operation of two to four ROMs.Each MM521 in the SK0001 raster scan kit canstore 2564-bit dot patterns. As the inset letter"N" in Figure 2a indicates, the MK001 ROMstores the first four 4-dot line segments of each ofthe 5 x 7 characters, the M K002 stores 4-bitsegments of the other three-dot lines, and M K003suppl ies the fifth bit of each of the seven-dot lines.All ROMs are addressed simultaneously.The 6-bit ASCII code was devised to select 64 (2 6 )characters. However, an 8-bit address is used toselect the dot lines and the 6-bit ASCII code fromthe 256 (2 8 ) word locations in each ROM. Thesetwo additional bits Clre supplied by the A and Boutputs of a TTL binary counterDM8533 (SN7493) and the counter's C output isused to commutate the MK001 and MK002. TheROMs are enabled by an output at the TTL logical"0" level. Thus, with the gating shown, theMK001 is enabled during the first four of sevenline-rate clock inputs and the MK002 during theremaining three inputs.The MK003 is continuously enabled by groundingthe chip-enabled pin, CEo It must generate a 1-bitoutput for each of the 7 x 64 dot lines in the64-character set, which implies a 9-bit address.Rather than produce a special ROM just for thisfunction-which would make it expensive-theMM521 was programmed to generate 2562-bitoutputs from the 8-bit address. The counter's Coutput simply gates out the unwanted bit.For a 5 x 7 font, the new single-chip charactergenerators are simply programmed to generate all5 bits in each dot line, from a 9-bit address. Standardprogramming provides the 64-characterASCII set, but special characters can be substitutedby changing the stored dot patterns. Thereprogramming process consists of altering anetching mask that controls gate insultation thicknessin the MaS field effect transistors of thestorage array. If the oxide is left thick, the transistorwill not switch when selected by the decodinglogic, generating a "0" output from that location.Figure 9 indicates why the storage capacity of theMM5240 is 5 x 8 x 64 rather than 5 x 7 x 64-eachROM can generate half of the 8 x 10 x 64 characterset. The ROMs can be addressed simultaneously,as before, and be com mutated by thecontrol logic to put out the 8-dot horizontal linesin the correct sequence. For very high speed charactergeneration, the addressing of the ROMs canbe skewed or overlapped so that the outputs fromone are generated while the inputs to the other arebeing decoded. The only real limitations to thecharacter generation rates achievable with suchtechniques are the speed of the bit serializing logicand the bandwidth of the video circuitry.• •:. : MM524t-l-·J .. -I-~• •• MMS241; .; 150 8)8 x 10 RASTER SCAN CHARACTER.......I• I •MMSZ41 i I : MM5241(8x6):: ~.6)______ ".J!!"!!".!!. ____ _·. , .••• ¥ •••MM5Z41 I: MM524118x6). : (BII6)16 II 12 VERTICAL SCANFigure 9. Multiple ROM Character FontsCONTROL LOGICStarting with the dot/character or dot and spacecounter in Figure 7, the counter moduli are set toaccomplish the following functions:• The dot and space counter determines the numberof horizontal spacing bits between char- .acters in the character row on the display. Itsoutput is loaded into the parallel inputs of theDM8590 serial-in/parallel-out shift register. Fora 5 x 7 font, for example, a modulus of sixinserts one spacing bit (logical "0" bit) betweeneach 5-dot group in the serialized stream.During line recirculation periods, this counteralso drives the N counter at the character sh iftrate of the N register.• The N counter causes the line select counter tochange state at the end of every recirculation ofthe row data in the N register. It generates apulse at intervals of 6N dot clock periods(assuming one spacing bit).• The line select counter generates seven sets ofthe three address bits that sequence dot-lineselection from the ROM.• A character line counter is needed in someraster-scan displays to keep track of which pageline has just been generated. This time is signifiedby the C or D output of the line selectcounter.Outputs of the first three counters actuate theregister clock drivers, keeping the line select bits insynch with the data code. If the line select counteris a 4-bit binary device, eight states are available onthe ABC outputs (000 through 111). The D outputcan be used to provide a ninth state and thereset function. Only seven states are needed forline select, so the eighth and ninth states providethe interval needed for loading the N register fromthe M-N register, as previously described.»zt~o-t'::rCDen

...... oca...U)CDc::CD~...CD...()...caca.t:.CJo ....t:.()cao...c.c.«U)ECD...U)>enCD.t:.~o~IZ«VERTICAL SCANNERS AND PRINTERSVertical scan character generators are generallyused in hard copy applications. Also, a verticalscan type of character generator can sometimes bemore suitable for CRT displays than raster scan.Displays or printouts of calculators and smallbusiness machines often show only numerals and alimited variety of symbols-not enough for a fullalphanumeric generator. Such fonts are easilyprogrammed into a small ROM such as the1024-bit MM522, which stores 128 8-bit words.There's room for 16-5 x 7 dot characters on thechip .These ROMs are also used in the SK0002 kit for a64-character ASCII-addressed font (Figures 2b and3b), which requires the storage of 3207-dotcolumns and a 7-bit address. Connected as shown,the DM8533 TTL binary counter will reset on thecount of 16. And with the gating and interconnectionsshown, the column select cycle is:Counter Outputs DCBDCB000001010011100101ROMs EnabledMK004MK005MK004MK005MK006reset (instantaneous)A CRT beam can be intensity modulated by theserialized output, as in the raster scan technique.However, the electron beam traces either a sawtoothor pedestal-type scan pattern on the screen(Figure 10). Every column of each character in thedisplay line is scanned in sequence, starting at theleft-hand side of the screen.The sawtooth scan is straightforward, but thepedestal scan requires that the bit order be reversedin the second and fourth columns. To dothis, the outputs of the M K005 ROM are simplyconnected to the output buses in the reverse order(i.e., output 1 to bus 7, output 2 to bus 6, etc.) .SAW TOOTH DISPLAYPEDESTAL DISPLAY~., I A • ----, .. ., t"' ,-----,f f:. ". • : I " : I,A)II.6l/ I • '.",: 1'llll'ill?j" I 1'1 I :.1:1/ 1;:. :: T I : I I.il II 1/ :. : : ,,:: :..... ,,' II', ~ .' I : I...L. : I..,., II II " ., I I I • I I• I , r • L .... L_J I~ ~Figure lOa. Two Techniques for Vertical ScanNEXTCHARACTERFigure lOb. Example of Character Generation UsingPedestal·type Scan.Long shift registers, operating at relatively slowrates can be used. The character rate-the registershift rate-is no more than 1/6 of the columnselectrate for a 5 x 7 font, since the beam tracesone complete character before going on the nextone. A dot counter loads spacing bits betweencharacters via the TTL shift register, a charactercounter triggers the sawtooth or pedestal scanningpatterns, and a row counter would control positioningof the beam in a page display system.I n the new single ROM (MM5241) version of thissystem, (Figure 11), a 9-bit address is needed,6 bits for the ASCII code and 3 bits for dot col-CHARACTERGENERATORZ AXISMOD.INPUTCHARACTERDATAPARALLelENABLEFigure 11. Vertical Scan Display System

l>ZI~oCHARACTER {DATA'-------It~~~~~~~==~===L--Jumn select, Since the ROM stores five dot columnsfor each of 64 characters in a 5 x 7 font, 3 decodeline are necessary. Also, the ROMs are programmeddifferently for sawtooth or pedestalscanning. Because the output pins are committedfor all columns, external connections cannotsimply be used to reverse output bit order.Hard-copy printers can use the same fonts asvertical scan CRT displays. MaS registers may beused for data input buffering, but of course refreshregisters are not generally required. The charactergenerator output may be used to select some combinationof 35 hammers, needles or electrodes thatprint the 5 x 7 dot patterns on the paper. Onetechnique for handling the character generatoroutput is shown in Figure 12.In Figure 12, a TTL counter connected to divideby six (five columns and the blank column spacebetween characters) generates the column selectaddress. The ROM's outputs are accumulated inTTL latches (or held in TTL serial-in/parallel-outshift registers). When all dots for a character areready, they are printed. In tape printing applicationsin which a 7-transducer array sequentiallyprints or punches a column at a time as the papermoves under the transducers, the ROM outputscan be used as they are generated unless storage isrequired for some other purpose.Character generators are not needed for conventionalelectromechanical typewriters. But MaSROMs do have a role here-one version of theMM521, for example, is programmed to convertthe ASCII communications code into the Selectriccode used to control ball-type printers.PRINTING APPLICATIONSThe application of character generators in aprinting application is normally quite differentfrom that of the display system. Most printersrequire that a total character font be availablebefore the print is executed. An example of apractical method of accomplishing this (Figure 12)is to sequence the character generator elementthrough the fOllt sequence. Each of the characterFigure 12. Printer Application Block Diagramcolumns or rows is addressed. The character generatoroutput data at each of these address intervalsis transferred into bipolar memory. Thismemory not only satisfies the memory storage butalso the general power buffer which is requiredbetween the MaS character generator and theelectromechanical on thermo electric printer. Inthe printer application there may be a requirementto buffer the input data with data storage becauseof the relative differences in data and printer ratesbut generally there is no need to retain the printedcharacter intell igence.The data transfer from the character generator tothe bipolar memory in Figure 12 is accomplishedby sequencing the column address lines and enablingthe appropriate memory simultaneously.Each pair of DM8550s (SN7475s) then containsthe data for one of the five columns in a character.The DM8842 (SN7442)-one in 10 decoder providesthe decoding functions which are connectedto the enable line on the quad latches.LARGER, FASTER SYSTEMSMost low cost terminal designs have been based dnthe 5 x 7 font because of the high cost of diodematrixes and wideband video circuits. But it is byno means the most legible font. A 5 x 7 font isacceptable for applications in which the displaychanges slowly, but human engineering studiesindicate that it causes severe eyestrain when anoperator reads rapidly changing data.The greatest portion of the discussion has dealtwith a 5 x 7 font. A full 64 character display canbe coded into a single MaS package. Now that LSIhas entered the scene, we see a different trendtowards larger, more stylized font. The economyof MaS ROMs will provide the customer with amore legible character font at the present cost of"discrete" character generators. An analysis of themost practical solutions to various fonts are tabulatedin Table 2. The part types which have beenused to generate a 64 x 7 x 5 raster scan font arethe SKOOOl-3 ROM kit or the MM5240 which isunder development. The vertical scan font is satisfiedby the SK0002-3 ROM bit or the MM5241l>"C"C...oD)n~r+oo~D)...D)nr+CD...C)CD::lCD....D)r+o...U)237

fo....ca ...CDCCDC!J...CD...Co)...caca~(.)s~Co)caec.c.c:(enE! en>enCD~I-o~IZc:(which is under development. If we examine theother possible fonts, these same two monolithicelements will satisfy the requirements if they were64 x a x 5 and 64 x 6 x a respectively. Therefore,the added memory storage is being incorporatedinto the MM5240 and MM5241. In some of thesecases the font is scanned in the horizontal dimensionwhile in others the font is scanned in thevertical dimension. You find both the a x 5 and6 x a elements capabie of satisfying the fontmatrix requirement. Since all the ROMs listed arestatic by design, there are no special clocking hard·ships induced with the solution of any of theselarger fonts. This is not true for all dynamic ROMsolutions.As mentioned before and shown in the table, thesame ROM element is used in both raster scan orvertical scan applications. If we recall the designsolutions showing the refresh memory and charactergenerator for a 5 x 7 display, the first thingwhich is apparent is that the sequencing of thecharacter generator is different in each of the twobasic techniques. In one case the character genera·tor is sequenced at the character rate (raster scan)while in the other case the generator element issequenced at the column rate (vertical scan) of thefont.Since a display utilizing the vertical scan techniqueshas input address changes at some multipleof the display character rate, a clocking system fora dynamic ROM character generator must besupplied. This requires the addition of a frequencydivider and clock generator which results in ahigher system cost when dynamic ROMs are used.A second consideration which should not be overlookedin systems cost is the compatibility ofROMs in mUlti-package character fonts. OptimumROM usage and organization will result in lowersystems cost. ROMs will also find applications inmicro-programming and code conversion wheresynchronous operation is preferred.The a x 10 font is much better and 12 x 16 isalmost optimum for legibility. Small, lower casecharacters can be sharply defined, too, and theyalmost appear to be drawn with continuousstrokes.System designers considering these fonts for lowcostdisplays run, at present, into CRT cost problems.The least expensive displays are televisiontypeCRTs with limited video bandwidth. Bandwidthalso limits the number of characters that canbe displayed simultaneously. Not counting thetimes required for beam retrace and functionsother than character generation, which reduce thetime available in a refresh cycle for dot handling,the necessary bandwidth is roughly:BW = (dots and spacing bits per character)X (characters per display row or page)X (refresh rate)TV·type CRTs have a maximum bandwidth ofabout 4 MHz, of which only about 2.5 MHz isgenerally useful. If one uses a 5 x 7 font with onespacing bit (6 x 7 total) at a 60-Hz refresh rate,each displayed character needs 2.52 kHz of bandwidth,so the limit is about 1,000 characters. Incontrast, the new ROMs take as little as 700 nano·seconds to generate a dot line, or about 5 fJ.S percharacter. That's fast enough to generate 200,000characters a second, or a display of more than3,000 characters at the 60-Hz refresh rate. Theactual dot rate in the serial bit stream to the CRTcan approach 10 MHz. And if larger fonts aregenerated in some multiplexed addressing mode,the required bandwidth can be much higher.Luckily, these problems are not insurmountableand there are alternatives to using oscilloscopequalityCRTs or storage tubes, which are fine forhigh performance applications but too rich forlow cost terminals.Obviously, the designer can drop the refresh rates.New CRTs with longer persistence phosphorsfacilitate this. Also, CRT manufacturers have beenresponding to the new terminal market by workingon bandwidth improvements, and they are appar·ently going to reach 10 MHz in moderately pricedvideo systems soon.Finally, the designer is not obligeq to display hischaracters digitally just because he uses a MaSROM. Don't forget that the ROM is really workingas a code converter, generating a 35-bit machinelanguage code from a communications code. Thelanguage translation can be whatever the situationrequires.All 'that need be done is update methods used inanalog displays, wh ich form characters withstrokes rather than dot lines or columns. TheROMs can be programmed such that the bit outputs,when integrated, control X and Y rampgenerators. The slopes of the ramp functions aredetermined by the number of bits in a sequenceand the lengths are determined by the locationschosen for turn-off bits. As in the vertical scantechnique, the ROM is addressed at the characterrate.Even though some characters can be formed withone or two strokes (I, L, etc.),.equal time shouldbe given to all characters in a page display to keepthe character rows aligned. A standard sized areaof the MOSFET array, such as 6 x a or 5 x ashould be used for each character. Most patternswould thus be a combination of stroke and nostrokeoutputs. The single-chip fonts have ana-stroke capacity for each of 64 characters whichis more legible than the standard segmented typeof instrument readout, since slant lines could begenerated wherever needed.238

APPENDIXI~oWHAT ABOUT INSTRUMENTSAND CONTROLS?While it is safe to predict that 1970 will be "theyear of the MOS" in alphanumeric terminals, MOSapplications in numeric readouts are just beginningto emerge.A new device with considerable promise in thisfield is a high voltage, MOS static shift register, theMM5081. Developed by National, it has a TTLcompatibleserial input, 10 parallel outputs thatcan stand off -55V, 10 latching-type storagestages, and a serial output.This novel combination of functions means thatthe MM5081 can drive lamps, numeric indicatortubes, filament tubes in segmented number andsymbols displays, electroluminescent panels, andthe new gas-cell arrays. In short, it provides MOSwith a good foothold on the numeric side of thereadout family tree in Figure 1.The register stages can either shift the bits to theserial output for recirculation or store the dataindefinitely. Hence, displayed characters can beswept along a line of indicators, "frozen" on astationary display, or made to reappear periodicallyat any desired repetition rate.A code-converting/character-generating ROM canbe placed at the register input, to display numbersand symbols or alphanumerics. A designer can getalmost as much flexibility from a lamp or paneldisplay as from a CRT display. In fact, the firstapplication of the MM5081 is controlling a matrixof neon lamps in a moving billboard display.Some applications for character generators in instrumentsare also cropping up. Displaying rangescales on an oscilloscope is a good idea that can beimproved upon with the new ROMs_ The displayfrees the operator of the chores of mentally calculatingscale factors and manually writing these onscope photos. With an alphanumeric font, thecamera can also record information such as testconditions, date and time of test, identificationnumbers, etc_ Photo sequences and the dataneeded to analyze the curves can be coordinatedautomatically.Similarly, a ROM can be programmed to displaystandard curves for go-no-go equipment checkoutoperations_ For example, if a radar's pulse amplifiershould have certain output characteristics, theROM generates the correct output curves througha digital-to-analog converter and stroke generator.When an actual operating characteristic and thereference curve are displayed simultaneously, theoperator can tell at a glance whether the radar isfunctioning properly. Many curves or general purposecurve segments can be programmed into aROM and picked out as needed with selectorswitches or a ROM microprogram mer.ROMs can be programmed as lookup tables,random-logic synthesizers,4 encoders, decoders,and microprogrammers as well as character generators.A single ROM can perform limited combinationsof these functions, virtually qualifying it as amicrocomputer. It has been suggested that thiscapability be used in control panels to performfunctions like actuating an alarm when a transducerlevel goes out of range and initiating correctiveaction. ROM addresses can be derived fromdigital meter circuitry. In mUlti-point measuringsystems, this would provide the solid state equivalentof a rack of meter relays.DEFINITIONS OF DISPLAY TERMSFont: A set of printing or display characters of aparticular style and size. A typical dot-characterfont is 5 x 7, referring to the number of dot locationsper character.Dot Character: A character formed by a pattern ofbright dots on a CRT screen or dark spots on hardcopy, rather than by continuous strokes. The dotpattern corresponds to bit-storage patterns in adigital memory.Column: In a dot character matrix for verticalscanning, a column is a vertical series of dots_ On apage display, a column contains several verticallyaligned characters. In this article, a column refersto a dot column.Row: A horizontally aligned group of characterson a display.Line: In this report, line refers to the number ofdots displayed in a single scan when a raster scancharacter is generated. In a 5 x 7 dot character,there are seven lines of 5 dots each.Page: A display consisting of several rows of characters,corresponding to lines on a printed page.Raster Scan: See Figure 9.Vertical Scan: Two types of CRT vertical scans areshown in Figure 10. In hard copy applications, thedots in a column or character may be printedsimultaneously by the printing transducers ratherthan being scanned.Sawtooth Scan: See Figure 10,Pedestal Scan: See Figure 10.Dynamic Element: A digital device that must beclocked. A dynamic shift register must be clockedto retain data. A dynamic ROM is clocked todecode the address and generate an output.Static Element: A device that does not have to beclocked to retain data. A static ROM uses directcoupled decoding for bit selection and static outputbuffers.239

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Application NotesMAY 1971HIGH VOLTAGE SHIFT REGISTERSMOVE DISPLAYSThere was a time when one had to go to TimesSquare or Picadilly Circus to see a moving lampdisplay. But now they're going into stadium score·boards, stock brokers' offices, waiting rooms andmany other places where an attention· getting manmachineinterface is wanted.Naturally, display designers would like to makethe control and drive circuitry more compact andless expensive. What's needed to replace the banksof discrete switching devices is storage and switchinghigh-voltage circuits in monolithic form. That'sexactly why National developed the MM5081 highvoltageMOS shift register.This unusual IC is the first MOS device capable ofdriving gas-discharge tubes and other high-voltagedisplay elements without going through a bipolarbuffer such as a transistor or SCR. Moreover, it can"walk" the message around and around the displaywhen operated in a recirculating mode. Thelatter feature provides a clear-cut division betweensystem functions - the MM5081's take on the responsibilityof display operation per se, while thesystem logic need only format messages and controlupdating by invading the registers. In otherwords, the main system logic need pay only intermittentattention to display operation. If the mainsystem is a data-processing computer, for instance,it can handle the display like any other peripheral.Relieved of responsibilities for moving and refreshingthe display, the main system can do more dataprocessing between display updates.REGISTER PLUS SWITCHESFigure 1 shows in simplified form how oneMM5081 would be connected to drive a bank of10 neon lamps. A data bit stream is entered intothe serial input and shifted at the clock rate to theserial output. Then, it can be routed back to theinput and recirculated to repeat the display motion.The states of the data bits circulating through theregister control the switching of the MOS outputtransistors. When a bit in the true state (MOSlogical "1 ") is being stepped down the 1 0 registerstages, the lamps will turn on and off in sequenceat the register clock rate. In this mode, the clockrate is the display rate. A typical display rate willmove the light along by no more than two orthree lamps per second, making any message displayedon parallel rows of lamps easy to follow andread. A latch-type register cell that can sh ift at frequenciesto DC and a single-phase clock input areused in the MM5081 to achieve this effect. However,the logic formatting the data for display willhave to run at some higher rate. If the controlsystem has other functions as well, it may bedesirable to load the register at a clock rate in thehundreds of kilohertz. At such a high rate, thebit stream flashes by the 10 parallel outputswitches too rapidly to see the lamps being turnedon. After loading, when the main system logic isfreed, the clock rate is dropped to the displayrate and the message is seen. The message simplyrecirculates at the display rate until new data isready for loading.3:o

n>coQ.rnCQ)>o~rn ...Q)1;)C)Q)a:........oJ:(/')...Q)C)COo>oJ:C):x:The use of high-speed logic for control is facilitatedby making the MM5081 with low-threshold,p-channel, enhancement-mode MOS transistors. Asa rule, a low threshold device allows data to beentered at bipolar logic levels.The output transistors do not need a large gate·voltage change to turn on and off. They are alsolow-threshold devices in this sense. But they haveto withstand transients up to 100 volts and standoff steady state voltages up to 55V to operatelamp-type displays reliably. Adequate gate logicvoltages for the output transistors must be ensuredto make the lamps glow brightly when they shouldbe on or to make them free of any residual glowdue to switch leakage when the switching transistorsare turned off. That is, a low RON and highROFF must be ensured despite very high voltageon the MOSFET drains. Because a pullup resistoris used, the input gate should be a TTL or DTLdevice with an uncommitted-collector output ableto withstand at least 1 OV. Among such devices arethe DM881 0, DM8811 or DM7426 (SN7426) quadNOR.gates, or the DM8812 hex inverter. All theseTTL devices will stand off to 14V.The other two gates used in the input switch canbe any TTL or DTL types. The arrangement shownbrings the serial output back to the serial inputthrough the top gate when the "new data enable"line is low (DTL/TTL logical "0") or permits theregisters to be reloaded with new data when theenable line is high. A pull-down resistor is placedon the register output to handle 1.6 mA the currentsinking required for operation of the TTL orDTL recirculation control gate.TICKER-TAPE DISPLAYA straightforward type of moving lamp display isillustrated in Figures 2 and 3. Simple messages suchas CALLING DR. CASEY ... CALLING DR.CASEY ... DR. CASEY, PLEASE REPORT TOSURGERY ... or stock quotes, or a series ofinstrument readings would be displayed as 7X5characters by this system. That is, each characterwould be a lighted lamp pattern selected from amoving matrix seven lamps high by five lampswith a moving column of lamps turned off betweencharacters. The off column is a space bit in eachlamp row.Assume that the display is long enough for 33characters. Each row requires 33X6 lamps and198 register stages. Each row is a cascade of 20MM5081's. The input of the first register and theOATA INROW7FIGURE 2. 7XN Bit Shift Register and Display242

output of the last register are connected as inFigure 1, and the registers in between are simplydaisy-chained by connecting each serial output tothe next serial input. All seven rows would use140 register packages.The character data for this type of system can beformatted by a standard character generator. Forinstance, the standard ASCII code can address abipolar compatible read-only memory such asNational's MM5241AA, which is programmed togenerate 5X7 dot-type characters for CRT display.However, in the lamp display system, the displayrefresh function is handled without an additionalmemory. The column bits are entered in eachregister chain, as before, through the input gatingat a rate determined by the clock rate suppliedthe MH0025C clock driver. The MH0025C is atwo-phase driver. However, since the MM5081takes a single-phase clock input (converted to atwo-phase clock inside the register package), onlyone of the dual drivers in the MH0025C packageis shown (the other half can be used to share theclock-drive load).After the registers are loaded, the clock into thedriver is dropped to a frequency of 2 Hz, if theregister was loaded at a higher frequency. This rateis stabilized by the coupling capacitor Ce. Thecoupling capacitor on this type of driver determinesthe maximum pulse width, but the minimumpulse width is established by the clocksignal. So, at the lower frequency, the characterssweep smoothly from right to left across the displaylamps. They repeat the message every 100seconds because 200 register stages are in each ofthe seven parallel rows.Both the clock driver and the registers operate offthe 10V and -6V power supplied.1 5DHz 1... --, r--1 r---125 L..J L.JON OffNEW DATAINPUTswitch. The purpose is to limit the current andvoltage across the lamps and the MaS output transistorsto ensure that they operate reliably andhave long lives. Also, the method reduces powerconsumption and allows lower power, inexpensivehigh-voltage power supplies to be used.The high-voltage switch seen in Figure 3 anddetailed in Figure 4 switches at a rate of 50 Hz anda duty cycle of 25%. Thus, when any of the MaSoutput transistors is on, the lamp that is "on"during that 250 msec display-rate interval (1 00%duty cycle at 2 Hz) is actually on for only 5 msecat a time. Then it turns off for 15 msec. This refreshrate was chosen because it provides a goodlamp intensity with no apparent flicker.-.. "6'L--'\"""_ ....._ .....()_12••FIGURE 4. High Voltage SwitchThe -125V supply turns on the lamps, and the-45V supply turns them off. But what is actuallybeing used is the voltage difference, or bias. Mostglow-discharge lamps require a 65V starting voltageand a 60V holding voltage. The switch keeps thelamps alternating between these levels while theMaS transistors are on, but imposes a maximumvoltage of only -65V on the MaS transistors (thatis, 125-60V) for the 5 msec "on" time. TheMM5081 can easily take this - the spec allows-100V at 60 Hz (or 16.66 msec) and they arestress-tested to this level.INDUSTRIAL DISPLAYS3:o

en>caC.enCC!)>o~en""" C!)tienC!)a:There are many potential new applications formoving-lamp displays in industrial control systems_Functions such as process flow rates throughseveral feeder pipelines or subassembly line ratein an assembly plant, cannot easily be set up on aCRT display_ Complex computer graphic techniquesor very expensive mUlti-gun displays maybe needed.The clock rates and lengths of a number of rowsof lamps can readily be adjusted by hand-operatedcontrols, such as voltage-controlled oscillators andgating between registers chosen by selector switches.Any feeder-line display rate that can be representedby the display rate could therefore be variedat a compressed scale of time and distance until thedisplay operator arrived at the optimum balanceof rates. This is a visual approach to a problem thatgenerally requires complex mathematics and analogcomputers to solve.Nor do the rows of lamps have to be aligned.Individual rows might represent route sections ina transportation network between junctions. Bydriving each section at a display rate simulatingthe speed of a particular train, and switching the"train" of moving lights from row to row viaswitches at the junctions (serial output to serialinput register connections), control personnelcould simulate system operation. Problems suchas tie-ups - or worse - at junctions could be workedout by varying display rates for the trains whoseschedules conflicted.244

DYNAMIC MOS RANDOM ACCESSMEMORIES SYSTEM CONSIDERATIONSABSTRACTA new TRI-STATETM common I/O configuration,capable of precharge decoding without losing systemperformance and bipolar compatibility, isemployed in a 1024-bit MOS RAM. In combination,the techniques reduce typical memory modulepower dissipation some 66%, number of overheadcircuits by 50%, and overhead costs by 66%without sacrificing system speed. Performance andcost of the new RAM are compared with those ofan earlier design in a similar system application.INTRODUCTIONUnlike earlier advances in MOS memories, theadvantages offered by the MM5260 MOS RAMdo not stem from a new process. I nstead, a newcombination of operating techniques is used tosolve system cost/performance problems. The techniquesare a TR I-STATE I/O structure at a commonI/O terminal, precharge decoding, and bipolarcompatibility.Memory size, cost and propagation delay of themonolithic MOS random-access device were notdecreased. These savings could have been realizedquite easily at the device level by foregoing someof the system advantages. The result at the systemlevel though is very low average power dissipation,simplified timing control, fewer and fasterinterface devices with the external system, reducedcooling requirements; elimination of high-levelApplication NotesAUGUST 1971MOS supplies, and other cost reductions. Chiefly,dissipation is reduced by 66%, overhead circuitsby 50%, and overhead cost by 66% with no lossof speed.To make these points realistic, the new design willbe compared, in a system environment, with anotherMOS RAM design with slightly faster accessand cycle times specified at the device level.MOS STORAGE DEVICEThe internal design of the new MM5260 (Figurela) is fairly standard except for its bipolarcompatibility, I/O structure, and precharge decoding.The 1024 storage cells are in a 32 x 32 array_ A10-bit address is X-V decoded on the chip toaccess a cell. In each cell, 0 1 is the storage element,O 2 a read gate, and 0 3 a write gate. An MOS "1"is stored by charging the capacitance of 0 1 and an"0" by not charging it. Read consists of sensingthe data level after an access is made.Bipolar compatibility means that all data andaddress inputs sense bipolar data levels and thatdata .is read out at the original data leVels. Thiseliminates external level translators at inputs andsense amplifiers at outputs. Previous MOS designsrequired these interface circuits in a typical memorymodule. The common I/O terminal on theMM5260 is made possible by the I/O structurel>2Ic.noc

U)c,2~tV..CD"CU)Co(JECD...U)>enU)CD''::oECD:eU)U)CD(J(Jc:(Eo"CCtVa:eno:e,~EtVC>CoU)IZc:(seen in Figure la. The I/O gating and sensing ele·ments are TRI-STATE MOS. As the name implies,each element has three operating states. Two arethe bipolar-compatible "1" and "0" states. Thethird is a high-impedance state that disables thatelement. In the third state, only a small leakagecurrent flows at no definable logic level.The third state prevents data transfer, allows oneelement to look into the other, and permits outputsof several packages to be bus-connected withno significant change in memory cycle time. Onepin serves for 1/0 because the read output bufferis in the third state when write is enabled, andvice-versa. When these outputs are bus-connected,read speed is high because the disabled elementson the bus load the enabled output very lightly.In addition, the MM5260 uses two standard supplies(+5V and -12V) instead of three high-leveland non-standard supplies (+20V, +16V and +5V).A possible additional negative supply (-5V) will berequIred for a high speed sense amp.A conventional MaS output could not share acommon terminal with an input. Separate data-inand data-out terminals may be required. Severaloutputs also may be bus-connected. However, thismultiplies the capacitive loading, causing a proportionalincrease in output transition times: Toaccommodate this, system cycle times must beincreased. For maximum speed, each conventionalMaS output should look directly into a lOW-levelsense amplifier which also has a low impedanceresistor at its input to minimize the data transfertime constant.Dynamic RAMs require some special considerations.The storage cells are dynamic, meaningthat stored charges leak from the storage transistorsand must be refreshed periodically. Eachcell must receive the refresh clock at intervals of2 ms. Refresh is applied column by column at62.5 p.s clock intervals (an access also refreshes allother cells in a column). Since accesses are madeevery 600 ns, refresh overhead is less than 1% anddoes not significantly affect system efficiency.Refresh signals are given precedence over addressesin the system control logic.The chief advantage of dynamic MaS RAMs issmall cell size, about 4 or 6 square mils, whichmakes packing density high and cost low. StaticMaS devices have latching cells that are notrefreshed but are most costly since the cell sizeis 16 to 20 square mils. Therefore, fewer bitsmay be placed within the same package. BipolarRAM cells are also large and costly, but operatein about 50 ns.Dynamic MaS RAMs fit quite well into largememories and higher system memory hierarchiessuch as fast store, virtual memory and main memory.Their low cost, high density and relatively lowpower dissipation suit them to main memory.SYSTEM ORGANIZATIONHaving ten address inputs, the MM5260 is effectivelya memory of 1024 l-bit words. Lengtheningthe bits per word merely require parallel accessof several devices, such as nine for 1024 9-bitwords. A chip-select input, enabled by decodingadditional address bits, allows expansion of wordcapacity.Figure 2 is a MM5260 module storing 4096 16-bitwords (4k x 16) in four lk x 16 submodules. One}--!+--!.L---......,..-o.., ow!-!-bL----+-.....L.._D, BUSCOUNTERIIIIPUTCOUNTERIIIPII'.MH_+---+----:,...-..--.:::oC(lNTROlMEMORYstlECTFIGURE 2. Main Memory Module Storing 4096 16-Bit Words Using MM5260246

submodule is selected at a time by two bits of theDM7442 TTL decoder address. The same decodercould access eight submodules with a 3-bit address,and so forth. This is standard decoding practice.The external data selectors (DM8123) and read/write bus buffers (DM8093 and DM8094) areTR I-STATE TTL devices. 1 These have high-speed,active-pullup outputs when enabled. The two typesof buffers can operate in parallel with the internalMOS input/output mode read/write gates. Onecontrol line gates both in complementary fashionbecause one is enabled by an "0" and the other bya "1". The data selectors hold off accesses duringa submodule's refresh intervals. Figure 3 is theTTL clock forming and timing control circuit forthe module.FIGURE 3. System Clock Timing and Control CircuitPRECHARGE DECODINGDuring standby, each MOS RAM circuit dissipatesabout 75 mW. To achieve memory access, apulse called the "precharge" is applied to set upthe decoders and other I/O functions. Prechargeminimizes system power dissipation by making itunnecessary to energize decoding logic betweenselects. During a 600 ns access, MM5260 powerdissipation goes up to 400 mW.It is important to keep as many as possible of theRAM circuits on standby to minimize systemaverage power dissipation. Excessive dissipation,without adequate cooling in a high-density system,would overheat the semiconductor junctions. Theonly ways of preventing overheating, should averagedissipation be high, are to slow down speed andlose performance, reduce packing density, or increasesystem cooling hardware. Average powersupply and clock-driving requirements are alsoreduced by precharge modulation or by reducingthe rate of precharge pulse. The added circuitryto effect power minimumization is only threeelements.Figures 2, 3 and 5 illustrate the most effective wayyet developed to decrease precharge power dissipation.This "precharge decoding" method appliesprecharge to a submodule only when that moduleDon Femling, "TRI-STATE Logic in Modular SystemOrganizations," National Semiconductor AN-43, April1971.is selected. This is implemented by having thechip-enable of the decoder gate the precharge clockvia the TR I-STATE TTL data selectors in theclock circuitry. Simultaneously, the I/O directionsare controlled. Selective precharge decoding canyield an ultimate average power dissipation of77 mW.MEMORY TIMINGThe MM5260 timing control is quite simple becauseof precharge decoding and the I/O structure.As indicated in Table 1, maximum cycle time is600 ns. A delay of 100 ns before precharge isallowed for address settling and decoder operation.This allowable delay will not affect the access timeunder worst case conditions. This element designcharacteristic permits a very straightforward selectiveprecharge decoding technique which does notaffect the performance of the memory system.Precharge goes low for 250 ns to set up thedecoders, then returns to conserve power.'""""=i x='""~ r-UABlE I lAC \ /"''"'"''~''--r-'-~O~TA""'DATAINPUTFIGURE 4. MM5260 Timing DiagramIf read is commanded, the read gates are enabledand the write gates disabled at the outputs. Storeddata is available at the output within 350 ns of thestart of the access. Write may be commanded justprior to the precharge trailing transition and iscompleted by the end of the 600 ns cycle.Address, precharge, and chip select timing is notcritical. A skew of about 50 ns between addresstiming by the CPU and leading and trailing edges ofchip-select and precharge will not affect accesstime, cycle time, or overall memory speed.DEVICE COMPARISONSThe 1103-type MOS RAM comes closest of previousMOS RAM designs to the MM5260 in performanceand organization. It is also a 1024-bitdevice with chip select and on-chip decoding of10-bit word addresses. The package has two additionalpins, one for the extra power supply andanother because data outputs and inputs areseparate.»zI(J1oc

U)co',f:to...G):2U)coCJEG)...U)>enU)G)''::::oEG)~U)U)G)(,)(,)«Eo"CCtoa:eno~(,)EtoC>Coit)IZ«r _,'".,," (INPUTlCOUNn~INPUTFIGURE 5. Main Memory Module with Conventional 1103·Type MOS RAMsTABLE 1: Comparison of Major Characteristics of MM5260 and 1103MM5260 1103Organization lk x 1 lk xlChip Select Ves VesI nput Data Levels TTL High 1+20V)Output Data Levels TTL Low 18001lA)Common 110 Bus Ves NoPower Supplies +5, -12V +20, +16. +5, -5Package Pins 16 18Access Time 350 ns 300-390 nsRead Cycle Time 450ns 540 nsWrite Cycle Time 600ns 580 nsRefresh Intervals 2ms 2msPower Dissipation During Access 400mW 300mWStandby Power 75mW 75mWTABLE 2: Components in Typical4k x 16 Memory ModuleMM5260 1103UNITS UNITSMOS RAM Packages 64 64Total for Storage 64 64Interface and Control DevicesDM8123 Quad Data Selector 2 2DM7442 BCD-to-Decimal Decoder 1 1MH0026 Clock Drivers 3MH0027 Clock Drivers 18DM74451 Power Translator 18DM8093iDM8094 Bus Buffers 10 4DM7402 Gates 2DM7400 Gates 2 2DM7404 Gates 5DM7408 Gates 1DM7420 Gates 1DM8281 Counter 1 1DM86L 76 Counter 2 2DM74L73 Flip-Flops 1 1DM9601 Monostable Multivibrator 3 4LM7524 Dual Sense Amplifiers 8Total for External Parts 26 69248

. Important differences between the MM5260 and1103 characteristics are summarized in Tables 1and 2. Their individual device costs are comparableand the 1103 appears to enjoy a performance edge(50 ns) at the device level. However, let's examinethe 1103 specifications at the system level.Major modules, though not submodules, are almostinterchangeable. As proof, compare the typical1103 4k x 16 module in Figure 5 with Figure 2.Both are very similar conceptually.MODULE COMPARISONPower DissipationOne significant difference is in the power requirements.The 1103 uses two high-level supplies anddissipates about three times as much power asthe MM5260 module. Total dissipation in the MOSRAMs and by the circuitry outside the RAMs inFigure 5 is around 30W, while that of the MM5260module is about lOW. As a benchmark, core memorieswith the same capacity dissipate about 25W.Clearly, the MM5260 has the advantage. The powerdissipation factors are standby power-the same75 mW for both device-precharge dissipation,and external dissipation.A quick calculation shows that the MM5260 hasprecharge dissipation in only 16 out of 64 devices,due to precharge decoding. With standby dissipationin the other 48, total memory dissipation isabout lOW. Dissipation in the logic devices is notlarge in either device.Precharge dissipation in the 1103 is 300 mW,100 mW less when it is accessed at a 600 ns rate.PRECHAIIGEV .. ~• 1'-+:--+---'11------,,,------1IrFIGURE 6. Timing Diagram of 1103-Type RAMPrecharge is used to reduce access time as well asaverage dissipation in the 1103, which compromisesprecharge power savings. Using precharge tosave time precludes precharge decoding. Figure 6,the 1103 timing diagram, shows that prechargesets up the decoders to receive the addresses.Therefore, it must be applied to all 64 RAM circuitssince the chip-enable portion of the addressis not decoded until after precharge begins. Afterchip-enable decodirig, precharge may be turnedoff for the unselected submodules. By then, these49 circuits will have been precharged for some100 ns, consuming an extra six watts.A total of about 14W are dissipated in prechargeand standby power in the 1103 memory module.In other words, the MM5260 memory solutionhas already saved 30%.The extra amplifying devices account for the restof the increase. Address, chip-enable and data inputsmust be pulled up to +16V. These leveltranslators must drive heavy capacitive loads. Forexample, each address input capacitance is 7 pF,a total of 450 pF for 64 in parallel. To avoidmaking input delays very long, high-power transistordrivers must be used. The low-level outputsmust be detected with sense amplifiers to drivelogic in the processor. Fufthermore, the highlevelsupplies increase dissipation elsewhere in thesystem and add to the system cost since they arenonstandard.Timing TradeoffsNext, is the question of access and cycle times.The access time of the 1103 is 300 ns if the prechargetime can be anticipated. If address andprecharge occur together, access time is 310 ns.Access time also depends upon the leading edge ofchip-enable. The read and write slots are alsoquite critical.Extra timing control circuits are needed. Conservativedesign must take into account Murphy's Law("if anything can go wrong, it will") in moduleand address tim ing.Good bipolar drivers at the inputs, such as a monolithictranslator like the MH0027 or three transistorsand several resistors in each, will hold theinput delays to 40 to 60 ns. These add to the memorysystem cost. A low-cost alternative, opencollectorTTL devices with passive pullup, wouldstretch input delay to about 225 ns (due to theRC time constant of a 450 pF load and 500npullup resistor). Furthermore, these passive pullupdevices would about double power dissipationagain. The delays in the sense amplifiers are approximately30 to 40 ns. Good sense amplifiers areessential to achieve a short read time and becausethe MOS outputs are wired-OR'ed. (64 rather than16 sense amps aren't practicaL) As mentionedbefore, wire-OR'ing also delays output transitions.Most of the high speed sense amplifiers also requirean additional negative supply (about -5V).In sum, there is a minimum increase of some 70 nsin 1103 access or cycle time, and an increase up to»zI(J1oc

enCo....ca...CI):EencoUECI)....en>enenCI)'':oECI):?!enenCI)C.JC.J«Eo"'CCcaa:eno:?!C.JEcac>C1 00 ns might result in some system designs. Thiseasily offsets the access specification of 350 ns inthe MM5260. This included an output delay ofsome 40 to 50 ns in the MM5260 access andcycle times because of on chip output TTL compatiblebuffering. This delay in the TRI-STATEsense amplifier in the MOS chip was considereda worthwhile tradeoff to achieve the benefitsalready cited for the common TRI-STATE I/Otechnique.It might be noted that the TRI-STATE TTL busbuffers will drive long buses at high speed withhigh noise immunity. Therefore, the common I/Obus can extend well into the system structure.SYSTEM COST SAVINGSThe obvious savings in system costs are listed inTable 2. These consist of 17 interface and controlcircuits, 8 dual sense amplifiers, 14 resistors, anda need for only two supplies (+5, and -12) insteadof high-level supplies of (+20, +16, +5 and -5). Onecan also add proportional savings in printed-circuitboard costs, cooling hardware, assembly, componenttest, inventory control, and so forth.Effective packing density is higher, because theMM5260 has two less pins than the 1103 (obtainedby common I/O), one less supply, and less stringentcooling requirements. More RAM circuits can bepacked into the same volume; more also can beadded on bigger boards when system designerswant to increase word length or module wordcapacity. Smaller boards, of course, further reducesystem packaging costs.CONCLUSIONSSavings using the MM5260 in a typical memorysystem module are 66% less pOl/\.er dissipation,50% fewer overhead circuits, and 66% less, overheadcost. Speed performance is not curtailed and,in many applications, an improvement may beachieved.These advantages stem from a combination ofthree techniques: TRI-STATE common I/Ostructurewith an internal sense amplifier, precharge decoding,and bipolar compatibility. All are orientedtoward system advantages, rather than cost/speedimprovements at the device level.4K x 16 Memury ModuleusingMM5260oI.!')IZ«1 K Dyn.mic MOS RAMFIGURE 7. 1103-Type and MM5260 Modules. The 1103 memory module utilizes NH0026level translators in place of 36 DM74451 and NH0027 elements.250

USING THE MM5704 KEYBOARDINTERFACE IN KEYBOARD SYSTEMSINTRODUCTIONWhen one contemplates the design of an MOS-LSIchip to perform the keyboard interface function,several elements immediately stand out for consideration.Among these is the obvious problemof encoding a key closure, and whether the bitpattern produced should be presented in a parallelor serial fashion. One must also consider whathappens if more than one key is depressed, ormore than two. How fast can keys be physicallydepressed and released? One at a time, or in aseries? What is required to be compatible with thedynamic characteristics of the many differentkeyboards being manufactured? What is the bestway to match the switch closure characteristics,i.e., switch bounce, etc.? How may various keyboardcapacities best be accommodated, or whatis required to allow for expansion of keyboardcapacity? All of these considerations and morehave been answered in the design of the first MOS­LSI chip manufactured by National, the MM5704.It is called the keyboard interface (KI) chip andit is one of a total of five chips, called MAPS -Microprogrammable Arithmetic Processing System,being designed to implement all the functions requiredof bit serial calculation systems.All of these chips are unique in that they aredesigned to perform their functions in a definedsystem, hence implying a standard design. Yeteach may be as individualized and as varied as thereare ways to perform their functions. To explainhow this apparently paradoxical situation is possible,let's take an example. The keyboard interfacechip, MM5704, will accept 32 character keyclosures and provide 64, 9-bit encoded words inthe output. Each key closure will generate andoutput a code up to 9-bits long for lower or upperApplication NotesNOVEMBER 1971case depending upon the state of the shift key.Thus, a standard function is performed, that ofproviding a 9-bit pattern with each key closure.However, the bit pattern itself may be programmedaccording to the desires of the individual user. Thisability is possible because the 9-bit pattern isgenerated through the use of a read-only memory(ROM) located within the chip. The key closuremerely addresses the ROM and its output becomesthe custom encoded word.These chips are P-channel, enhancement mode,monolithic MaS devices. They are manufacturedusing silicon 1-0-0 technology which provides thelow thresholds required to interface directly withbipolar DTL or TTL integrated circuits. (Thislatter statement is true only if an output is notalso used as an input, such as the JlI bUS.) Thechips typically use +5 VDe (Vss, Pin 12) and -12VDe (V GG , Pin 24) power supplies because thisarrangement permits direct signal compatibilitywith bipolar logic systems. There is, however,nothing sacred about this power supply arrangement.It is the 17V differential across the chip thatis important, and conceivably in an all MaS systemone might have a single -17 VDe supply withrespect to ground.,A two phase clock is required to operate thisdevice. This is due to the dynamic nature of theMaS logic circuits used in its construction. Thisdevice is designed to accept clock speeds up to1 MHz.The MM5704 is packaged in a 24-pin cavity dual-inline package. The input-output pin configurationis shown in Figure 1 along with the pin configurationsof all the MAPS elements of this set.»zIC1INc:enjCO-t:::T(1)s:s:C1I....o~(1)< "C"oD)...Q.jr+(1)=.D)n(1)j(1)< "C"oD)..Q.en

enECD;>en"0~cao.c>CD~CCD(,)...ca~CD...CPinTimingKeyboardArithmetic RegisterControl&InterfaceUnit UnitROMControlChip(AU) (RU) (CRaM)(T&C)(KIIMM5700 MM5701MM5703MM5702 MM57 041 RES III ALOUf2 t/l2 CM CS3 RES 102 fE t/l2 R74 102 pi R65 101 101 CM R56 pi t/ll t/ll R47 t/ll Pl R38 Vss Vss P2 Vss R29 CM t/l2 t/ll Idle Key Reset10 TE TE Rl11 P02 t/l2 RO12 POl CM Vss Vss13 Pm! FFO t/ll14 P04 RES t/l215 pi CM16 VGG VGG VGG T417 10 T118 T219 OS T320 B+9 T521 pi22 BUSl23 A BUS224 VGG VGGFIGURE 1. MAPS Pin AssignmentsNInIZ4WHAT IT DOESIn addition to the 32 character key switch closuresthat may be encoded, there are 8 static switchesthat may be interrogated. These static switchesmay be controlled by the user to form an 8-bitword which upon command will be sent via thekeyboard interface output to· the rest of the system.These switch closures are used to performcontrol functions. They may be used to form anydesired data word especially if it is to be variedfrom time to time.The output of this device is presented at Pin 2' ina bit serial fashion. This organization was requiredto be compatible with the bus structured organizationof the five chip MAPS. The bit serial, digitserial, organization of this system was designedto keep to a minimum the number of pins requiredfor each MOS-LSI chip used in this system. Actually,Pin 2' is a bidirectional bus, with inputcapability for controlling static switch interrogation,data interrogation, or control of the alarmand shift functions. In a system this is accomplishedwith time mUltiplexing. (Figure 5)If a system contains more than 32 character keyclosures, the functions performed by the MM5704may be expanded by paralleling two or more ofthese devices. Two devices will provide 64 keyclosures ('28 data words), three provide 96, etc.The two key rollover and three key alarm functionswill continue to function by paralleling the busy'(Pin 22) and busy 2 (Pin 23) signal lines. Thealarm signal will be available at Pin , of thedevices. This signal is not OR-tieable.TWO KEY ROLLOVERIf a second key is depressed before the first keyis released, a condition exists that is defined as twokey rollover. In this situation, the device will acknowledgeand transmit the encoded word generatedby the initial key closure then acknowledgeand transmit the encoded data word generated bythe second key closure. At the time that the systemresponds to the initial key closure, the "busy'" signal line becomes true (MOS logic "'" condition).This informs any parallel keyboard interfacechips that a key closure has been detected. The"busy'" signal will remain true until the encodeddata word resulting from initial key closure hasbeen transmitted and the key released.If during the time that the "busy'" signal is trueand a second key closure is detected, the systemwill flag this condition by causing "busy 2" to gotrue. "Busy 2" will remain true until the encodeddata word generated by the initial key closure hasbeen transmitted and one key released. "Busy'"will remain true until all keys are released. A keyonce depressed and acknowledged by the systemmust be released and depressed again before it willbe accepted and acknowledged as valid by thesystem for the second time.THREE KEY ALARMIf three or more keys are depressed, a conditionexists that will be detected by the system andinterpreted as the alarm condition. Because theKI chip cannot process more than two key closures,depression of more than two must alarmthe system. When the alarm condition exists, a252

signal is generated at the alarm output (pin 1) andan alarm pulse may be transmitted .to the rest ofthe system via the data bus. The ability to signalthe alarm condition on the data bus is a programmablefeature. The signal made available atPin 1 may be used to inform the operator of theexistence of the alarm condition. The alarm conditionwill also be triggered if two or more keysare depressed simultaneously, such that the secondkey closure is detected before the first key closurecan be processed and transmitted.IDLE KEY RESET (PIN 9)An automatic reset signal is generated during theidle key mode of operation. This mode is definedas no keys depressed and power is on. The resetsignal is created by charging an external capacitor(CR) which enables the control logic to detectfirst key closure. The purpose of the reset is toprevent keyboard lock-up due to mass depressionof the keys, or any other attempt to void theintegrity of the keyboard interface chip. An exampleof this might be, depressing three or morekeys (including the clear key) to force an alarmcondition to repeat thereby voiding the keyboardlogic. When such an attempt occurs, as soon as thekeys are released and the bounce delaY'is timedout, the idle key reset enables the control logic.KEYBOARD MATRIX~,--SC_ANLOG,--I' f (~ -- ~,~."~ -~ltlIILff.-L1 LffLJ 4f1J IL _____ _The value of the reset capacitor (CR) is dependenton the keyboard scan cycle.'i . tCRV,Where: average charging current = 1 mAV1 reset voltage ~ 3.0Vt charging time intervaltE+nTWhere: E modu 10 of E cou ntern = number of scan cycles beyondbounce out delay = 2(Jf = frequency of clock (Jin.Typical values for CR, that would fit most applications,range from 0.001 J.l.F to 0.1 J.l.F.HOW IT WORKSAs may be seen by the simplified block diagram inFigure 2, the keyboard interface chip is partitionedinto three basic logic areas. These areas are theScan Logic, the ROM encoder (with its associatedinput control logic and output data converter), andthe system housekeeping logic.:______ JRLiNES.usu»2IUIN_.:lCD< "C'om..Q.CJ)

enECD....en>tJ)"C...~o.c>CD~c:CDCJ~'t:CD....c:Nit)IZc:(TO BLOCKM COUNTERThe Scan.. Logic will sequentially interrogate eachkey of the keyboard. It provides the timed interrogationpulses. The detection of a key closure isaccomplished by the ROM input control logic.This results due to the Rand B line being com-·bined in an AND condition at the input to theROM control logic. The rate at which the keyboardis scanned is basically determined by theclock input. Provision has been made internal tothis logic block to compensate for the variouscapacitive loads that different keyboards mightpresent. This is a programmed feature. The scanlogic is shown in greater detail in Figure 3. It isdesigned to sequentially scan 32 keyboard switchesin a 4 x B matrix as shown in Figure 2. The T linesenable each of the four quadrants in sequentialfashion. The B lines are then used to sequentiallydecode the B R lines at the ROM input. As theA counter changes from state N to N+1 a pro·grammable delay times out before the B counteris allowed to decode the R lines within the quad·rant. This delay is necessary to allow the T line tocharge the capacitance, associated with that quadrantof the keyboard switch matrix, to its fullvalue, and discharge the capacitance associatedwith the last quadrant to be scanned.The delay is accomplished through the use of theD counter in the following fashion: The samesignal from the B counter output that advancesthe A counter sets a latch (block flip·flop) whichin turn inhibits any further advancement of theB counter. It also sets the D counter to an initialstate from which it must advance until a signal isgenerated in its output which resets the blockflip·flop. This enables the B counter to advancethrough its cycle until its terminal state is reachedand the A counter is again advanced, at which timethe cycle is reinitiated. The degree of delay that isgenerated by the D counter is a function of theclock input to the counter and the modulus of thecounter. The modulus of the D counter may be.specified by the customer to be any value from1 to 15. Either the {} in clock or the cycle marker(CM) from the system may be used to advancethe D counter. Since both of the signals are generatedand controlled external to the device, thedelay resulting from this technique is completelyFIGURE 3. Scan Logic of MM5704adjustable over a reasonably broad range. Thisdelay must exceed that time required by the systemto fully charge or discharge any keyboardcapacitance associated with any given T line. T4duration will always be equal to and may be greaterthan the duration of the other T lines.The following example will serve to clarify theuse of the D counter to develop a programmeddelay for a given keyboard capacitance. Assume akeyboard capacitance of 300 pF and a clock ({})rate of 500 kHz with a pulse width of 500 ns.Also, we are given a .5 mA current source tocharge the T /R line capacitance with each 500 nsclock pulse width. Using the math function:WhereV =i . tV =­cV = the voltage developed across thecapacitori = the charging currentt = the charging timec = the capacitance(15 x 10-3 ) (500 x 10-9 )(.3 x 10.9 )= .B3VWe know that a voltage of BV is a safe MaS "1"level voltage, and if our capacitance charges .B3Vwith each clock pulse then we will need approxi·mately 10 clock cycles to charge the T linecapacitance of BV or greater.10 x .B3V = B.3VTherefore, the modulus of the D counter should bespecified at 10 and it should be driven from theclock ({}) to meet the requirements of this particularkeyboard.The ROM accepts detection of any given keyclosure along with the "Case" signal input andproduces a 9-bit parallel output. The ROM outputis serialized and transmitted on the data bus at theproper time and upon command to the rest ofthe system. The output of the ROM will be takenfrom the upper 32, 9·bit words if the upper case254

condition is specified (Pin 2 = V GG ). If lower caseis specified (Pin 2 = Vss) the output wi.1I be generatedby the lower 32, 9-bit words. The outputfrom the ROM is loaded in parallel into a 9-bitshift register (Key Register) upon command fromthe housekeeping logic. This command is generatedafter the housekeeping logic has acknowledged agenuine key closure. A "Character Ready" signalis also sent out via the data bus to the rest of thesystem, at the same time. Upon receipt of thetransmit signal (Xmit key) the key register willtransmit its information out on the data bus ina bit serial manner, at the proper time. Thecontents of the ROM contain character codes thatare completely specified by the customer. Thereforethis device becomes in effect part of hiscustomized system.The static switches are interrogated by the scanlogic and entered into the static switch holdingregister at T5 time with each scan cycle. Thesesignals bypass the ROM and are switched directlyfrom the static switch holding register onto thedata bus serial fashion upon command from thesystem.The housekeeping logic performs many tlmmgand control functions which are initiated upondetection of a key closure or an input from thedata bus. These are listed below:1. Provides for elimination of switch bounce. (Forboth conditions-when the key is depressed andreleased). This feature is adjustable to accommodatethe different switch bounce times thatexist with different keyboard switches.2. Provides two key rollover.(a) Detects first key closure and generates"Busy 1"(b) Detects second key closure and generates"Busy 2"3. Provides three key alarm.4. Provides the signals ("Alarm" and "CharacterReady") to the data bus at the proper time.5. Accepts input commands (Xmit key, Alarm. Reset, etc.) from the data bus and processesthem. (See Figure 5.)The housekeeping logic performs most of its functionsupon initiation from any key signal. Thissignal is generated by detecting when any of the Rlines are true. Two key rollover detection is accomplishedthrough the use of a counter (M counter)whose modulus is equal to the keyboard scancounter (33). The sequence of events is as follows:The initial key closure is detected and the "AnyKey" signal is generated, which performs the followingfunctions: It sets a flip-flop which generatesthe "Busy 1" signal. It initializes the M andthe E counters (the E counter will be dealt withlater). It sets. another latch (1st character FF)which prevents any additional "Any Key" signalsfrom affecting the state of M .and E counters andthe "Busy 1" latch. The M counter is now timelocked to the first detected "Any Key" signal.The signal that delays the B counter in the scanlogic also delays the M counter. This enables theM counter to remain time locked to the scancounters and permits multiple key depressions tobe detected. The first key time slot will always becoincidental with the M counter equal to 0 time.Any other key depression will generate the "AnyKey" signal at the time when the M counterdoesn't equal O. This is more clearly illustrated inFigure 4.For purposes of illustration it is assumed that keyclosure was detected at scan counter time 18. The"1 st character" and "busy 1" latches will remainin the true state until the system has delayed longenough to eliminate switch bounce (key closure)and acknowledges the receipt of the valid character.This action switches the contents of the ROMinto its output shift register, and sends out a "dataready" signal on the data bus. The "1st character"and "busy 1" latches go false when the release ofthe first key is detected, again with sufficientdelay to eliminate switch bounce (key release).»zI(J1NCen::l

nE...CDrn>UJ"C-cao.Q>CD~CCDCJca.......-CDC"C-cao.Q>CD~~o ,....in~~The delay required to avoid switch bounce isaccomplished through the use of the E counter.This counter is incremented each time the Mcounter completes a cycle. The E counter willcontinue to advance until it counts out its programmedmodulus at which time all switch bounceis a thing of the past and the system is allowedto accept the initial key closure as valid. Whenthe first key is released, the E counter is again setto its initial state and allowed to advance to itsterminal state. Upon reaching its terminal state forthe second time, when all switch bounce associatedwith the first key release is over, the reset procedurefor the "1st character" and "busy 1"latches will take place. The modulus of the Ecounter may be varied to accommodate the switchbounce times of the various switches that may beused with this device. This is a parameter specifiedby the customer. The modulus of the E countermay be anything from 1 to 15.If a second key is depressed, while the first keyis held down, a sequence of events very similarto that already described will occur. The basicdifferences are that detection of the second keywill occur as a function of the "any key" signaland the M counter not equal to O. The data readysignal, from the first key closure, must have beenserviced by the system. Otherwise, this is an alarmcondition (two keys depressed simultaneously).After transmission of the first key data and detec·tion of the second key depression, the "2nd character"and "busy 2" latches will be set. The Ecounter will inject its delay and the system willacknowledge and transmit the second character.Should the system be processing two key closuresand receive yet a third, the alarm latch will gotrue. The third key depression is detected whenthe "any key", M =1= 0", and "second character" inprocess" signals occur simultaneously. When thealarm latch goes true, a signal may be transmittedto the rest of the system on the data bus. Thealarm latch is reset through the use of the clearkey or by a reset pulse on the data bus.The remainder of the housekeeping logic acceptsthe input signals from the data bus and transmitsdata out on the bus at the proper time. The timedsequence for the data bus associated with thisdevice is shown in Figure 5. We have alreadydiscussed the nature of the keyboard alarm, characterready, and Xmit key signals. The alarm setand reset signals are inputs from the rest of thesystem that cause or remove the alarm condition.The test input is for testing purposes only. It isused to speed up the testing of this device whenthe inputs to the device are generated from controlled(bounce free) sources. Therefore there isno need for the normal system delays. The systemcould conceivably be used by the O.E.M. manufacturerfor incoming receiving inspection, just asthe factory uses it. A more exact understanding ofits use should be acquired from the factory beforeit is used.The static Xmit inputs are used to cause the keyboardinterface to deliver the data stored in thestatic switch holding register at the immediatenext appropriate time. There are four of thesestatic Xmit input pulses to permit use of up toNinI2:«XMIT KEYSHIFT CODESTATIC XMIT 1STATIC XMIT 2STATIC XMIT3STATIC XMIT 4ALARM SETALARM RESETCHARACTER READYKEYBOARD ALARMJL~OIAhIAIhlohlcLFIGURE 5. MM5704 1/0 Time Slots256

»zI01N~~1111111111111I IC:===:=JI GAlA TRANSfER LINE-_"--SIGNALOKCONTAOLLINEfour keyboard interface chips and associated staticswitches in parallel. The device user may specifywhich time slot will be used with a given device.This is especially important when two or more ofthese devices are to be used in a system. If this isleft unspecified in a single keyboard interface chipsystem, this will generally be programmed to theXmit static 1 time slot. It is an illegal conditionfor both a static transmit and key code transmitrequest to occur in the same word cycle.THE KEYBOARD INTERFACEAS USED IN MAPSFIGURE 6. MAPS Block Diagraml 461", :! DM1441The natural environment for this device is tooperate in conjunction with the "timing and control"(T&C) chip (MM5702) of MAPS. MAPS(Microprogrammable Arithmetic Processing System)is a five MOS-LSI chip, mini-processor system.The block diagram shown in Figure 6illustrates the system's primary components andtheir interconnections. Besides the clock lines andpower supplies, the keyboard interface chip has acycle marker (CM) input from the MAPS system.This signal (CM) is generated in the T & Cchip from a master timing clock and is used tosynchronize the entire system including the KI.This procedure is mandatory in a system, such asthis, where all data as well as command and operationsignals are transmitted in a serial by bit andserial by digit basis. The exchange of all informationbetween the system blocks is time multiplexedonto single wire buses; therefore, all of the systemcomponents must be in step. The cycle markerflags the beginning of a 76 bit word cycle time.The important bit times for the KI chip inMAPS are, for example, 11 through 30. Theseare the bit times in any given word cycle thatare allotted for the KI to communicate withthe rest of the system through the T & C chip.The detailed nature of this time period is morecompletely defined and illustrated in Figure 5.The various time slots are logically defined andimplemented within the KI chip as follows: TheCM initiates a delay line composed of a series ofMOS inverters. The outputs of these invertersbecome true in a sequential fashion, one afteranother in step with each clock transition. Therefore,once the sequence is initiated at the propertime (CM) the MOS delay line will behave as aspecial decoded counter in step with the mastercounter in the T & C chip. The output of eachstage will define a precise bit time with respectto the CM. This occurs within the housekeepingblock (Figure 2). When the KI has acknowledgeda key closure it will send out a character readysignal (bit time 20), and continue to send it untilit is acknowledged by the T & C chip. The T & Cchip will receive this and, in some subsequent wordcycle at bit time 12, will send a transmit key,'"Ctil:::sCC...-t::rCD3:3:01.....o~CD< "0"'oQ)...0-:::sr+CD...~Q)(')CD:::sCD< "0"'oQ)...0-m

enEQ)...en>en..."CcooJ:l>Q)~r:Q)(,)CO...'t:Q)r:KEYBOARD MATRIX,....---------------,i!(t(~I Lf+.-1J Lff,-U II _ ' IL _____________ ..JNUMERICSALPHA ALARM OUT VGGI "R6A5R4R LINESR3R2TI9DATA BUSTIS:~:~llL~~I----be PARITY1----.,KMr_-bsPARITYI--+-bs PARITYCODN:a~~~ER ~--+-b4 PARITY~_-+_b3PARrTY1--+-b2 PARITY~--+-bl PARITYT LINESR1ROTO 11 T2 T9 TilTIleLKv~CLOCKDM885DSN14tDlCONTROLLOWERCASEFIGURE 7. ASCII Keyboard Encoder Using the MM5704NLnIz«command. This will cause the keyboard to sendits data from the keyboard shift register out ontothe data bus (microinstruction) during time slot 22through 30 immediately following the receipt ofthe transmit command. The data bits are receivedby the T & C chip. The static switch information,from the keyboard, is handled in a similar mannerby the system. It is the intent of this section toonly deal with the interaction of the KI chip withthe rest of the system. Therefore, a more detailedtreatment of the operation beyond this pointbelongs in a description of the T & C chip, asrelated to MAPS.THE KEYBOARD INTERFACE ELEMENTAS A STANDARD ASCII ENCODE SYSTEMThe MM5704 may be used quite conveniently inapplications other than as part of the calculatorchip system for which it was designed. To illustratehow this may be done, a small keyboard systemwas designed to perform the keyboard to ASCIIencoding function. Only one of the MM5704swas required to provide for all 128 characters inthe ASCII 7-bit communications code. This systemis illustrated in Figure 7.A two phase clock must be generated and a mastercounter designed to operate from the clock system.A DM8850 (9601) is used to drive a JKflip-flop in the toggle mode of operation. Thisforms a master clock that has an equal duty cycle.One eight bit shift register and one SN74107 isused to form a twisted ring counter. This type ofcounter was chosen because of the ease withwhich its states may be decoded. One and 1/2 quad2 input NAND gates are used to decode thecounter outputs into the discrete time slots requiredfor the bit serial operation of the KI.Because there is no need to concern ourselveswith anything other than the time slots requiredto operate the KI chips, the time slots have beenreorganized and the word length shortened. This ismore clearly defined and illustrated in Figure 8.The cycle marker signal is generated by setting alatch at time 0 and resetting it at time 1. CM isonly used, in this system, by the KI chip.The keyboard switch entry operation is accomplishedexactly as described in a previous sectionof this application note. The KI chip will interrogatethe keyboard switch matrix. The alpha/numeric control is accomplished externally by a258

XMIT KEYRESET XMIT LATCHCHARACTER READYT 0Jl 2341516171891011112113114115116117118191011cMLIJ"'l.-FIGURE 8. ASCII Keyboard I/O Time Slots»zIU'1Nc:(II::s(Q-I::s­(I)mechanical latch on the keyboard. If the keyboardshould lack this facility, an integrated circuit latchcould be added to perform this function.At character read time (T91, the data bus ().II) isgated to an RS flip-flop. For the sake of illustratingthe action sequence, let's assume that a characterready (T9) signal appears on the).ll data bus andthe Xmit latch is set. The data bus line is the datainput to an eight bit shift register. This shiftregister is used to perform the serial to parallelconversion. Nothing further occurs until the nextword cycle is initiated and time slot 1 is reach~d.The Xmit flip-flop has enabled a gate that willgenerate the Xmit key signal at T1 and place thison the).ll bus. This will be received by the KI chipand trigger the transmission of data from the keyboardholding shift register beginning with timeb7~0 b7~1CON. UC LCb6~1 b6~0 b6~0 b6~1TABLE 1. ASCII Keyboard Assignmentsslot 11 and ending with time slot 18 (8 bits long).The Xmit latch will automatically be reset at timeT2. The generation of the Xmit latch will auto·matically be reset at time T2. The generation ofthe Xmit key signal at T1 also causes anotherlatch to be energized (prepare for data). This latchwill enable a gate which at time T11 (the beginningof the data word) will set a clock control latch.This action enables the clock to the output shiftregister for 8 clock pulses. The clock enable latchis reset at time T19. The eight clock pulses to theshift register will permit the entry of the datacoming from the KI ).II bus and accomplish theserial to parallel conversion. At time T19, the dataprep. latch is reset.The character and control codes associated withthe KI device are illustrated in Table 1. The con·0 SP N+l @ \ T4 R6 b7~1~Alpha1 1 S04 A a T2 RO b7~0~Numerics2 " STX B b T3 R43 # ETX C c T3 R2 LC~alpha • b6~ 14 $ EOT 0 d T2 R2 UC~alpha • b6~05 % ENO E e Tl R26 & ACK F f T2 R3 Numbers~Numerics. b6~17 BEL G g T2 R4 Control~Numerics • b6~08 ( BS H h T2 R59 ) HT I i Tl R710.LF J j T2 R611 + VT K k T2 R712 FF L 1 T3 R713 - CR M m T3 R6 • ~Key Legend14 SO N n T3 R5 example15 / Sl 0 0 T4 RO·16 0 OLE P p T4 Rl17 1 DCl 0 q Tl RO18 2 DC2 R r Tl R319 3 DC3 S s T2 Rl20 4 DC4 T t Tl R421 5 NAK U u Tl R622 6 SYN V v T3 R323 7 ETB W w Rl Rl24 8 CAN X x T3 Rl25 9 EM Y y Tl R526 : SUB Z z T3 RO27 ; ESC [ ! T4 R228 < FS \ : T4 R3~29 GS 1 I T4 R4~ ~30 > RS T4 R531 ? US - DEL T4 R7...::s(I)~Q)n(I)::s(I)'< "C­OQ)...Coen...'

U)EQ)...U)>til..."0coo.c>Q)~c- ...Q)Q)()CO...cTABLE 2. American Standard Code for Information Interchangeb 7 a a a a 1 1 1 1bs a a 1 1 a a 1 1____.bs a 1 a 1 a 1 a 1Bit b4 b 3 b 2 b,~ a 1 2 3 4 5 6 7Ia a a a a NUL OLE SP a @ P pa a a 1 1 SOH DCl ! 1 A G a qa a 1 a 2 STX DC2 " 2 B R b ra a 1 1 3 ETX DC3 # 3 C S c sa 1 a a 4 EOT DC4 $ 4 0 T d ta 1 a 1 5 ENG NAK % 5 E U e ua 1 1 a 6 ACK SYN & 6 F V f va 1 1 1 7 BEL ETB 7 G W g w1 a a a 8 BS CAN ( 8 H X h x1 a a 1 9 HT EM ) 9 I Y i Y1 a 1 a 10 LF SUB * : J Z j z1 a 1 1 11 VT ESC + K [ k I1 1 0 a 12 FF FS < L \ I1 1 a 1 13 CR GS - - M J m !~1 1 1 a 14 SO RS > N~ n1 1 1 1 15 SI US / ? 0 - 0 DEL~ I j I jROW -This coded character set is to be used for the general interchange of information among information processing systems,communication systems, and associated equipment.NInIZ«trol codes are identical with the numerics sectionof this device, except that bit b6 is a logic "0"instead of "1 n. The lower case letters are the sameas the capital letters (alpha section) except thatbit b6 is a logic "1" instead of "0". A glance atthe 7-bit ASCII standard MAPS (Table 2) willshow this to be consistent with the acceptedstandard. The manner in which this is implementedin our stand alone system is as follows: When thecontrol key is depressed bit b6 is slaved low in theoutput of the serial to parallel shift register, then ifthe numeric characters are being generated by theKI, control codes will result in the output of theshift register. If character key $, for example, wasdepressed, the resulting data code from the serialto parallel converter would be modified from01001000 ($) to 00001000 (EDT).The features of the KI chip will permit a moreelaborate system than this, but this is all that isrequired to accomplish the use of the KI chip intoa bipolar system. The total parts count is asfollows:1 - MM57041 - DM88502 - SN741071 - MH00251 - DM88002 - DM85704 - DM74001 - SN7404PROGRAMMING THE KEYBOARDINTERFACE CHIPWithin this device, there are nine areas that may bespecified, or programmed, by the customer. Thelargest of these is the encoding ROM with its 649-bit words. The ROM is actually programmedduring the process with a masking step that eitherleaves or removes gate oxide from a given nodedepending upon whether a 1 or 0 is desired fromthat node. To assist in programming the modulusof D and E counters, which may vary from 1 to15, vital information pertaining to keyboard performanceis required. This information will enablethe KI chip to overcome T line delays and switchbounce as explained in an earlier section of thisarticle. The D counter clock may also be specifiedto be either 8 in or CM. The fifth area to be specifiedas the static switch recognition code. If morethan one chip is used in any given system, eachchip must be given a unique internal code that willenable it to respond when the system calls forstatic switch data from a specific device.The sixth area to be defined is an option that willpermit the static switch information to be generatedfrom normally open, or normally closed,switch contacts. The seventh programmable functionpermits specifying the shift key switch aseither normally open or closed. Within the chipitself, these functions are implemented by inserting,or not inserting an inverter in the appropriateplace. Programmable function number eight per-260

mits the user to inhibit or transmit the alarm pulseon the JJI bus. Number nine specifies whether thesystem will accept or reject, set and reset alarmpulses from the JJI bus. These latter conditionsresult from making or not making the appropriateinternal connections.Figure 9 is a copy of the form used to manuallyprogram this device. Because a great deal of theactual process involved in programming this deviceis accomplished with the use of a computer, anormal computer input such as IBM cards may besubmitted by the customer to program this device.J>Z1UINc:UI _.~CO-I~CDNational Semiconductor Corporation2900 Semiconductor Drive, Santa Clara, California 9505114081 732-5000/TWX 19101 339-9240KEYBOARD INTERFACE PROGRAM SHEET MM5704NAME:ADDRESS:CITY:PHONE:STATE"ZIP'AUTHORIZED SIGNATUREDATE:CUSTOMER PAINT OR ID NO.PURCHASE ORDER NO.TOTAL KEY MATRIX CAPACITANCECLOCK FREQUENCYMIN TVP MAX UNITS FOR NATIONAL SEMICONDUCTOR USE ONLY1------+---- ---+---'--"-=---+-----'~'-'r'-'-"-"-=----;cc::_-'-'-'~=_=;:_~"__,~__jpFCOUNTERDRIVINGMODULOTIMINGPROGRAMFUNCTION~KEY BOUNCE DELAYo COUNTER1------ --------I----_+---'I____+--___ic-----I__---+---+---+--ICYCLE MARKER FREQUENCY (CM) kH, E COUNTERI-- ----CASE SHIFT CONTROL (CS)STATIC KEY FOAMKEYIDEN­TITYSCANLINET A"-"-- -" -""--1--.--+---,-_+-----'---__\__------------'----'--------1NONOPIN NO.2 (+JNCUpper Case L09icLevel + -DeviceNo"10 203D 40COMMENTST1 ROI__--+-+-+-__+--_+-"~~----_+---+___+--_+----+__+---+___+~-_+--+__+--_+--_I____iTl Alr--~-+_I___+--+-__+--__\__~I___+--I___+--_+--_+--+__+--+___+--_I____i---+--+___+Tl R2T1 A3T1 A4T1 A5T1 A6151 T1 A7T2 ROT2 RlT2 R2I-----~~+--+-""-"-"-T2 R3T2 R4T2 RST2 R6-KEYIDEN·TlTYPINNO.2H"----+--~--"~--~--+---I---+----\-----+--+--+--+---+--+---+---+--+---+~....CD...~C»(')CD~;:iIIi:CD

enECI)...en>en"C...C'CSo.Q>CI)~c:CI)(,)C'CS't:CI)...c:The input must, however, follow the format asillustrated in Table 3. The output bit patternis converted to a three digit decimal number. Eachcard contains eight of these numbers using the first32 columns on the card. The associated addressrR7XXXT2 XXXL.C.T3 XXXT4 XXXrXXXT2 XXXU.C.T3 XXXT4 XXXCOlumnl~Example (for column 1)Ref>XXXXXXXXXXXXXXXXXXXXXXXXTABLE 3. Computer Programming FormatR5XXXXXXXXXXXXXXXXXXXXXXXXRlXXXXXXXXXXXXXXXXXXXXXXXX(Tx, Rx) is specified by card number and outputdigit location. Only the ROM portion of thekeyboard interface chip may be programmed. Allother programmable features must be specifiedin another fashion.R2XXXXXXXXXXXXXXXXXXXXXXXXR3XXXXXXXXXXXXXXXXXXXXXXXXR4XXXXXXXXXXXXXXXXXXXXXXXXR6XXXXXXXXXXXXXXXXXXXXXXXX1st Card2nd Card3rd Card4th Card5th Card6th Card7th Card8th CardNumber R7. Tl Bit 8Output Conversion Example 256o128o64o32 16 8 4 2Bit 0 (1st out)o24832256L.C. = lower caseU.C. = upper case302NanIZ

Application NotesOCTOBER 1971»2IU'IU'Ir­o:eLOW FREQUENCY OPERATION WITH DYNAMICSHIFT REGISTERSIn many dynamic shift register applications, it isadvantageous to operate the circuit at low clockfrequencies or in clock burst modes where highfrequency clock rate periods are followed by longintervals in which the clocks are absent. To insurethat his system will operate correctly under theseconditions, the designer should be aware of thelimitations of the type of shift register he is using.There are two basic forms of dynamic shift registercells: the ratioless and the ratio. The ratiolesscircuit of Figure 1a is based on a capacit~r pre·charge concept. During 1>IN clock time, node B isprecharged by transistor 0 3 ; i.e., 0 3 is turned onby 1>IN, creating a low impedance path from nodeB to V GG which charges the node capacitor C 2 toa negative Voltage. Data is coupled at the same timethrough transfer transistor 0 1 to node A, the gateof O 2 , If the incoming data is a positive or "0"level, O 2 will be in a high impedance off state, andnode B will charge to a negative voltage one thresh·old more positive than the 1>IN clock amplitude.When ct>IN returns to a positive level. 0 3 is shutoff, isolating the precharged voltage of node B.The stored charge of node B, coupled with anadditional increment contributed by C 4 , redistributesbetween nodes Band C when the ct>OUTclock turns on transistor 0 4 , The redistributedcharge develops a negative voltage" 1" level acrossC 3 which becomes isolated when 1>OUT returns toa "0" level. The "1" level turns on 0 5 , resultingin a low impedance path between the output of thecell and Vss, establishing a "0" level at the output.In the ratioless cell, there are two nodes whichbecome isolated from any charge replenishingsource during normal operation of the circuit:nodes Band C. These are the nodes which establishthe low frequency limitations of the cell. In mostdesigns node C, the gate of the logic transistor 0 5 ,is the limiting node because total capacitance isless. If we had assumed the initial data coupled by0 1 during ct>IN to be a "1" level, then node Awould of course be the limiting node of the cell.OUTPUTFIGURE la. Ratioless Dynamic Shift Register Cell263

...enQ)...enC)Q)a:...0f-.&:.tJ)()Ecoc>C.&:....1----0

The period of the minimum operating frequencyis the sum of the two, or1

...(1)Q)....(1).-0>Q)a:........s::.en. ~Ecoc>o.s::.....co.~CO...Q)C-O>(,)cQ)::;,0"Q)...LL~o....IananIZ~The shift register user can often increase his marginof safety when operating at low frequency, orfor long periods of time with the clocks stopped,by designing the system with that operation inmind. The ambient operating temperature of theregisters should always be minimized. The cell requiresa minimum voltage at the critical node tooperate, and the time to discharge the node to thatvalue is dependent upon the initial voltage, as wellas capacitance and leakage:~ CNODE (VINITIAL - VMIN ) (6)tdILtdCNODEVINITIALVMINTIN or TOUT for ratioless cells;

AMERICAN AND EUROPEAN FONTS INSTANDARD CHARACTER GENERATORSTen popular American and European 64-charactersubsets for displays and printers are now availablefrom National as single-ch ip, standard charactergenerators. These parts, listed in Table 1, are soldoff-the-shelf without a ROM masking charge.The ROMs are static, bipolar-compatible types,operating without clocks on standard power supplies.Rowand column access times are typically450 and 700 ns respectively. An MM4240/MM52402560-bit ROM is used for the 5 x 7 horizontal-scanfonts and an MM4241/MM5241 3072-bit ROM forthe 7 x 5 vertical-scan fonts. The M M4240 andMM4241 operate at -55°C to +125° C and theMM5240 and MM5241 at -25°C to +70°C.TYPE NUMBERHorizontal Scan (5 x 7)MM4240AAlMM5240AAMM4240AE/MM5240AEMM4240ABU/MM5240ABUMM4240ABZ/MM5240ABZMM4240ACA/MM5240ACAVertical Scan (7 x 5)MM4241ABLlMM5241ABLMM4241ABV/MM5241ABVMM4241 ABW/MM5241 ABWMM4241ABX/MM5241ABXMM4241ABY IMM5241 ABYCODEASCIIASCIIHollerithEBCDIC-BEBCDICASCIIECMAECMAECMAECMAApplication NotesJANUARY 1971I nput-output configurations and character formatsfor the ROMs are shown in Figures 1 and 2. ApplicationNote AN-40 The Systems Approach toCharacter Generators gives examples of line andcolumn address-control logic, and CRT and printeroperating techniques.Note that each ROM has a chip-enable input topermit multi-ROM operation with common controllogic. For instance, two horizontal-scan ASCIIcharacter generators may be operated in tandem toobtain upper and lower-case characters. I n thiscase, chip-enable would be controlled with bit b 6of the n~mal 7-bit ASCII code, and its complement,b 6 .64-CHARACTER SUBSETFIGUREUpper-case alphanumeric 3Lower-case alpha and symbols 4Upper-case alphanumeric 5Upper-case alphanumeric 6Upper·case alphanumeric (IBM) 7Upper-case alphanumericUpper-case A/N, Scandinavian 9Upper·case A/N. German 10Upper·case A/N. generalEuropean (French, British, Italian) 11Upper·case A/N. Spanish 12B»zI(J'I.....»3CD~.(')Q):JQ):JC.mC...o"0CDQ):J.."o:Jr+VI_.:Jrnr+Q):JC.Q)...c.(')~Q)...Q)(')r+CD...C)CD:JCD...o ...Q)r+VITABLE 1. Single-Chip. Standard Horizontal-Scan and Vertical-Scan Character GeneratorsCODEINPlJTS1C""'ClE'A!lOR£SS)1::bJ"cMM4Z401MM~240"B,"'.OUTPUTSOUTPUTSB,B2 Bl 84 Bs000001. •010 •••ROW 011 •••ADDRESS 100. ••101. •110. •111. •CHARACTER FORMAT",1",CODE h,INPUtS[CHARACTER hADDRESS) ,COLUMNADDRESSINPUTS".I""C,C'J~RDGRAMMABLECHII'ENABLE ICoB,""MM4241! B,MM5241'.'."B.L,-\ '"""COLUMNADDRESSg8~;;~~'.. •a·. IOllTPUTS~ :',.B,.B,CHARACTER FORMAT•••FIGURE 1. Horizontal-Scan Character Generator ROMFIGURE 2. Vertical·Scan Character Generator ROM267

..... oCO..Q)..Q)...CJco ..U)cQ)oco~()'Eco"0Cco...encU)...coLLCCOQ)Q.o ..:::sw"0CCO..CCO. ~Q)E«" t.nIZ«HORIZONTAL SCAN FONTSThe subsets of 64 5 x 7 characters in the horizontal-scanfonts are the ones most commonlyused in low-cost TV and CRT raster-scan displaysand dot-matrix line printers.MM4240AAlMM5240AA contains the ASCII-6 preferredgraphic subset, formed from ASCII-7 byignoring bit b 6 . The remaining six bits form twooctal address characters. One is formed by thethree more significant bits, b 7, b 5 and b 4 , and thesecond by b 3 , b 2 and b l .Also, characters 36 and 37 in ASCII (x3.4 1968) *are respectively a carat (or circumflex), and anunderscore. These are awkward in a video display,so they are replaced by the more useful arrows.(The arrows are related to characters in an olderteletypewriter set.) This font, shown in Figure 3,is also described on the MM4240/MM5240 datasheet (which should be referred to for operatingcharacteristics of all the horizontal-scan charactergenerators)..:... . ....:::.::::... .... ..... .....: ·.. . ...... .... .. ... ... . ... . ... ..... . . .... ... .... ...... ...IW 01 02 03 D4 05 06 07000001 000010 000011 000100 000101 000110 000111I. ..: eii: .t · . . ..... ·... . ....... ..... ..... .:: .-: : ::. ::...:III 11 II 13 14 IS Hi 11001000 001001 001010 aUlD!1 001100 001101 001110 001111r··: .... :. ....: ....i···: .:.... ··i··!......iii i.!! :.:.: ! ...... :. I : ••• : .:. i···1,0 21 22 23 24 25 26 n·.. ..010000 010001 010010 010011 010100 010111.. ..... ...... ...: ..:.. .o • ..':..: : ..... = ... ..:. : ! ·1:··34 J; 35 37011000 011001011011 011100 011101011111: : .. ...... .... ..... ..... .. ::. ... ... .41100000 '".1000Ul'. ·4Z 43 44 45 46 47100010 100011 100100 100110 100111.:::. .. ::: ... ..... .. ..'.':: :,...51101000::.: .... .....52 53 54 55 56 57101010 101011 101100 101101 101110 101111.: :.... ... ....::.1.•••• ••• :••:. I I···. ••...61.. :.... ••••• I •••••••••• I110001....·... .·.. 52 63 64 65 66 67110010 110100 110101 110110 110111.... . . .,1072 73 74 75111001 111010 111100 111101 11111030 31 32 D......50: : . ... ·· : :: .. · .. . . .·.".. .. ........ ...· .. : ::· ... .... . .Input addre'ies are in SIX bit ASCII code and are shown in theiquence A5. A4.valent IS also shown lor.elerence." "Ao; the octal equi.. .......110 01 02 03 04 05 06 07'.' · :... ..... ..... ..... .I ! .-:-. 1 •• 1 i',.: I···! :-:: 1:-:1 :•••:..000000..000001.. .....000010 000011 000100 000101 000110 000111.. .. .. ..••: :.. ••••• i···1 I···! •• .:. 1.=.=..: :.. ..... .:. .:::..... I !! .:.10 11 12 13 14 15 15 17001000 001001 001010 001011 001100 001101 001110 001111... .:. .:. ... ... ... .:. .:.I···! !.. :.! i·: ..! I·: ...! I ... :·11:·:1111 .. ... I·!·I· . . . . . . ..20 21 22 23 24 25 26 2J010000 010001 010010 010011 010100 010101 010110 010111:.... :.:.:.: ..:.:.: :... : :.:.: :.:.: :...: •...:·................................: ...................................... ,: : : :,:: :: ,: ,,:,,::.m 31 n n.....~ ~ ~ 31011000 011001 0111110 011011 011100 011101 011110 011111· · · · ..... ·... · ....••• 140 41 4Z 4J 44 45 .. 47· .. 1(100(10 1000(11 100010 100100 100111· . ·· . · ... • ... .. ..: : : : .....50...50 51 53 54 55 56 51101000 101001 101010 101011 101100 101101 101110 101111...!. .... 11.1:.·· .... ........... ·····:··: :: :: :· .. .. ....~. .61 ~ ~ ~ M 66 g110000 110001 110010 110011 110100 110101 110110 110"1·..... . = . . ..'. :· · ... .1072 73 74 7571111000 111001 " 111010 111011 111100 111110 111111. · . .. ·: .. ... .. · .. ..· .. .: ., :.....:. .... .... ....· ·:.. . · . · : ... · · :.. . .. .. .: : : :... ·· .. .... .. ... . ..· ·...· . : I I.. ... ......... . · . · .FIGURE 4. MM4240AE/MM5240AE Horizontal·ScanASCI 1-7 Lower-Case Graphic and ControlSymbol SubsetThe Hollerith character subset in Figure 5b isformed by using six gates to compress the 12-line Hollerith code to the 6-bit address for 64characters, as shown in Figure 5aPUNCHEO ""'"MM'l40ABU'MM~l40ABUFIGURE 3. MM4240AA/MM5240AA Horizontal·ScanASCII-7 Graphic SubsetMM4240AE/MM5240AE generates unique symbolsdescribing the ASCII-7 control codes, as well aslower·case letters (Figure 4). The designer may notwish to display or dot-print the symbols. Since thesymbols are generated only when the most significantaddress bit is logic "0", this bit line may beused to disable the ch ip, and blank the screen whencontrol signals are transmitted. If not, the systemdesigner can use the symbols as he likes.'American National Standards Institute (ANSI)FIGURE 5a. MM4240ABU/MM5240ABU TypicalAddress Inputs268

1111.: ·... ... .. .....:. : :::....... . .......:..:. :·:.... .....:.... : .......... :02 OJ M as ~ ~111111[11111 IIUOnll1 "'·000010 000100 000101 000110 000111............. .....:· .... . ..I-... ....: :.i:::; .:::: .... : .. ·.. . ....n,:: '.~:' .~; In:·...11] II 11UOIOIO 001011 001100 001101 001110: : ......... I ! I::::!.!·:·:·:·1~: : 71 •• ~ •• ~ •• ~ •• ~ :·26·:: 17:·III1IUOIl OlUOOI 010010 010011 010100 010101 010110 010111...... .... ••••• ... .....•••• :1.. ...... . . · .... · .. . .....lO 31 3234 35 35 37Dl1001 011010 011011 "· ..... 011100 011101 011110 011111. ..... .. .. ........ .::.. : ::: ·:1 :1···••••• : •• I. ••• : :: : :•••: :.....40 41 42 43 44 45 46 47100000 100001 100010 UOOll 100100 100101 100110 100111:.... . ... : : :.... .. : : .' '. · .I. : ..:.... ... ...... :.. :· ...50 51 52 53 55 56 51101000 101001 101010 101011 "· .... ... .... ..... .....101110 101111...... . .... .. ... ... . ..••:•• i···1 .i•.: :..•.. 1 ..: I •••• I :••• 1·60·61·62·63 64·65·66 67110000 110001 1100111 110100 110101 lUll0 110111· ... ...... .. .. .... ....i···: ... :-. :...:: : ..'..:...... ... :::.:::: :..... ... ... · : : . ..· · ... · ... .. · · ..... · ." " "10 11 72 11 14111000 111001 111010 111011 111100 111101 111110 111111FIGURE 5b. MM4240ABU/MM5240ABU HorizontalScan Hollerith Graph ics SubsetAs shown in Figure 6, an ASCII·compatible subsetis provided by the EBCDIC-8 character generator(MM4240ABZ/MM5240ABZ) by simply ignoringthe two most significant bits, bo and b" in theEBCDIC-8 code. The ABZ version follows theANSI standard, while the ACA version follows the· .. .. .. . . .... :......... :.... :.... : .............. ... ...· ...... . .. ... . ..... ... .... ...... ....· .......:....: .'·. :·...:..00 01 01 03 D4 ~ 00 ~·000000 000001 000010 000100 000110 000111: .:. ~. I.. :: · 14··17 '. :001000 '" 001001 001010 001011 " 001100 001101 " 001110 ". ·.... 17001111........ .·... . ..... . .. ...... ...... . .10 21 12 23 M 15 26 n...010000 010001 0111010 010011 010100 010101 010110 010111.... ... . . · . . . ....... . .. · .. .·:1· . ·· ..: ..:. ·....30 37 J2 33 J4 35 J6 37011000 011001 011010 011011 011100 011101 011111: ....... ....... : ::::::: :·.. ........ :: ::::.: ... ...... ·40 41 41 43 44 45 46 47100000 100001 100010 100011 leo 100 1001Ui 1001U 100111.......: ......:·...· .. ·.. 'SO.51101000 101001.: .52 53::: ...' .54 ••••• 56101010 101011 101 100 101S~Ol..... .....·53101 110:.... ... ...::....:..... ..: ::.:.....: ;.... ...,. .1.......61110000·.-··: .. 110011 ... .110100· · · .110110 1101110 :: ............·. · ..76 71 72 3J 74 15 16 71111001} 111001 111010 111011 111100 111101 111110 111111... :: .. : :::: .. :: :: ...... . · · . ·: . : :.:. . .: ... ::,.· ... . ... . . .. .... ...:... ..:.:.... ..... : .......... :62 63 64 65 66 67.. ..... ..· · . ·.FIGURE 6. MM4240BABZ/MM5240BABZ Horizontal­Scan EBCDIC-8 Graphic SubsetIBM style. A cent sign, and IBM's logical OR andlogic NOT signs are given by the ACA subset(characters 12, 17, and 37). And a plus or minussign is provided, as character 52. (See Figure 7.)· .. .. ... . .I···! i ...: :.... I ...: i .... I: ..:!no 01 02 03 D4 05 06 07DUO 000 000001 000010 000100 000101 000110 000111: .:......· i'". .:.::i:.' :... ::.:.. .....". : ·:171416001000 001001 " 001010 001011 " 001100 001101 " 001110 001111'7·.. .... .......... 010000 010001 010011 010100 010101 010111.... ..:.::.:·...... . . .. ·.. ....:. :· II ····130 31....32011001 011010. .3J011011.....:... .J4 35 J6 37011100 011110 011111: : :· ... i·40 41 421001}00 100001 100010...... .·· ·. ·.· : · .: : .:. :...: . 100011 " " ·45 46100101 100110 ":::..:.. .... ··1·· .. .. ..... ..... . ·......:...100111....:·50 51 52 53 54 ••••• 56101000 101010101100 55 101110 101111 "'.... · .!..... :....... ..: ::.:..... ....: ;.... .....6661110000 110001:·... ..:.... ..... : .......... :62 63 64 65 66 67...: : .110010 110011 110100 110101 110110 110111:: .:.:.. ·. ...· 71 72 3J 74 7571111000 111001 111010 111011 111100 111101 111110 111111... :......... :.... :.... :· ...... ..... .............:: .. :..::. : :...: :... ::.. : :::: ..:: ::.............. : .. :.... : :: ::...::...· ...10 21 22 23 24·...2~ 26 27.. ..... · · . ·. . .: ... .... ... . ..... .. .... .. .'". .. . ... . .· . .. · .:: .:.: .· .. : : :FIGURE 7. MM4240ACA/MM5240ACA Horizontal·Scan IBM EBCDIC Graphic SubsetVERTICAL SCAN FONTSAll five of the standard vertical-scan subsets inFigures 8 through 12 are generated with 6-bitcodes derived from code recommendations R646of the International Organization for Standardization.These recommendations cover ASCII-7, EuropeanECMA-7 and CCITT alphabet number 5 .The ASCII subset for American use, in Figure 8,is practically identical to the horizontal-scan subset.Those in Figures 9 through 12 follow preferredcharacter styles in the countries indicated. Theunderscore (character 37) is dropped below theline so that it may be used as a cursor.Vertical-scan character generators are generallyused in dot-matrix tape printers, ink-dot sprayprinters and high·definition sawtooth or pedestalscanCRT displays. They may also be used tocontrol raster·scan TV tubes or CRTs if the tubeis turned on its side so that the raster scan is madevertically to provide a page-like format.With standard programming, the bits in the columnoutputs are sequenced for a sawtooth scan withdot columns running in the same direction, asillustrated in Figure 13a. For a pedestal scan,Figure 13b, alternate columns can be reversedby putting an 8-bit shift left/shift right TTLshift register (DM74198) on the output as illustratedin Figure 14."l>ZIU1"(')Jm~m(")....CD~G')CD:lCD~m....o~(I)269

(I)..... oasQ)..Q)...Co).. asas..cQ)CJ.cCJ" as"...c asU)c(I)...cou.casQ)Q.o..~w" c ascasCo)..::Q)Ect....anIZct... ... .... ... ... ............I I-i 1 ... 11 ... 1 I • I -: I... L.. I .:1.::-iii ...: :.... i ..·· i .... : :._".!00 ~ ~ m MM.: : ... _:_: .e: :••::. : •••••000000 0011001 000010 000011 0011100 000101 000110 OD0l111···1 .I. I I·: i10 11 13 12 14 15 16 1700IDOO 001001 001010 001011 001100 DOt 101 001,10 001111! : ! i··.! I I•••• : •• :•••• : :1·:·••••I···: :•••: I···: :•••• ··1·· I II II Ii··· i·.::·:: ...: : i i :: III• •• •• . ...• . ••. : r·:20 21 U n ~ n H 21010000 010001 010010 010011 010100 010101 010110 010111:::.: ..,.:..... . :... ··1 C-·t·: : : :.•.. I •• : .....011110 "•·:II .1.:••·1·· ::.: :.: ...• ·Ii· ·:1:· :••:: :::.:•I•I.·..4J ~ % U:·1·: •• 1 ••· ..... .......... " •::.'"eI .... ..... ·, .... .......:1.··1 ·1 .• ... .I ••:': I···........ I .. :.......... ••· .... .. • • .6Z B3 .. •110000 110001 mOlD 110011 110100 110101 "·... .. .. .. . ..110110 110111..... •••• 1 • • •. .. .. ••I ...: •••• · . I ... ..... .. ·. . •1130 31 32 34 35011000 011001 011010 011011 011100 011101.. 411000011 100001101000 "101001.. 61"42100010IOQOIl 100100 100101 10011031011111100111 "52 53 54 55 56 57101010 101011 1011110 101101 101110 101111"" "OS 671113 14mOOD 111OD1 111010 111011 111100 111101 111110 111111FIGURE 8. MM4241ABL/MM5241ABL Vertical·ScanASCII·7 Graphic Subset........""UDUOOOoi···1: :OU1000 '"... ... ..... ........1 ••• 1 .. I •••: I • I .:. I... . I... I .:: ::......... :... :.... : ....:01 02 03 04 O~ 06 07.:. ..... ... .... ......000001 000010 0110011 0001011 000101 000110 000111i.:.001001 "I I·: I•••• : ·.1 •••• :I : 11··.11 I:: .: •••••12 13 14 15 16 17001010 001011 001100 1101101 001110 001111I···: :•••: I···: :•••• ··1·· I I I II I•••••••••••••••• :: I::I :.:.: I .......: I :...: : :..:10 21 22 23 24 25 26 27010000 010001 010010 010011 010101:.010111:: : ....:. ....:.: ••,.. ••• ::::: :•••: I I· I •· . . ...... ...... .....30 31 32 33 34 35 36n· ...011111:.:. ....... .:. ...:::1:. .:;: : :: ..... ....•.. ·.:"·...43 44 45 46:·1·:· •• 1 :., ••..:·......... ..... ..... .: .............:1.··1·1 •••• .: ::.L ••••: I···. •••••••• 1 •• :.... ••••• : .......... :&0 61 &2 63 64 65 86 61.......... ..i::i ::::1 . .:....... ..·•.. ..........11 71 n15 16 77"'... 111 DOl 11101011110a " 111101 111110 111111011000 011001 011010 011011 011100 011101 0111104D10000010100041· 11100015110100141100010100011 100100 100101 100110100111 "52 53 54 55 55 57101010 101011 101100 101101 101110 101111110000 1100Dl 110010 110011 110100 110101 110110 110111.173111011..:::.....ao000000i···i: :001000 '"... .... ... ... .............. .. ... . ..11 •••••...·1••• :.... : •••.:...01 02 1IJ 04 05 06 07.:.. :.:..;:!::i I.·.· .-.ei::.~. •••• : ·.1•••• : I: •••••1 ••• 1 i ...: I • I -: I... I... I .:-:-:.-: -1-:···000001 000010 000011 000100 1100101 000110 00011100100112 13 14 15 16 11001010 001011 001100 001101 0111110 001111I···: : ••• : i···: : •••• ··I··! i I ! I II··· I •• : I·:: ••• : I I • :: : I :• 20 .~ •• 22 ••• ~. ~ ·rs· Fe :·n·:.. ....... .. .. 010001 010010 010011 010100 010101 010110 010111:.: ..,.. ,:::, : : ,:::: I · . . ...... ...... . . . .·30 31 J2 33 34 35 36011000 011001 011010 011011 011100 011101 011110i : :•100000 "(·41:I~~ :=1:: ;:.;; I::::...42 4J 44 45 46100001..100010 100011 100100 100101 100110·1 :·1·:·.J•• .... ..41100111::.101000 " 101001 "101111 ": ..:........ I •• : ••••. . · . .. ." ·61 62 B3 .. .. ..11000II 110001 110010 lID 011 110100 110101 110m 110111 ". ..· ... . ...·. ... .· '.152 53 S4 55 56101010 101011 101100 101101 101110......31011111·.. ... . eI ... . ..... .. I···· ........: .. •• I ••••: I· ... •· .. ... . .....· .. ·... .. .. .. ...•· ·. . . .•••• 1..... · .. .• • ....• ... ... .... ..•· •" "" "7D13 1411111000 1110111 111010 111011 111100 111101 111110 111111FIGURE 9. MM4241ABV/MM5241ABV Vertical ScanECMA·7 Font for Scandinavian Use.. .......···o~·0000001···1: :... .... ... ... ........... .1 ••• 11 ••• I • .: I... I... I .:I I I •••: :•••• I •• •• I •••• I :••• 101 ~ W ~ ~ 00 01000001.:.000010 000011 000100 000101 000110 000111••• 11·: •• 1 •••• i : i i··:1 i ...:.:. I •• : : •• ::. : .···1i.:.12 13 14 15 16 17001000 " 001001 " 001010 001011 001100 001101 001110 001111I···: :•••: i···: :•••• ··1··· II :: Ii··· I ••: I·:: ···(1 I : I I.: 1.:.120 ·~··22···~· ~ ·rs· t ·27·010000 010001 01001n 010011 010100 010101 010110 010111: : I -::... .:.· . . .....r-:... ...30 31 32 •• : I...o I ••• 1 ·:J4011000 011001 011810 011011 " 011100 011101 "............ .l6011110·1·· ··1· •• :••41100001 100010 " 100011 100100 100101 100110 100111 ":..• ·1· •... • I· . I·51 52 53 54 55 56101000 " 101001 101010 101011 101100 1011111 101110 101111 "..... .: ..... ..... .: :.... .......::.·1·: •••••• : ..... .....:: ' .. I :::.....:. ···r •...::•..: I&0 61 &2 U " ~ ~ U·..... ......110001 110001 110010 110011 110100 110101 110110 110111..... •... 1 •I : ••• .: .: ... .... ..... ....73111000 111001 111D10 111011 11110D ".. ·100000.. .. :·: .:......10 71 72.....n...011111.:.....:.. :. :: :.:.:.....43 44 45 46:.. .... ....:.... .... .15 16 11111101 wIn 111111FIGURE 10. MM4241AI;JW/MM5241ABW Vertical·ScanECMA·7 Font for German UseFIGURE 11. MM4241ABX/MM5241ABX Vertical·ScanECMA·7 Font for General European Use(French, British, Italian)270

~ ____ .... _________ ~~~C~ATE... ... .... ... ... ..... ..... ...:... . 1 ..... 1 I •.... : I .!.: ... I... . I... .. I .:•••• : ::••••••••·1••• :•••• : •••.:00 01 ~ ro ~ ~ ~ ~.:. .... .... ...·......i ..: ... I.··: I·:·! I:. :: :... . ............ . ...llUnOOO 000001 000010 000011 000100 000101 000110 000111· . ·..n 12 13 14 1& 16 11IW1UOO 001001 001010 001011 001100 001101 001110 001111'"I···: :...: I···: :......!.. I II II I... :.::.: : ::: I::: ..... : ....... : ..... ::..:m 21 22 23 N 2~ 26 n...11111000 UIOOOI 010010 010100 010101 010111........ . . ...... .:. .. :. :. .: .· . . .....i3D 31 32i· .·".:.. ... .. .::I ··1 :.... I .....01100U 011010 0111111 ".. . .34 35 36011100 011101 011110". ...... . ::·i·· ··1·. ..:....011111.. ...... ......... . . .42 43 44 45 46100000 100001 100010 100011 100100 100101 100110..:....: . ..:.:....51· 52 53 S4 §5 5& 57101000 101001 101010 101011 101100 101101 101110 101111......& ..... ..... .: I··.. ........:I.··! • •••• .: ::.L ••••• :... • ..... ..:.. :.... ..... : ....: :...: !" M ~ ~ M ~ " ~....... .110000 110001 110010 110011 110100 110101 110lID 1101110000 o •O··...... .... ·.00 0 0.· 011 1214n111010 " 111001 111010 111011 " 111100 111101 " 111110 " 111111.. .. ...... •••• 1 ..:0· ....-41100111..:. .FIGURE 12. MM4241ABY/MM5241ABY Vertical-Scan ECMA-7 Font for Spanish Usel>ZICJ'I.....l>3(1)...(;'m::;,m::;,a.m... co'0(1)m::;,."o::;,...enPEDESTAL DISPLAYNEXTCHARACTERFIGURE 13a_ Sawtooth Vertical ScanFIGURE 13b. Pedestal Vertical ScanCHARACTERGENERATORINPutCHARACTERDATALEFT/RIGHTSHIFTERZAXISMODULATIONL,X·AXISINCREMENTr-... --=,,--.... +---------IMOVEALONGTOPORBOTTOMOFPEOESTALILINECOUNTERLINEDIVIDERDOT/COLUMNDIVIDERFIGURE 14. Conversion of Sawtooth Output to Pedestal ScanCUSTOM FONTSThe two ROMs can also be custom-programmedto provide special characters, or fonts larger than5 x 7. The MM4240/MM5240 actually stores 645 x 8 characters or character segments and theMM4241/MM5241 stores 64 8 x 6 characters orsegments. They are not limited to 5 x 7 and 7 x 5.For example, the extra height may be used in anotherwise 5 x 7 font to drop the tails of commas,sem icolons and lower-case letters below the bottomline of the capital letters. Fonts as large as 16 x 12are entirely practical without additional controllogic, using the chip-enable feature of fourMM 5241 s. Large-font organ izations are discussed inAN-40.271

BriefsJANUARY 1970...aTRIG FUNCTION GENERATORS 0Accuracy is the major design variable of trigonometriclookup tables built with MaS read-onlymemories. Only a few ROMs are needed for mostpractical applications, but accuracy can be madeto increase very rapidly with memory capacity ifinterpolation techniques are used.For instance, without interpolation a single1024-bit ROM can store 128 angular incrementsand generate an 8-bit output that wi II be betterthan 99.9% of the handbook value (Table 1).BINARY DECIMALADDRESS DEGREES OUTPUT SINE0 0 . 00000000 0.0001 0.7 .00000011 0.0122 1.4 . 00000110 0.0233 2.1 .00001001 0.035127 89.3 .11111111 0.996r----;,-,I II II II IIIIITl(a)12-1ITWlRED·OROUTPUTE ~'-' ,-,,-,,~3:oenttlCD~-I....cC'."C:::sn~.o:::sCi)CD:::sCD....m...o....tnTABLE 1. MM422BM/MM522BM Sine Function GeneratorIf one simply cascaded ROMs to improve inputresolution and output accuracy for a high-accuracytrig solution (X=sin 0) as in Figure 1, large numbersof ROMs might be needed. This 24-ROMsystem stores 2048 12-bit values of sin x (or othertrig functions), giving angular resolution of 1 partin 2" (0.05%) and output accuracy of 1 part in2' 2 (0.024%). The system in Figure 2 has thesame resolution and is accurate to the limit of its12 output bits (0.024%), which makes it just asgood. But it only requires four 1024-bit ROMs andthree 4-bit TTL full adders, so it only costs aboutone-fifth as much as the more obvious solution ofFigure 1.~-~-,-----,,.,,,Instead of producing x = sin 0, the Figure 2 systemdivides the angle into two parts and implementsthe equationx = sin 0 = sin (M + L)= sin M cos L + cos M sin LIt can be programmed for any angular range.Assume the range is 0 to 90 degrees and let M bethe 8 most significant bits of 0 and L be the 3 leastsignificant bits of 0 (0 being the 11-bit inputan gu I a r inc r e ments, equal to 90° /2048, or0.044 deg.) as in Table 2.With an 8-bit address, the three 256x4 ROMs willgive the '12-bit value of sin M at increments ofM = 90° /28, or 0.352 deg. The cos L can only varybetween 1 and 0.99998. So we assume cos L=1and store values of sin M at 0.352 deg. resolution(b)FIGURE 1. Conventional 2048-Incremjlnt Sine Table Uses24 ROMsin the top three ROMs, reducing the equation tosin 0 = sin M + cos M sin LValues of the second term are stored in the fourthROM. The maximum value of the second term inth e above equation can only be cos Msin L= 0.00539 where cos Mmax = 1, sin Lmax= 0.00539. This is the maximum value to be addedto sin M above. Only the five least significant bits273

o.-..-....CDmeno::Eof a 12-bit output are needed to form the maximumoutput, so an MM522 is used in its 128x8configuration..IIU1'I1011_01ITSI_.ct..._....._.I~"tARRY OUTPUT.....ADDER~Ul...CARRYIN'UTCARRY OUTPUT......"'DOER_IllADDER~OUTCARRYIIilPUT!:OUTCARRYINfUTt'r'r',-Ir',~r',-.,-.r'rIoI~nrnMADDRESS M. L0 01 1 L: 0.044 02 1 03 1 14 1005 1 o 16 1 1 01 1 1 18 1 000 M: 0.352 0~9 1 0 0 1r- 16 1 0 00032 100 00064 1 000 000128 1 0 000 o 0 0256 1 0 o 0 0 0 000512 100 o 000 o 0 01024 1 000 o 0 0 0 o 0 02048-1 1 1 1 I, 1 1 1 1 1 1 1TABLE 2. Programming of 2048-lncrement Sine Tablesin L=O, and sin x=sin M to 12-bit accuracy. Thenthe error rises to a limit of near 0.002% at everyeighth increment where L is 0.352-0.044. Thiserror can be halved by adjusting the fourth ROM'soutput so thatsin (J = sin M + cos (M-2.81°) sin L3lUSTItIIITl-1IIn.IIIIIOOE)~linlJ1)(IIIIIODE ......._I"·U)"L3MIIIU1 ......"'M_/J~.. M+",IM.-UJ"LFIGURE 2. Four-ROM Lookup Table Generates 2048Values of Sin x by Interpolation Technique.Let the 4 most significant bits of M be called M4and the angle at these increments be Xm = 90° /24= 5.63 deg. Sin L (the 3 least significant bits of (J)has the same maximum as before and cos M4 has amaximum of cos 5.63 deg. = 0.99517, and continuingas follows:cos (11.26) = 0.98076cos (16.89) = 0.95686cos (84.37) = 0.09810through the 16 increments of M4. Nowsin (J = sin M + cos M4 sin Land the appropriate cos M sin L values are storedin the fourth ROM. In effect, we have divided the0° to 90° sine curve into 16 slope sectors with M4,each sector into 16 subsections with M, and eachsubsection into'8 interpolation segments with L.Since we are using an approximation, accuracy isnot quite as good as the Figure 1 system. Theadditional error term is cos L, assumed 1 butactually is a variable between 1 and 0.99998. Atevery eighth increment, L is zero, making cos MIf five ROMs are used-four MM521's and all eightoutputs of the MM522-15-bit accuracy can beachieved, and thus improving the accuracy by afactor of eight. The resolution could also besmaller, of course, if the angular range weresmaller 'as in an application involving a sensor witha limited field of view. Variations of the systemcould be used to space the increments irregularlyto compensate for sensor nonlinearities, to improveaccuracy in specific angular ranges.This example has a binary fraction output, like thesine function generator in Table 1. For instance,the 8-bit output at the 64th increment representingsin x = sin 45° is 10110101. This equals1 X Tl + 0 X 2-2 + 1 X 2-3 + 1 X T4 + 0 X T S+ 1 X T6 + 0 X 2- 7 + 1 X 2- 8 , wh ich reduces to181/256 or 0.7070. Handbooks give the four-placesine of 45° as 0.7071, so at this increment theoutput is accurate to approximately 0.01 %. Thistable, the MM422BM/MM522BM. is used in fastFourier transform. radar. and other signal-processingapplications.Other standard tables that are available off theshelf include an arctan generator, several codegenerators (EBCDIC to ASCII, BCD to Selectric,and Selectric to BCD) and ASCII-addressed charactergenerators for electronic, electrical and electromechanicaldisplay and printout systems. Allinterface with TTL logic and operate off 12-voltpower supplies. Write for data sheets, or use one ofour programming tables to jot down any specialinput-output logic functions you need.274

MASK PROGRAMMING SPECIALIZESMOS SHIFT REGISTER DESIGNSA quick, economical way of customizing MOSshift register bit lengths is programming the metallizationmask, the mask that defines the thin-filmwiring pattern etched on the silicon wafer- Metallizationetching is the most convenient process stepto specialize because it is consistent from waferto wafer and is the last major process step beforetesting_Utilizing this technique, National Semiconductorhas developed two variable-length dynamic MOSregister designs. Both of them, MM4007/MM5007and MM4019/MM5019, are bipolar compatible.Dual registers 20 to 256 bits long, single registers40 to 512 bits long, and a variety of taps andpinouts provide the system designer with a methodof obtaining custom length shift registers quicklyand at reasonable cost.Up to metal masking, wafer design and fabricationare standardized. No time is lost-or money spentindeveloping custom arrays or tuning up theprocess. Automatic test systems further reduceturnaround time and production costs.Programming the metallization mask mainly involvesrouting signal connections past selectedstorage cells to adjust total register length to thedesired number of cells. Wire-bonding changesprovide output tap options.DUAL REGISTER DESIGNSBasically, each of the variable-length types is adual register (Figure 1 and Table 1A).BriefsSEPTEMBER 1971There are enough storage cells,· I/O stages, clockand power supply lines on each MM4007 chipto make up to two 100-bit registers. The minimumlength of each register half, MA and Me, is 20 bits.The programmable parts, P A and Pe, may be 0 to80 bits long. Lengths need not be equal. Forinstance, register A may be 29 bits and register B76 bits (P A = 9, Pe = 56).v ••VssTOP VIEWFIGURE 1. Dual Shift RegistersAn MM4019/MM5019 chip is similarly organized,except that MA and Me are 40 bits and P A andPe vary from 0 to 216 bits. Again, lengths maybe unequal, such as 240 bits in the A half and 136bits in the B half.Clock and supply line pin locations are standardized,but I/O pinouts are selectable. The I/Oterminals on the chip may be bonded to packagepins which are more convenient for the PC boardlayout. For example, a couple of board feedthroughsmight be eliminated by bonding the Aregister input to Pin 7 (rather than Pin 1) if datacomes in from the right and exits on the left. Or,A and B could share an input pin when they havethe same signal source....CD......a~3:men~......~oCCm33~CCrn'CCD(')mNCDen_.....r+:DCDCCenr+CD...c_.CDenCC~enA. DUAL REGISTERSTABLE 1 ~egister Length OptionsMM4007/MM5007MM4019IMM5019M P TOTAL M P TOTAL(BITS) (BITS) (BITS) (BITS) (BITS) (BITS)A Register 20 Ot080 20 to 100 40 Oto 216 40 to 256B Register 20 Oto 80 20 to 100 40 Oto 216 40 to 256B. SINGLE REGISTERSMA+MB PA +PB MA+MB PA + PB40 o to 160 40 to 200 80 o to 432 80t0512c. TAPPED SINGLE REGISTERSTotal register length same as single registers with tap locations determined by either half of the dual registers.275

enctJ)enQ)Ca-Q)...entJ)Q)a:enQ)Nco(JQ)Q.entJ)cEEcoa-tJ)oa-Il.~enCO:?!....Q)a-meno:?!SINGLE-REGISTER OPTIONSSince clock rates are synchronized by the commonclock inputs, the registers may also be seriallyconnected inside the package, as diagrammed inFigure 2. One output is internally connected tothe other input.This extends the maximum length of an MM4007/MM5007 to 200 bits and the MM4019/MM5019maximum to 512 bits. However, each half stillhas the same minimum, so the minimums become40 and 80 bits, respectively (Table 18). Again,the customer specifies the most convenient I/Opin connections.VssTOP VIEWFIGURE 2aVssTOP VIEWFIGURE 2bFIGURE 2. Single RegistersGoing to the output tap designs of Figure 3takes only one more wire bond; from the firstregister output to any available pin. Tap locationsare selected by specifying the bit lengths of eachof the dual registers. For example, an MM5007105 bits long may be tapped at any stage from20 to 85 bits. Generally, this flexibility makesinput taps unnecessary-an output at 29 bits ina 105-bit register usually serves the same purposeas an input at 76 bits.OUTPUTTAPNCVGGNC2 6 OUTPUT BVssTOP VIEWFIGURE 3aVGGOUTPUT A 2 6TOP VIEWFIGURE 3bOU11'UTTAPFIGURE 3. Output Tap OptionsOPERATING CHARACTERISTICSAll specifications, except bit lengths, are the sameas those of other MM4000/MM5000 series dynamicshift registers with the same number of I/O stages.Clock-line capacitance, power dissipation, as wellas other AC and DC parameters, are independentof the lengths programmed. This is accomplishedby standardizing clock and supply wiring patternsto achieve minimum turnaround time and cost.The MM4007/MM5007 and MM4019/MM5019 arefabricated using a low-threshold, p-channel enhancement-modetechnology developed for theMM4000/MM5000 series of registers. This meansthat they are bipolar compatible, sensing TTL orDTL data without input pull·up resistors anddriving TTL or DTL loads without output pull·down resistors. They operate on standard +5Vand -12V supplies. The clock frequency rangeis also the same, from 300 Hz to 2.5 MHz,guaranteed.Either TO-99 or dual· in-line packages may bespecified. MM4007 and MM4019 operate at -55°Cto +125°C. MM5007 and MM5019 are commericaltypes, specified for -25°C to + 70°C.276

ORDERING INFORMATIONWhen ordering, indicate the appropriatepart number followed by the packagedesignation, e.g., MM5230D.PACKAGEDESIGNATIONND0FHGPACKAGE TYPEMolded Dual-in-Line PackageCavity Dual-In-Line PackageQuartz Lid Cavity Dual-in-Line Package(MM4203/MM5203 only)Flat PackageMetal Can Package12-Lead Metal Can Package (Hybrids Only)rr::::~f.Lt:i~1~ te::J ~ ...T __ ~~ ~ ...JL ~""- ~OIA.'DLEADSOrdering InformationlPhysical Dimensions14-Pin Flat Package (F)R·---: Ttr~=d~P1;'-j".SEAT,NGPLANElnlili-.L m1 '":!!!-n-n.OI6UU~ O~t+ :.:4-Lead Metal Can Package (H)Dr--- M'::-11mr; .. ,1 -1It'".085' ~~1214.".t...• D75WW+'MAX t." 1 [IIU- -.;r,:;MAX , .on~_.~~:~f-.::~ 1 i:: f- ~ ~ •. ""Io......Q.CD::lCO::l....o...3CI)roto·::l".":::r

W r-------------------------------------------------------------,Co.- wCG)Ecasuw.c>a.........c.2...as..E....oc.-..C)cG)'EoHi==R UH18-Pin Molded Dual-In-Line Package INIT1~I '~'=3~'~' ~·~'~·~·=·~I1~'~1ao'"~ r--+----' \ Ii J ' ~ ~, '[[1::]::11 l 3 4 i I 1 B !"'LI' ~'.~ IFt r!=mmnBI~."o.'10 .0401.010 .IS0 j~ T _----L---'-1--.1 ,..---I 1 ----l 1.",1_ Il.o"TVP ---i TVP1----.... ::::---4 ~.". --I 1-.'01'" --II-.m.", ........ ----124-Pin Molded Dual-In-Line Package INIT1·~I' . ~~.18-Pin Cavity Dual-In-Line Package 101T10 .",..,J11.• 1.111-----1.+- I I \ Tvvnvnvnnl\--m:---j -l0~~1- -H-'111~.-~ ~.~~===------.Im,-,.,,-I' ~~"1i"iT""'ImI, I24-Pin Cavity Dual-In-Line Package 101"I24-Pin Cavity Dual-In-Line Package 1011""1'rffiikmffiW---=r=='·"·.L---=:J -T.~-J.,,,L ~l. .."24-Pin Quartz Lid Cavity Dual-In-Line Package IQI278

Clock Repetition Rate: The range of clock frequenciesfor which register operation is guaranteed.Clock Frequency cJ>t: The range of clock frequencieswhich register operation is guaranteed.Maximum clock frequencies are dependent uponminimum and maximum clock pulsewidth restrictions,as presented by the Guaranteed OperatingCurves.Clock Delay C/>d: C/>d is defined to be that minimumamount of time that must expire after C/>1 hasundergone a V",L to V"'H transition and the startof a C/>2 V",H to V"'L transition. The same spacingsapply, when C/>2 preceeds C/>1 •Clock Phase Delay C/>d, ifid: The time between theVC/>H levels of C/>IN and C/>OUT- C/>d is the time betweenthe trailing edge of C/>IN and the leadingedge of C/>OUT. ~d is the time between the trailingedge of C/>OUT and the leading edge of C/>IN'Clock Pulse Risetime, t,,,,: The time delay betweenthe 1 0% and 90% voltage points on the clock pulseas it traverses between its logic V"'L and logic V",Hlevels.Clock Pulse Falltime, tf",: The time delay betweenthe 1 0% to 90% voltage points on the clock pulseas it traverses between its logic V",H and logic V"'Llevels.Clock Pulse Width, C/>pw: The duration of timethat the clock pulse is greater than 1.5V.Clock Input Levels: The voltage levels (logic V'" Lor V"'H) which the clock driver must assume toinsure proper device operation.Clock Control Setup Time, tcs: The time prior tothe clock Low to High transition at which theclock control must be at its desired logic level.Clock Control Hold Time, tch: The time after theHigh to Low transition for which the clock controlmust be held at its desired logic level.Data Setup Time, tm: The tir;ne prior to the clockHigh to Low transition at which the data inputlevel must be present to guarantee being clockedinto the register by that clock pulse.Data Pulse Width, tdw: The time during;which thedata pu Ise is in its V I H or V I L state.Data Hold Time, ~h: The time after the clockHigh to Low transition which the data input levelmust be held to guarantee being clocked into theregister by that clock pulse.Data Input Voltage Levels: The voltage levels(logic V I L or V I H) which the data input terminalmust assume to insure proper logic inputs.Definition of TermsData Output Voltage Levels: The output voltagelevels (logic Va L or Va H) which the output willassume under normal operating conditions.Data Input Capacitance: The capacitance betweenthe data input terminal and ground referencemeasured at 1 MHz.Output Resistance to Ground: The resistancebetween the output terminal and ground with theoutput in the logic Va H state.Partial Bit Times TIN, TOUT: The time betweenleading edges of clocks, measured at the VC/>Hlevels. TIN is the time between the leading edge ofC/>IN and the leading edge of C/>OUT' TouT is thetime between the leading edge of C/>OUT and theleading edge of C/>IN'Output Sink Current: The current which flowsinto the output terminal of the register when theoutput is a logical low level. Conventional currentflow is assumed.Output Source Current: The current which flowsout of the output terminal of the register when theoutput is a logical High level. Conventional currentflow is assumed.Input Voltage Levels: The logical Low level, VILor VC/>L is the more negative level. This level isgenerally referred to as a TTL or DTL logical "0"and an MOS logical ",". The logical High level,.VIH or V~H is the more positive level. This level isgenerally referred to as a TTL or DTL logical ","and an MOS logical "0".Output Voltage Levels: The logical Low level,VOL, is the more negative level. This is the state inwhich the output is capable of sinking current.The logical High level, VOH , is the more positivelevel. This is the state in which the output iscapable of sourcing current.VGG Current Drain: The average current fl9W outof the V GG terminal of the package with the outputopen circuited.Power Supply Voltage, VGG: The negative powersupply potential required for proper device operation;referenced to Vss.Power Supply Return, VSS: The Vss terminal isthe reference point for the device. It must alwaysbe the most positive potential applied to thedevice.Vss Current Drain: The average current flow intothe Vss terminal of the package. It is equal to thesum of the IGG and 100 currents.Power Supply Voltage, V 00: The negative powersupply potential required for proper device opera·tion, referenced to Vss.cCD....~;::;: _.o~o ....-ICD...3tn279

II)E...Q).......oc::o+Jc::....Q)oClock Input Voltage Levels, V¢HV¢l: The voltagelevels (logic "1" or "0") which the clock drivermust assume to insure proper device operation.Data Output Voltage Levels, VOH, Val: The outputvoltage levels (logic "1" or "0") which theoutput will assume with a specified load connectedbetween output and V ss line.Data Input Voltage Levels, V1HV1l: The voltagelevels (logic "1" or "0") which the data inputterminal must assume to insure proper logicinputs.Control Release Time, te,: The maximum timethat a load command signal can be changed priorto the V¢L to V¢H transition of the output clock,rPo UT, without affecting the data during bittime tn'Control Initiate Window: The time in which a loadcommand signal must be applied to affect bit timetn' This time extends from the start of ter to thestart of tes'Control Hold Time: The time that the load commandsignal must remain stable during tn bit time.See control timing diagram.Logical "0": The logical zero voltage is the voltagestate occurring near ground. At the output ofthe device the logical zero voltage is guaranteed tobe [lot more than -1.0 volt under worst case conditionsof power supply and ambient temperature.The input requirements are guaranteed so that anyvoltage up to -1.5 volts will be interpreted as alogical zero. This implies a 0.5 volt noise immunityfor the logical zero state.Logical "1": The logical one voltage is the morenegative voltage state occurring near the negativesupply (V D D) value. At the output of the devicethe logical one voltage is guaranteed to be not lessthan -8.0 volts under worst case conditions ofpower supply and ambient temperature. The inputrequirements are guaranteed so that any voltagemore negative than -7.0 volts will be interpretedas a logical one. This implies a 1.0 volt noiseimmunity for the logical one state.ACKNOWLEDGEMENTThe following individuals have contributed to the authorship ofthe application notes and MOS briefs in this handbook: DilipBapat, Gene Carter, Don Femling, Bob Johnson, Dale Mrazek,Richard Percival and Carl Ross.Nationa I does not assume any responsibi lity for use of any circuitry described; no circuit patent licenses are impl ied; and National reserves the right, at any time without notice, to change said circuitry,280

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