w65c816s Microprocessor Data Sheet.pdf

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The Western Design Center, Inc.W65C816S Data Sheet8.19 Interrupt PrioritiesThe following interrupt priorities will be in effect should more than one interrupt occur at the same time:Highest Priority Lowest PriorityRESBABORTB, NMIB, IRQB8.20 Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit RegistersAll transfers from one register to another will result in a full 16-bit output from the source register. Thedestination register size will determine the number of bits actually stored in the destination register and thevalues stored in the processor Status Register. The following are always 16-bit transfers, regardless of theaccumulator size: TCS, TSC, TCD and TDCNote: PHP and PLP are always 8 bit operations.8.21 Stack TransfersWhen in the Emulation mode, a 01 is forced into SH. In this case, the B Accumulator will not be loaded intoSH during a TCS instruction. When in the Native mode, the B Accumulator is transferred to SH. Note that inboth the Emulation and Native modes, the full 16 bits of the Stack Register are transferred to the A, B and CAccumulators, regardless of the state of the M bit in the Status Register.8.22 BRK InstructionThe BRK instruction for the NMOS 6502, 65C02 and 65C816 is actually a 2 byte instruction. The NMOSdevice simply skips the second byte (i.e. doesn’t care about the second byte) by incrementing the programcounter twice. The 65C02 and 65C816 does the same thing except the assembler is looking for the second byteas a “signature byte”. With either device (NMOS or CMOS), the second byte is not used. It is important torealize that if a return from interrupt is used it will return to the location after the second or signature byte.8.23 Accumulator switching from 8 bit to 16 bitCare must be taken when switching from 16 bit mode to 8 bit mode then to 16 bit mode. The B register isrestored so that the following code shows a potential problem:Here BOB = $2301 and NOT $000VLONGA ONREP #$20LDA #$2345STAMIKELONGA PFFSEP #$20LDA #$01STASAMLONGA ONREP #$20STABOBThe Western Design Center W65C816S 60
The Western Design Center, Inc.W65C816S Data Sheet9 HARD CORE MODEL9.1 W65C816 Core Information• The W65C816S core uses the same instruction set as the W65C816S• The only functional difference between the W65C816S and W65C816S core is the RDY pin. TheW65C816S RDY pin is bi-directional utilizing an active pull- up. The W65C816S core RDYfunction is split into 2 pins, RDYIN and WAITN. The WAITN output goes low when a WAIinstruction is executed.• The W65C816S core will be a smaller die since the I/O buffers have been removed.• The outputs are the N-channel and P-channel output transistors drivers.• The following inputs, if not used, must be held in the high state: RDY input, IRQB, MIB, BEand ABORTB.The timing of the W65C816S core is the same as the W65C816S.•10 SOFT CORE RTL MODEL10.1 W65C816 Synthesizable RTL-Code in Verilog HDLThe RTL-Code (Register Transfer Level) in Verilog is a synthesizable model. The behavior of this model isequivalent to the original W65C816S hard core. The W65C816S RTL-Code is available as the core model andthe W65C816S standard chip model. The standard chip model includes the soft core and the buffer ring inRTL-Code. Synthesizable cores are useful in ASIC design.The Western Design Center W65C816S 61
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