w65c816s Microprocessor Data Sheet.pdf

The Western Design Center, Inc.Table 6-7 (continued)Address Mode Note Cycle VPB MLB VDA16a. Direct, X d,xADC, AND, BIT, CMP, EOR, LDALDY, ORA, SBC, STA, STY, STZ,12 OpCodes,2 bytes, 4,5,and 6 cycles(2)(1)16b. Direct, X (R-M-W) d,xASL, DEC, INC, LSR, ROL, ROR,6 OpCodes, 2 bytes, 6,7,8 and 9 cycles (2)17. Direct, Y d,yLDX, STX2 OpCodes, 2 bytes, 4,5 and 6 cycles (2)18.Immediate #ADC, AND, BIT, CMP, CPX, CPY,EOR, LDA, LDX, LDY, ORA, REP,SEC, SEP14 OpCodes, 2 and 3 bytes, 2 and 3cycles19a. Implied iCLC, CLD, CLI, CLV, DEX, DEY,INX, INY, NOP, SEC, SED, SEI,TAX, TAY, TCD, TCS, TDC, TSC,TSX, TXA, TXS, TXY, TYA, TYX,XCE25 OpCodes, 1 byte, 2 cycles19b. Implied iXBA1 OpCode, 1 byte, 3 cycles19c. Stop the ClockSTP1 OpCode1 byte RESB=13 cycles RESB=0RESB=0RESB=1(See 22a. Stack Hardware Interrupt)19d. Wait for InterruptWAI1 OpCode,1 byte3 cycles IRQB, NMIB(1)(3),(17)(1)(1)(1)(6)RDY=1(9)RDY=1RDY=0RDY=1122a344a122a344a56a6122a344a122a121231231c1b1a11231111111111111111111111111111111111111111111111111110000011111111111111111111111111000111000110111000111001010010000011001(14)VPA(14)1100001100000001100001111010010000011001Address Bus(15)PBR,PCPBR,PC+1PBR,PC+1PBR,PC+10,D+DO+X0,D+DO+X+1PBR,PCPBR,PC+1PBR,PC+1PBR,PC+10,D+DO+X0,D+DO+X+10,D+DO+X+10,D+DO+X+10,D+DO+XPBR,PCPBR,PC+1PBR,PC+1PBR,PC+10,D+DO+Y0,D+DO+Y+1PBR,PCPBR,PC+1PBR,PC+2PBR,PCPBR,PC+1PBR,PCPBR,PC+1PBR,PC+1PBR,PCPBR,PC+1PBR,PC+1PBR,PC+1PBR,PC+1PBR,PC+1PBR,PC+1PBR,PCPBR,PC+1PBR,PC+1PBR,PC+1W65C816S Data SheetData BusOpCodeDOIOIOData LowData HighOpCodeDOIOIOData LowData HighIOData HighData LowOpCodeDOIOIOData LowData HighOpCodeIDLIDHOpCodeIOOpCodeIOIOOpCodeIOIORES (BRK)RES (BRK)RES (BRK)BEGINOpCodeIOIOIRQ(BRK)RWB11111/01/011111110011111/01/01111111111111111111(see Table 6-8 for abbreviationsThe Western Design Center W65C816S 46