The Western Design Center, Inc.W65C816S <strong>Data</strong> <strong>Sheet</strong>Table 6-2 Emulation Mode Vector Locations (8-bit Mode)Address Label Function00FFFE,F IRQB/BRK Hardware/Software00FFFC,D RESETB Hardware00FFFA,B NMIB Hardware00FFF8,9 ABORTB Hardware00FFF6,7 (Reserved) Hardware00FFF4,5 COP Software00FFF2,3 (Reserved)00FFF0,1 (Reserved)Table 6-3 Native Mode Vector Locations (16-bit Mode)Address Label Function00FFFE,F IRQB Hardware00FFFC,D (Reserved)00FFFA,B NMIB Hardware00FFF8,9 ABORTB00FFF6,7 BRK Software00FFF4,5 COP Software00FFF2,3 (Reserved)00FFF0,1 (Reserved)The VP output is low during the two cycles used for vector location access. When an interrupt is executed,D=0 and I=1 in Status Register P.The Western Design Center W65C816S 34
The Western Design Center, Inc.Table 6-4 OpCode MatrixW65C816S <strong>Data</strong> <strong>Sheet</strong>MSD0123456789ABCDEFLSD0 1 2 3 4 5 6 7 8 9 A B C D E FBRK s7,2BPL r2,2JSR a6,3BMI r2,2RTI s7,1BVC r2,2RTS s6,1BVS r2,2BRA r2,2 !BCC r2,2LDY #2,2BCS r2,2CPY #2,2BNE r2,2CPX #2,2BEQ r2,2ORA(d,x)6,2ORA(d),y5,2AND(d,x)6,2AND(d),y5,2EOR(d,x)6,2EOR (d),y5,2ADC(d,x)6,2ADC(d),y5,2STA(d,x)6,2STA(d),y6,2LDA (d,x)6,2LDA (d),y5,2CMP (d,x)6,2CMP (d),y5,2SBC (d,x)6,2SBC (d),y5,2COP s7,2 *ORA(d)5,2 !JSL al8,4 *AND(d)5,2 !WDM2,2 *EOR (d)5,2 !PER s6,3 *ADC(d)5,2 !BRL rl3,3 *STA (d)5,2 !LDX #2,2LDA (d)5,2 !REP #3,2 *CMP (d)5,2 !SEP #3,2 *SBC (d)5,2 !ORA d,s4,2 *ORA(d,s),y7,2 *AND d,s4,2 *AND(d,s),y7,2 *EOR d,s4,2 *EOR(d,s),y7,2 *ADC d,s4,2 *ADC(d,s),y7,2 *STA d,s4,2 *STA(d,s),y7,2 *LDA d,s4,2 *LDA(d,s),y7,2 *CMP d,s4,2 *CMP(d,s),y7,2 *SBC d,s4,2 *SBC(d,s),y7,2 *TBS d5,2 !TRB d5,2 !BIT d3,2BIT d,x4,2 !MVP xyc7,3 *MVN xyc7,3 *STZ d3,2 !STZ d,x4,2 !STY d3,2STY d,x4,2LDY d3,2LDY d,x4,2CPY d3,2PEI s6,2 *CPX d3,2PEA s5,3 *ORA d3,2ORA d,x4,2AND d3,2AND d,x4,2EOR d3,2EOR d,x4,2ADC d3,2ADC d,x4,2STA d3,2STA d,x4,2LDA d3,2LDA d,x4,2CMP d3,2CMP d,x4,2SBC d3,2SBC d,x4,2ASL d5,2 *ASL d,x6,2 *ROL d5,2 *ROL d,x6,2 *LSR d5,2 *LSR d,x6,2 *ROR d5,2 *ROR d,x6,2 *STX d3,2 *STX d,y4,2 *LDX d3,2 *LDX d,y4,2 *DEC d5,2 *DEC d,x6,2 *INC d5,2 *INC d,x6,2 *ORA [d]6,2ORA[d],y6,2AND [d]6,2AND[d],y6,2EOR [d]6,2EOR[d].y6,2ADC[d]6,2ADC[d],y6,2STA[d]6,2STA[d],y6,2LDA [d]6,2LDA[d],y6,2CMP [d]6,2CMP[d],y6,2SBC [d]6,2SBC[d],y6,2PHP s3,1CLC i2,1PLP s4,1SEC i2,1PHA s3,1CLI i2,1PLA s4,1SEI i2,1DEY i2,1TYA i2,1TAY i2,1CLV i2,1INY i2,1CLD i2,1INX i2,1SED i2,1ORA#2,2ORA a,y4,3AND#2,2AND a,y4,3EOR #2,2EOR a,y4,3ADC#2,2ADC a,y4,3BIT #2,2 !STA a,y5,3LDA#2,2LDA a,y4,3CMP #2,2CMP a,y4,3SBC #2,2SBC a,y4,3ASL A2,1INC A2,1 !ROL A2,1DEC A2,1 !LSR A2,1PHY s3,1 !ROR A2,1PLY s4,1TXA i2,1TXS i2,1TAX i2,1TSX i2,1DEX i2,1PHX s3,1 !NOP i2,1PLX s4,1 !PHD s4,1 *TCS i2,1 *PLD s5,1 *TSC i2,1 *PHK s3,1 *TCD i2,1 *RTL s6,1 *TDC i2,1 *PHB s3,1 *TXY i2,1 *PLB s4,1 *TYX i2,1 *WAI i3,1 !STP i3,1 !XBA i3,1 *XCE i2,1 *TSB a6,3 !TRB a6,3 !BIT a4,3BIT a,x4,3 !JMP a3,3JMP al4,4 *JMP (a)5,3JMP(a,x)6,3 !STY a4,3STZ a3,4 !LDY a4,3LDY a,x4,3CPY a4,3JML (a)6,3 *CPX a4,3JSR (a,x)6,3 *ORA a4,3ORA a,x4,3AND a4,3AND a,x4,3EOR a4,3EOR a,x4,3ADC a4,3ADC a,x4,3STA a4,3STA a,x5,3LDA a4,3LDA a,x4,3CMP a4,3CMP a,x4,3SBC a4,3SBC a,x4,3ASL a6,3ASL a,x7,3ROL a6,3ROL a,x7,3LSR a6,3LSR a,x7,3ROR a6,3ROR a,x7,3STX a4,3STZ a,x5,3 !LDX a4,3LDX a,y4,3DEC a6,3DEC a,x7,3INC a6,3INC a,x7,30 1 2 3 4 5 6 7 8 9 A B C D E F* = Old instruction with new addressing modes! = New InstructionORA al5,4 *ORA al,x5,4 *AND al5,4 *AND al,x5,4 *EOR al5,4 *EOR al,x5,4 *ADC al5,4 *ADC al,x5,4 *STA al5,4 *STA al,x5,4 *LDA al5,4 *LDA al,x5,4 *CMP al5,4 *CMP al,x5,4 *SBC al5,4 *SBC al,x5,4 *MSD0123456789ABCDEFThe Western Design Center W65C816S 35
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