w65c816s Microprocessor Data Sheet.pdf

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The Western Design Center, Inc.Table 5-2 W65C816S AC CharacteristicsW65C816S Data SheetSymbol Parameter 5.0 +/- 5% 3.3 +/- 10% 3.0 +/- 5% 2.5 +/- 5% 1.8 +/- 5% Units14MHz 8MHz 8MHz 4MHz 2MHzMin Max Min Max Min Max Min Max Min MaxVDD 4.75 5.25 3.0 3.6 2.85 3.15 2.375 2.675 1.71 1.89 VtCYC Cycle Time 70 DC 125 DC 125 DC 250 DC 500 DC nStPWL Clock Pulse Width Low 35 - 63 - 63 - 125 - 250 - nStPWH Clock Pulse Width High 35 - 62 - 62 - 125 - 250 - nStF,tR Fall Time, Rise Time - 5 - 5 - 5 - 5 - 5 nStAH A0-A15 Hold Time 10 - 10 - 10 - 20 - 40 - nStADS A0-A15 Setup Time - 30 - 40 - 40 - 75 - 150 nStBH BA0-BA7 Hold Time 10 - 10 - 10 - 20 - 40 - nStBAS BA0-BA7 Setup Time - 33 - 40 - 40 - 75 - 150 nStACC Access Time 30 - 70 - 70 - 130 - 365 - nStDHR Read Data Hold Time 10 - 10 - 10 - 20 - 40 - nStMDS Write Data Delay Time - 30 - 40 - 40 - 70 - 140 nStDHW Write Data Hold Time 10 - 10 - 10 - 20 - 40 - nStPCS Processor Control Setup Time 10 - 15 - 15 - 30 - 60 - nStPCH Processor Control Hold Time 10 - 10 - 10 - 20 - 40 - nStEH E, MX Output Hold Time - 5 - 5 - 5 - 5 - 5 nStES E, MX Output Setup Time 10 - 15 - 15 - 30 - 60 - nSCEXT Capacitive Load (1) - 35 - 35 - 35 - 35 - 35 PftBVD be TO Valid Data (2) - 25 - 30 - 30 - 60 - 120 nS1. Test or loading on all outputs.2. BE to High Impedance State is not testable but should be the same amount of time as BE to Valid Data.The Western Design Center W65C816S 30
The Western Design Center, Inc.W65C816S Data SheettFtRPHI2tPWLtPWHRWB, SYNCVPB, MLB A0-A15Read DatatDHRWrite DatatDHWtAHtADStACCtMDSWrite DatatDSRtAHsee note 1tDHRtDHWIRQB, NMIB, RESB,RDYtPCStPCHABORTBtPCSM/XMIEHtESXXtEHMMtEStEHEtEHBEDatatBVD1. Timing measurement points are 50% VDD.Figure 5-1 General Timing DiagramThe Western Design Center W65C816S 31
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w65c816s Microprocessor Data Sheet.pdf

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