w65c816s Microprocessor Data Sheet.pdf

The Western Design Center, Inc.W65C816S Data SheetDirect Indirect-(d)With Direct Indirect ((d)) addressing the second byte of the instruction is added to the Direct Register to form apointer to the low-order 16 bits of the effective address. The Data Bank Register contains the high-order 8 bits ofthe effective address.Instruction: OpCode offsetthen: + DBROperand Address:Direct Register+ offset00 (direct address)effective addressDirect-dWith Direct (d) addressing the second byte of the instruction is added to the Direct Register (D) to form theeffective address. An additional cycle is required when the Direct Register is not page aligned (DL not equal 0).The Bank register is always 0.Instruction: OpCode offsetDirect Register+ offsetOperand Address: 00 effective addressImmediate-#With Immediate (#) addressing the operand is the second byte (second and third bytes when in the16-bit mode) of the instruction.Implied-iImplied (i) addressing uses a single byte instruction. The operand is implicitly defined by the instruction.Program Counter Relative Long-rlThe Program Counter Relative Long (rl) addressing mode is used with only with the unconditional Branch Longinstruction (BRL) and the Push Effective Relative instruction (PER). The second and third bytes of theinstruction are added to the Program Counter, which has been updated to point to the OpCode of the nextinstruction. With the branch instruction, the Program Counter is loaded with the result. With the Push EffectiveRelative instruction, the result is stored on the stack. The offset is a signed 16-bit quantity in the range from-32768 to 32767. The Program Bank Register is not affected.The Western Design Center W65C816S 25