w65c816s Microprocessor Data Sheet.pdf

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The Western Design Center, Inc.4 ADDRESSING MODESW65C816S Data SheetThe W65C816S is capable of directly addressing 16 MBytes of memory. This address space has specialsignificance within certain addressing modes, as follows:4.1 Reset and Interrupt VectorsThe Reset and Interrupt Vectors use the majority of the fixed addresses between 00FFE0 and 00FFFF.4.2 StackThe Stack may be use memory from 000000 to 00FFFF. The effective address of Stack and Stack Relativeaddressing modes will be always be within this range.4.3 DirectThe Direct addressing modes are usually used to store memory registers and pointers. The effective addressgenerated by Direct, Direct,X and Direct,Y addressing modes is always in Bank 0 (000000-00FFFF).4.4 Program Address SpaceThe Program Bank register is not affected by the Relative, Relative Long, Absolute, Absolute Indirect, andAbsolute Indexed Indirect addressing modes or by incrementing the Program Counter from FFFF. The onlyinstructions that affect the Program Bank register are: RTI, RTL, JML, JSL, and JMP Absolute Long. Programcode may exceed 64K bytes although code segments may not span bank boundaries.4.5 Data Address SpaceThe Data Address space is contiguous throughout the 16 MByte address space. Words, arrays, records, or anydata structures may span 64 KByte bank boundaries with no compromise in code efficiency. The followingaddressing modes generate 24-bit effective addresses:• Absolute a• Absolute a,x• Absolute a,y• Absolute Long al• Absolute Long Indexed al,x• Direct Indexed Indirect (d,x)• Direct Indirect (d)• Direct Indirect Indexed (d),y• Direct Indirect Long [d]• Direct Indirect Long Indexed [d],y• Stack Relative Indirect Indexed (d,x),yThe following addressing mode descriptions provide additional detail as to how effective addresses arecalculated. Twenty-four addressing modes are available for the W65C816S.The Western Design Center W65C816S 20
The Western Design Center, Inc.W65C816S Data SheetAbsolute -aWith Absolute (a) addressing the second and third bytes of the instruction form the low-order 16 bits of theeffective address. The Data Bank Register contains the high-order 8 bits of the operand address.Instruction: OpCode addrl addrhOperand DBR addrh addrlAbsolute Indexed Indirect-(a,x)With Absolute Indexed Indirect ((a,x)) addressing the second and third bytes of the instruction are added to the XIndex Register to form a 16-bit pointer in Bank 0. The contents of this pointer are loaded in the Program Counterfor the JMP instruction. The Program Bank Register is not changed.then:PC = (address)Instruction: OpCode addrl addrhAbs olute Indexed with X-a,xPBRaddrhaddressWith Absolute Indexed with X (a,x) addressing the second and third bytes of the instruction are added to the XIndex Register to form the low-order 16-bits of the effective address. The Data Bank Register contains thehigh-order 8 bits of the effective address.addrlX RegInstruction: OpCode addrl addrhOperand Address:DBR addrh addrl+ X Regeffective addressAbsolute Indexed with Y-a,yWith Absolute Indexed with Y (a,y) addressing the second and third bytes of the instruction are added to the YIndex Register to form the low-order 16-bits of the effective address. The Data Bank Register contains thehigh-order 8 bits of the effective address.Instruction: OpCode addrl addrhOperand Address:DBR addrh addrl+ Y Regeffective addressThe Western Design Center W65C816S 21
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