Technology of Q 2500 colour TV set

Technology of Q 2500 colour TV setThe I²C bus 1 operates with a cycle frequencyof 100 kHz.I²C bus 2 with SDA 2 and SCL 1The Sat or Twin Sat unit is controlled from theSDA 6000 via the I²C-Bus 2.There are tuning ICs in the receiver unit. Generationof the tuning voltage and control of theband and standard transfer or LNC supply onthe SAT receiver.4.2.2 IC 24C64 memoryA 24C64 64 kbit memory is used. To distinguishthis EEPROM from the similarly soundingEPROM it is given the designationEAROM.In addition to system data for the digital ICsthe EAROM also contains user specific data.This is programme related location data suchas channel, reception range, standard, etc., aswell as customer specific tuning values forbrightness, volume and contrast, for example.The 24C64 has a memory capacity of 65536bits, and is organised into 8192 x 8 bits. Thememory life is at least 10 years, with morethan 1 million write and read actions guaranteed.Inputting and outputting of data is controlledby the SDA 6000 and implemented viathe I²C bus 0. For this the CCU generates an8-bit address word preceded by a start bit.The 8-bit value is composed of a 7-bit word forthe IC address and one bit, containing the onor off command.This address word is checked by the IC's connectedto the system for conformity with theaddress words they hold, and receipt is acknowledgedby an acknowledge bit from theappropriate IC. In the socket the master IC(SDA 6000) transfers the storage location address.This address consists of two 8-bitwords, receipt of which is acknowledged by anacknowledgement bit for each bit respectively.If this occurs, the 8 data bits are transferred toor from the memory IC and receipt is confirmedby the appropriate IC.Transfer of the data described is implementedvia line SDA 0 and is synchronised by theclock on line SCL 0. After transfer of the lastacknowledgement bit, the command "Input"sets the save procedure in motion. During thesave procedure the inputs SDA and SCL of24C64 are locked, in order to prevent any externalinterference with the memory during thistime.After the start up routine the system data isread from the memory by the SDA 6000 viathe I²C bus and and then the data is transferredvia the I²C bus systems to the appropriatedigital IC's.To prevent inadvertent deletion or overwritingof the memory on start up or shutdown, theWrite Protect line pin 7 of the two EAROMs isconnected via Q 2943 to the Reset line. In thestart up and shut down phase, pin 7 of bothEAROM`s is switched to the L level. Inadvertentdeletion or overwriting is thereby prevented.In the operating state H level is appliedto pin 7.4.2.3 EPROM M 27 C 322Device specific software is held in EPROM I2926 as non-volatile data.An IC with 32 Mbit memory is used. Thememory is divided into 2097152 x 16 bit areas.Data transfer from the EPROM to the computeris implemented via connections D0 toD16. The memory addresses, from which thedata is recalled, are transferred previously vialines A0 to A 20.Document Q 2500 75 © Loewe ProCollege