Technology of Q 2500 colour TV set

Technology of Q 2500 colour TV setThe end of data transfer (Stop condition) occurson signalisation of a positive flank (L > H)on the DATA line and concurrent H level onthe clock line.SDASCLMaster-Sender/Receiver(µC)Slave-Receiver(Display)SCL frommasterSDA signalvia transmitterSDA signalvia receiverStartSSlave-Sender/Receiver(RAM)Master-Sender(µC)1 2 8 9Slave-Sender/Receiver(E/A-Interface)9th clock bit for A• Multi-sound processor MSP 3410 to IFandVF processing.• The video processor VPC 3230, I 2271 fordigitising of input signals and processing inthe main signal path. It conducts the digitalY/UV signals to the I 491 memory.• SAA 4979 for conversion of the digital Yand C signals into analogue Y, R-Y and B-Y signals and for the control of the digital100 Hz processing with the two half picturememories and the SAA 4993.• The video/deflection processor TDA 9332for generation of the RGB control signalsfor the c.r.t. plate and for generation of thedeflection pulseUp to 400 kbit/s can be transferred via the I²Cbus interface of the SDA 6000. The data andclock impulses are switched by softwareswitching logic to the respectively requiredbus connections.The CCU operates on its I2C bus outputs witha level of 3.3 V. The other ICs and componentsoperate with TTL level. Adaptation ofthe CCU level to the TTL level is by transistorsQ 2883/86/88/91 and Q 2893.The following functions are controlled via theI²C bus systems:I²C bus 0 with SDA 0 and SCL 0Only the EAROM I 2931 is connected to theI²C bus 0. This memory contains all start valuesand customer specific values. The data isselected here on start up and when makingadjustments or writing to the EAROM on shutdown and for memory processes.If a DVB module is retro-fitted the secondEAROM I 2936 is also used. Programme datafrom 220 to 1470 is stored here.• Video processor VPC 3233, I 2151 for PIPsignal processing. The digitised Y/UVsignalsare fed to the two PIP synchronousmemories I 2161/71.The I²C bus has a maximum cycle rate of 400kHz.I²C bus 1 with SDA 1 and SCL 1Just like the I²C bus 0, fixed pins are also providedfor the I²C buses 1 and 2 in the SDA6000. Buses 1 and 2 operate with a commonclock line and separate data lines. Data isswitched to the respective line for the requiredbus in an internal transfer switch.The following are connect to the I²C bus 1:• The tuning and transfer IC’s on the receiverunits in the basic board.• The transfer IC’s for video (1 x TEA 6415)and audio (TEA 6422 and TEA 6420) forthe interface on the signal board.Document Q 2500 74 © Loewe ProCollege