1. Introduction - Laboratory for Reliable Computing

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• Economics!− Product quality− Product reliabilityWhy Testing?Defect detectedduring IC testDefect detectedduring system testDefect detectedduring field testm01intro7.02 Cheng-Wen Wu, NTHU 6
Semiconductor Trends (ITRS 2005)Matel 1 Helf Pitch (nm1009080706050403020100Shrinking Pitch Size# of Wiring18.51817.51716.51615.51514.5Increasing Wiring Levels2005 2010 2015 20202005 2010 2015 2020Year of ProductionYear of ProductionGbits/cm250454035302520151050Increasing Gate DensityPower Supply Voltage (V)<strong>1.</strong>210.80.60.40.20Decreasing Supply Voltage2005 2010 2015 20202005 2010 2015 2020Year of ProductionYear of Productionm01intro7.02 Cheng-Wen Wu, NTHU 7
Page 2 and 3: • IntroductionOutline• RAM func
Page 4 and 5: • Scope of testingOutline• Defe
Page 8 and 9: Test Cost9080706050403020100Test co
Page 10 and 11: Scope of Testing• Engineering Tes
Page 12 and 13: Fault Model and Error• Fault mode
Page 14 and 15: Testing and Fault Coverage• Testi
Page 16 and 17: Defect Level and Fault CoverageRequ
Page 18 and 19: Logic Fault Modeling: Stuck-at Faul
Page 20 and 21: Fault Diagnosis• Fault detection:
Page 22 and 23: Design for Testability (DFT)• A f
Page 24 and 25: MUX ScanxCombinationalLogicCTSIM D
Page 26 and 27: Scan-Based PS-BIST with Test Points
Page 28 and 29: Embedded Memory Testing• Embedded
Page 30: Off-Line Testing of RAM• Parametr

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