1. Introduction - Laboratory for Reliable Computing

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• Scope of testingOutline• Defect level and fault coverage• Fault models− Classical faults− Switch-level faults− Timing faults− Memory faults• Test and testing• Design <strong>for</strong> testability (DFT)• <strong>Introduction</strong> to memory testingm01intro7.02 Cheng-Wen Wu, NTHU 4
Typical IC Production FlowWaferProbe Test Probe TestPackagingVisual InspectionVisual InspectionFinal Test Final TestMarkingQA Sample TestQA Sample TestShippingm01intro7.02 Cheng-Wen Wu, NTHU 5
Page 2 and 3: • IntroductionOutline• RAM func
Page 6 and 7: • Economics!− Product quality
Page 8 and 9: Test Cost9080706050403020100Test co
Page 10 and 11: Scope of Testing• Engineering Tes
Page 12 and 13: Fault Model and Error• Fault mode
Page 14 and 15: Testing and Fault Coverage• Testi
Page 16 and 17: Defect Level and Fault CoverageRequ
Page 18 and 19: Logic Fault Modeling: Stuck-at Faul
Page 20 and 21: Fault Diagnosis• Fault detection:
Page 22 and 23: Design for Testability (DFT)• A f
Page 24 and 25: MUX ScanxCombinationalLogicCTSIM D
Page 26 and 27: Scan-Based PS-BIST with Test Points
Page 28 and 29: Embedded Memory Testing• Embedded
Page 30: Off-Line Testing of RAM• Parametr

1. Introduction - Laboratory for Reliable Computing

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