1. Introduction - Laboratory for Reliable Computing

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Design for Testability (DFT)• A fault is testable if there exists a well-specifiedprocedure to expose it, which can beimplemented with a reasonable cost using currenttechnologies− A circuit is testable with respect to a fault set wheneach and every fault in this set is testable• The term DFT refers to a class of designmethodologies which put constraints on thedesign process to make test generation anddiagnosis easier• Testability = controllability + observabilitym01intro7.02 Cheng-Wen Wu, NTHU 22
DFT Dilemma• No single methodology solves all VLSI testingproblems• No single DFT technique is effective for all kindsof circuits• No DFT approach is free− Manpower and tool costs− Area overhead and performance penalty• Two classes of DFT techniques− Ad hoc guidelines− Structured (systematic) techniquesm01intro7.02 Cheng-Wen Wu, NTHU 23
Page 2 and 3: • IntroductionOutline• RAM func
Page 4 and 5: • Scope of testingOutline• Defe
Page 6 and 7: • Economics!− Product quality
Page 8 and 9: Test Cost9080706050403020100Test co
Page 10 and 11: Scope of Testing• Engineering Tes
Page 12 and 13: Fault Model and Error• Fault mode
Page 14 and 15: Testing and Fault Coverage• Testi
Page 16 and 17: Defect Level and Fault CoverageRequ
Page 18 and 19: Logic Fault Modeling: Stuck-at Faul
Page 20 and 21: Fault Diagnosis• Fault detection:
Page 24 and 25: MUX ScanxCombinationalLogicCTSIM D
Page 26 and 27: Scan-Based PS-BIST with Test Points
Page 28 and 29: Embedded Memory Testing• Embedded
Page 30: Off-Line Testing of RAM• Parametr

1. Introduction - Laboratory for Reliable Computing

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