1. Introduction - Laboratory for Reliable Computing

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Defect Level and Fault CoverageRequired FC <strong>for</strong> DL = 200 DPM.Y (%)1050909599FC(%)99.9999.9799.899.698m01intro7.02 Cheng-Wen Wu, NTHU 16
The Testing Problem• Given a set of faults in the circuit under test(CUT), how do we obtain a certain (small)number of test patterns which guarantees acertain (high) fault coverage?− What faults to test? (fault modeling)− How are test patterns obtained? (test patterngeneration)− How is test quality (fault coverage) measured?(fault simulation)− How are test vectors applied and results evaluated?(ATE/BIST)m01intro7.02 Cheng-Wen Wu, NTHU 17
Page 2 and 3: • IntroductionOutline• RAM func
Page 4 and 5: • Scope of testingOutline• Defe
Page 6 and 7: • Economics!− Product quality
Page 8 and 9: Test Cost9080706050403020100Test co
Page 10 and 11: Scope of Testing• Engineering Tes
Page 12 and 13: Fault Model and Error• Fault mode
Page 14 and 15: Testing and Fault Coverage• Testi
Page 18 and 19: Logic Fault Modeling: Stuck-at Faul
Page 20 and 21: Fault Diagnosis• Fault detection:
Page 22 and 23: Design for Testability (DFT)• A f
Page 24 and 25: MUX ScanxCombinationalLogicCTSIM D
Page 26 and 27: Scan-Based PS-BIST with Test Points
Page 28 and 29: Embedded Memory Testing• Embedded
Page 30: Off-Line Testing of RAM• Parametr

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