1. Introduction - Laboratory for Reliable Computing

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Fault Model and Error• Fault model: logical effect of a fault− Structure faults∗ Stuck-at faults: stuck-at-0 and stuck-at-1∗ Bridging (short) fault∗ Open (break) fault∗ Transistor stuck-on and stuck-open faults∗ Transition and delay faults− Functional faults∗ RAM coupling and pattern-sensitive faults∗ PLA cross-point faults• Error: manifestation of a fault that results inan incorrect module output or system statem01intro7.02 Cheng-Wen Wu, NTHU 12
Failure• Failure: deviation of a system from itsspecified behavior− Fault → error → failure• Failure mechanism: physical or chemicalprocess that causes devices to malfunction;they manifest themselves on the circuitlevel as failure modes• Failure mode: the cause of rejection offailed device (effect of failure mechanism),such as open/short interconnections, ordegraded parameter valuesm01intro7.02 Cheng-Wen Wu, NTHU 13
Page 2 and 3: • IntroductionOutline• RAM func
Page 4 and 5: • Scope of testingOutline• Defe
Page 6 and 7: • Economics!− Product quality
Page 8 and 9: Test Cost9080706050403020100Test co
Page 10 and 11: Scope of Testing• Engineering Tes
Page 14 and 15: Testing and Fault Coverage• Testi
Page 16 and 17: Defect Level and Fault CoverageRequ
Page 18 and 19: Logic Fault Modeling: Stuck-at Faul
Page 20 and 21: Fault Diagnosis• Fault detection:
Page 22 and 23: Design for Testability (DFT)• A f
Page 24 and 25: MUX ScanxCombinationalLogicCTSIM D
Page 26 and 27: Scan-Based PS-BIST with Test Points
Page 28 and 29: Embedded Memory Testing• Embedded
Page 30: Off-Line Testing of RAM• Parametr

1. Introduction - Laboratory for Reliable Computing

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