1. Introduction - Laboratory for Reliable Computing

• IntroductionOutline• RAM functional fault models & test algorithms• RAM fault-coverage analysis & test generation• Testing word-oriented & multi-port memories• Memory built-in self-test (BIST) & built-in self-diagnosis(BISD)• Memory redundancy analysis and built-in self-repair(BISR)• Memory failure analysis• RAM on-line testing• Testing non-volatile memoriesm01intro7.02 Cheng-Wen Wu, NTHU 2

Chapter 1: IntroductionCheng-Wen Wu 吳 誠 文Lab for Reliable ComputingDept. Electrical EngineeringNational Tsing Hua University

• Scope of testingOutline• Defect level and fault coverage• Fault models− Classical faults− Switch-level faults− Timing faults− Memory faults• Test and testing• Design for testability (DFT)• Introduction to memory testingm01intro7.02 Cheng-Wen Wu, NTHU 4

Typical IC Production FlowWaferProbe Test Probe TestPackagingVisual InspectionVisual InspectionFinal Test Final TestMarkingQA Sample TestQA Sample TestShippingm01intro7.02 Cheng-Wen Wu, NTHU 5

• Economics!− Product quality− Product reliabilityWhy Testing?Defect detectedduring IC testDefect detectedduring system testDefect detectedduring field testm01intro7.02 Cheng-Wen Wu, NTHU 6

Semiconductor Trends (ITRS 2005)Matel 1 Helf Pitch (nm1009080706050403020100Shrinking Pitch Size# of Wiring18.51817.51716.51615.51514.5Increasing Wiring Levels2005 2010 2015 20202005 2010 2015 2020Year of ProductionYear of ProductionGbits/cm250454035302520151050Increasing Gate DensityPower Supply Voltage (V)1.210.80.60.40.20Decreasing Supply Voltage2005 2010 2015 20202005 2010 2015 2020Year of ProductionYear of Productionm01intro7.02 Cheng-Wen Wu, NTHU 7

Test Cost9080706050403020100Test costPackage costSilicon cost0.5um0.35um0.25um0.18umm01intro7.02 Cheng-Wen Wu, NTHU 8

DFT Usage Trend% T e s t C o v e r e d b y B I S T100806040200DFT for SOC/MPU2003 2004 2005 2006 2007 2008 2009 2012 2015 2018m01intro7.02 Cheng-Wen Wu, NTHU 9

Scope of Testing• Engineering Test− Diagnostic Test∗ Fault location∗ Failure analysis∗ Design and/or process debugging• Manufacturing Test− Characterization Test∗ Performance characterization: parametric test∗ Reliability characterization: bathtub curve (aging)− Production Test∗ Simple parametric test∗ Functional test∗ Reliability screening (burn-in)m01intro7.02 Cheng-Wen Wu, NTHU 10

Fault• Fault: a physical defect in a circuit/system− Permanent fault: a fault that is continuous and stable, whosenature do not change before, during, and after testing∗ Affecting the functional behavior of the system permanently∗ A.k.a. hard fault or solid fault∗ Usually quite localized∗ Can be modeled− Temporary fault: a fault that is present only part of the time,occurring at random moments and affecting the system forfinite, but unknown, intervals of time∗ Transient fault: caused by environmental conditions∗ No well-defined fault model∗ Called soft error in RAM∗ Often assumed no permanent damage was done− Intermittent fault: caused by non-environmental conditions∗ Often repeatable∗ Can use permanent fault models and repeated test with stressm01intro7.02 Cheng-Wen Wu, NTHU 11

Fault Model and Error• Fault model: logical effect of a fault− Structure faults∗ Stuck-at faults: stuck-at-0 and stuck-at-1∗ Bridging (short) fault∗ Open (break) fault∗ Transistor stuck-on and stuck-open faults∗ Transition and delay faults− Functional faults∗ RAM coupling and pattern-sensitive faults∗ PLA cross-point faults• Error: manifestation of a fault that results inan incorrect module output or system statem01intro7.02 Cheng-Wen Wu, NTHU 12

Failure• Failure: deviation of a system from itsspecified behavior− Fault → error → failure• Failure mechanism: physical or chemicalprocess that causes devices to malfunction;they manifest themselves on the circuitlevel as failure modes• Failure mode: the cause of rejection offailed device (effect of failure mechanism),such as open/short interconnections, ordegraded parameter valuesm01intro7.02 Cheng-Wen Wu, NTHU 13

Testing and Fault Coverage• Testing is the process of determining whether adevice functions correctly or not− How much testing of an IC is enough?• Yield (Y) is the ratio of the number of good diesper wafer to the number of dies per wafer• Fault coverage (FC) is the measure of the abilityof a test set T to detect a given set of faults thatmay occur on the DUT− FC = (#detected faults)/(#possible faults)m01intro7.02 Cheng-Wen Wu, NTHU 14

Defect Level and Fault Coverage• Defect level (DL) is the fraction of bad partsamong the parts that pass all tests and areshipped− DL = 1 – Y**(1-FC)• FC refers to the real defect coverage (probabilitythat T detects any possible fault---in F or not)• DL is measured in terms of DPM (defects permillion), and typical values claimed are less than200 DPM, or 0.02%m01intro7.02 Cheng-Wen Wu, NTHU 15

Defect Level and Fault CoverageRequired FC for DL = 200 DPM.Y (%)1050909599FC(%)99.9999.9799.899.698m01intro7.02 Cheng-Wen Wu, NTHU 16

The Testing Problem• Given a set of faults in the circuit under test(CUT), how do we obtain a certain (small)number of test patterns which guarantees acertain (high) fault coverage?− What faults to test? (fault modeling)− How are test patterns obtained? (test patterngeneration)− How is test quality (fault coverage) measured?(fault simulation)− How are test vectors applied and results evaluated?(ATE/BIST)m01intro7.02 Cheng-Wen Wu, NTHU 17

Logic Fault Modeling: Stuck-at Faultabc c stuck-at 0; c s-a-0; c s/0, or c/0a b c c(a/0) c(a/1) c(b/0) c(b/1) c(c/0) c(c/1)0 00 11 01 1000100000101• Single (line) stuck-at fault: line has a constant value (0/1)• Multiple stuck fault: several single stuck-at faults occur atthe same time− For a circuit with k lines, there are 2k single stuck faults, and 3 k -1multiple stuck faults0000001100001111m01intro7.02 Cheng-Wen Wu, NTHU 18

Test• A test for a fault f in circuit C is an inputcombination for which the output(s) of C isdifferent when f is present than when it isnot− A.k.a. test pattern, test vector, or experiment− A test x detects fault f iff C(x)⊕C f(x)=1• A test set for a class of faults F is a set oftests T such that for any fault f∈F, thereexists t∈T such that t detects fm01intro7.02 Cheng-Wen Wu, NTHU 19

Fault Diagnosis• Fault detection: tells only whether a circuitis fault-free or not• Fault identification (location; isolation):provides the location and the type of thedetected fault and other related information• Fault diagnosis: includes both faultdetection and fault identificationm01intro7.02 Cheng-Wen Wu, NTHU 20

Testing• Testing is a process which includes testpattern generation, test pattern application,and output evaluation− The quality of a test set depends on its faultcoverage (FC) as well as its size− FC (typically 98-99% single stuck faults forlogic circuit) can be determined by faultsimulationm01intro7.02 Cheng-Wen Wu, NTHU 21

Design for Testability (DFT)• A fault is testable if there exists a well-specifiedprocedure to expose it, which can beimplemented with a reasonable cost using currenttechnologies− A circuit is testable with respect to a fault set wheneach and every fault in this set is testable• The term DFT refers to a class of designmethodologies which put constraints on thedesign process to make test generation anddiagnosis easier• Testability = controllability + observabilitym01intro7.02 Cheng-Wen Wu, NTHU 22

DFT Dilemma• No single methodology solves all VLSI testingproblems• No single DFT technique is effective for all kindsof circuits• No DFT approach is free− Manpower and tool costs− Area overhead and performance penalty• Two classes of DFT techniques− Ad hoc guidelines− Structured (systematic) techniquesm01intro7.02 Cheng-Wen Wu, NTHU 23

MUX ScanxCombinationalLogicCTSIM D M D M DSO1. Switch to SR mode and check SR operation2. Initialize SR---load the first pattern3. Return to normal mode and apply test pattern4. Switch to SR mode and shift out the final state whilesetting the starting state for the next test. Go to 3m01intro7.02 Cheng-Wen Wu, NTHU 24

xLFSRCircular BISTMuxSISOCombinationalLogicMISRzMISRm01intro7.02 Cheng-Wen Wu, NTHU 25

Scan-Based PS-BIST with Test PointsLFSR PIPSMUXto cps CombinationalLogic SCfrom ops POMISRSource: K.-T. Tim Cheng, UCSBm01intro7.02 Cheng-Wen Wu, NTHU 26

Why Investigating Memory Testing?• Memory testing is a more and more important issue− RAMs are key components for electronic systems∗ In Alpha 21264, cache RAMs represent 2/3 transistors and 1/3 area;in StrongArm SA110, the embedded RAMs occupy 90% area [Bhavsar,ITC-99]∗ Memory cores will represent more than 90% of SOC area by 2010[ITRS 2001]− Memories represent about 30% of the semiconductor market− Embedded memories are dominating the chip yield• Memory testing is more and more difficult− Growing density, capacity, and speed− Emerging new architectures and technologies− Embedded memories: access, diagnostics & repair, heterogeneity,custom design, power & noise, scheduling, compression, etc.• Cost drives the need for more efficient test methodologies− IFA, fault modeling and simulation, test algorithm development andevaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.m01intro7.02 Cheng-Wen Wu, NTHU 27

Embedded Memory Testing• Embedded memory testing is increasingly difficult− High bandwidth (speed and I/O data width)− Heterogeneity and plurality− Isolation (accessibility)− AC test, diagnostics, and repair• Test automation is required− Failure analysis, fault simulation, ATG, anddiagnostics− BIST/BIRA/BISR generationm01intro7.02 Cheng-Wen Wu, NTHU 28

Typical RAM Production FlowWaferFull Probe TestLaser RepairPackagingMarkingPost-BI TestBurn-In (BI)Pre-BI TestFinal TestVisual InspectionQA Sample TestShippingm01intro7.02 Cheng-Wen Wu, NTHU 29

Off-Line Testing of RAM• Parametric Test: DC & AC• Reliability Screening− Long-cycle testing− Burn-in: static & dynamic BI• Functional Test− Device characterization∗ Failure analysis− Fault modeling∗ Simple but effective (accurate & realistic?)− Test algorithm generation∗ Small number of test patterns (data backgrounds)∗ High fault coverage∗ Short test timem01intro7.02 Cheng-Wen Wu, NTHU 30