Understanding Smart Sensors - Nomads.usp

88 Understanding Smart SensorsTable 4.3ADC ArchitecturesADC TypeTypicalNumber of BitsRelativeConversion RateRelativeDie AreaFolding (flash) 8 Fastest 14Successive approximation 12 Fast 10(hardware driven)Sigma-delta (Σ-∆) 16 Slow 8Successive approximation 12 Slow 7(software driven)Dual slope 12 Slowest 3Single slope 12 Slowest 1x(t)Σy(t)∆1-bitD/AF sy(n)16.4 MHz(1 bit)DigitaldecimationfilterF:f s s16(x)n100 kHz(16 bits)First-order Σ∆ - loopFigure 4.13 Block diagram of a first-order Σ-∆ ADC.block diagram of an oversampled first-order Σ-∆ ADC [26]. The analog inputis summed at the input node with the difference of the output of the 1-bitdigital-to-analog converter (DAC). The resulting signal is provided to an integratorand then to a 1-bit quantizer (ADC). A second-order Σ-∆ consists of twointegrators, two summers, and the 1-bit quantizer. Second- or third-order Σ-∆modulators reduce the baseband noise level even further than a first-order Σ-∆unit.The output of the Σ-∆ converter is averaged by applying it to the input ofa digital decimation filter. The digital decimation filter performs three functions.First, it removes out-of-band quantization noise, which is equivalent to