TSC2101-Audio Codec w/ Integrated Headphone Speaker Amp ...

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SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comBITNAMERESETVALUEREAD/WRITEFUNCTIOND10 XSTAT 0 R X Data Register Status0 => No new data is available in X−data register1 => New data for X−coordinate is available in registerNote: This bit gets cleared only after the converted data of X coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D9 YSTAT 0 R Y Data Register Status0 => No new data is available in Y−data register1 => New data for Y−coordinate is available in registerNote: This bit gets cleared only after the converted data of Y coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D8 Z1STAT 0 R Z1 Data Register Status0 => No new data is available in Z1−data register1 => New data is available in Z1−data registerNote: This bit gets cleared only after the converted data of Z1 coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D7 Z2STAT 0 R Z2 Data Register Status0 => No new data is available in Z2−data register1 => New data is available in Z2−data registerNote: This bit gets cleared only after the converted data of Z2 coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D6 BSTAT 0 R BAT Data Register Status0 => No new data is available in BAT data register1 => New data is available in BAT data registerNote: This bit gets cleared only after the converted data of BAT has been completely read out of theregister. This bit is not valid in case of buffer mode.D5 0 R ReservedD4 AX1STAT 0 R AUX1 Data Register Status0 => No new data is available in AUX1−data register1 => New data is available in AUX1−data registerNote: This bit gets cleared only after the converted data of AUX1 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D3 AX2STAT 0 R AUX2 Data Register Status0 => No new data is available in AUX2−data register1 => New data is available in AUX2−data registerNote: This bit gets cleared only after the converted data of AUX2 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D2 T1STAT 0 R TEMP1 Data Register Status0 => No new data is available in TEMP1−data register1 => New data is available in TEMP1−data registerNote: This bit gets cleared only after the converted data of TEMP1 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D1 T2STAT 0 R TEMP2 Data Register Status0 => No new data is available in TEMP2−data register1 => New data is available in TEMP2−data registerNote: This bit gets cleared only after the converted data of TEMP2 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D0 0 R Reserved50
www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 02H: Buffer ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15 BUFRES 0 R/W Buffer Reset.0 => Buffer mode is disabled and RDPTR, WRPTR & TGPTR set to their reset value.1 => Buffer mode is enabled.D14 BUFCONT 0 R/W Buffer Mode Selection0 => Continuous conversion mode.1 => Single shot mode.D13−D11 BUFTL 000 R/W Trigger Level TL selection of Buffer used for SAR ADC000 => 8001 => 16010 => 24011 => 32100 => 40101 => 48110 => 56111 => 64D10 BUFOVF 0 R Buffer Full Flag0 => Buffer is not full.1 => Buffer is full. This means buffer contains 64 unread converted data.D9 BUFEMF 1 R Buffer Empty Flag0 => Buffer is not empty.1 => Buffer is empty. This means there is no unread converted data in the buffer.D8−D0 0’s R ReservedREGISTER 03H: Reference ControlBITNAMERESETVALUEREAD/WRITED15−D6 0’s R ReservedD5 0 R/W Reserved. Always write 0 to this bit.FUNCTIOND4 VREFM 0 R/W Voltage Reference Mode. This bit configures the VREF pin as either external reference or internalreference.0 => External reference1 => Internal referenceD3−D2 RPWUDL 00 R/W Reference Power Up Delay. These bits allow for a delay time for measurements to be made afterthe reference powers up, thereby assuring that the reference has settled00 => 0 µs01 => 100 µs10 => 500 µs11 => 1000 µsNote: This will be valid only when device is programmed for internal reference and Bit D1 = 1, i.e.,reference is powered down between the conversions if not required.D1 RPWDN 1 R/W Reference Power Down. This bit controls the power down of the internal reference voltage.0 => Powered up at all times.1 => Powered Down between conversions.Note: When D4 = 0 i.e. device is in external reference mode then the internal reference is powereddown always.D0 IREFV 0 R/W Internal Reference Voltage. This bit selects the internal voltage for TSC ADC.0 => VREF = 1.25 V1 => VREF = 2.50 V51
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