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TSC2101-Audio Codec w/ Integrated Headphone Speaker Amp ...

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www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004WCLKth(WS)ts(WS)th(WS)ts(WS)BCLKtH(BCLK)tL(BCLK)td(DO−BCLK)tP(BCLK)SDOUTSDINts(DI)th(DI)Figure 4. DSP Timing in Slave ModeTypical Timing Requirements (see Figure 4)PARAMETER(1)IOVDD = 1.1 V IOVDD = 3.3 VMIN MAX MIN MAX UNITStH(BCLK) BCLK high period 40 35 nstL(BCLK) BCLK low period 40 35 nstP(BCLK) BCLK period 80 80 nsts(WS) WCLK setup 6 6 nsth(WS) WCLK hold 6 6 nstd(DO−BCLK) BCLK to DOUT delay 30 15 nsts(DI) SDIN setup 6 6 nsth(DI) SDIN hold 6 6 nstr Rise time 5 4 nstf Fall time 5 4 ns(1) These parameters are based on characterization and are not tested in production.13

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