TSC2101-Audio Codec w/ Integrated Headphone Speaker Amp ...

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004 FEATURESStereo Audio Playback Up to 48 kspsMono Audio Record up to 48 kspsIntegrated PLL for Audio Clock GenerationProgrammable Gain AmplifiersHardware Automatic Gain ControlProgrammable Digital Audio EffectsProcessingStereo Headset InterfaceCellular Headset Interface8-Ω Speaker Driver32-Ω Receiver DriverInterface with MicrophoneAuto-Detection of Headset and Button PressSupports Both Cap and Cap-Less Interfacefor HeadsetProgrammable Audio Routing4-Wire Touch Screen InterfaceIntegrated Touch Screen Processor WithFully Automated Modes of OperationProgrammable Converter Resolution, Speed,and AveragingProgrammable Autonomous Timing ControlDirect Battery MeasurementBuilt-In Buffer for Touch Screen DataSPI Serial InterfaceLow PowerFull Power-Down Control48-Pin QFN PackageAPPLICATIONS Personal Digital Assistants Smart Cellular Phones MP3 PlayersDESCRIPTIONThe TSC2101 is a low-power highly integrated highperformance codec and touch screen controller, whichsupports stereo audio DAC, mono audio ADC and SARADC.The TSC2101 features a high-performance audio codecwith 16, 20, 24, or 32-bit stereo playback, mono recordfunctionality at up to 48 ksps. The device integratesseveral analog features such as support for headsetinterface, cellular headset interface, microphone interface,and speaker and receiver drivers. The device supportsauto detection of headset and button press without anyglue logic. The TCS2101 has fully programmable audio.The digital audio data format is programmable to work withpopular audio standard protocols (I2S, DSP, left/rightjustified) in master or slave mode, and also includes anon-chip PLL for flexible clock generation capability.The TSC2101 contains a 12-bit 4-wire resistive touchscreen converter complete with drivers, and interfaces tothe host controller through a standard SPI serialinterface. The on-chip processor provides extensivefeatures specifically designed to reduce host processorand bus overhead, with capabilities that include fullyautomated operating modes, programmable conversionresolution up to 12 bits, programmable sampling rates upto 125 kHz, programmable conversion averaging, andprogrammable on-chip timing generation.The TSC2101 offers battery measurement inputs capableof reading battery voltages up to 6 V, while operating atonly 3 V. It also has an on-chip temperature sensorcapable of reading 0.3°C resolution. The TSC2101 isavailable in a 48-lead QFN.US Patent No. 6246394Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.SPI is a trademark of Motorola. Copyright © 2004, Texas Instruments Incorporated

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible todamage because very small parametric changes could cause the device not to meet its published specifications.PACKAGE/ORDERING INFORMATIONPRODUCTPACKAGEPACKAGEDESIGNATOROPERATINGTEMPERATURE RANGETSC2101 QFN-48 RGZ −40°C to +85°CORDERING NUMBER TRANSPORT MEDIATSC2101IRGZ Rails, 52TSC2101IRGZR Tape and Reel, 2500PIN ASSIGNMENTSQFN PACKAGE(TOP VIEW)IOVDDPWR_DNRESETGPIO2GPIO1AVDD2AVSS2AVDD1X+Y+X−Y−48 47 46 45 44 43 42 41 40 39 38 3713623533443353263173082992810271126122513 14 15 16 17 18 19 20 21 22 23 24DRVSS2OUT8PBVDDOUT8NDRVSS1VGNDSPKFCDRVDDSPK2SPK1OUT32NMIC_DETECT_INAVSS1VREFVBATAUX2AUX1BUZZ_INCP_OUTCP_INMICIN_HNDMICBIAS_HNDMICIN_HEDMICBIAS_HEDDVSSDVDDBCLKWCLKSDINSDOUTMCLKSCLKMISOMOSISSPINTDAV2

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comELECTRICAL CHARACTERISTICSAt +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise notedPARAMETER TEST CONDITIONS MIN TYP MAX UNITSTOUCH SCREENAUXILIARY ANALOG INPUTInput voltage range 0 +VREF VInput capacitance AUX1/2 input selected as input by touch-screen25 pFInput leakage current±1 µABATTERY MONITOR INPUTSInput voltage range 0.5 6.0 VInput leakage current Battery conversion not selected ±1 µAAccuracyVariation across temperature after systemcalibration at 4 V battery voltage and room±15 mVtemperatureTOUCH SCREEN A/D CONVERTERResolution Programmable: 8-, 10-,12-bits 8 12 BitsNo missing codes 12-Bit resolution 11 BitsIntegral nonlinearity −5 5 LSBOffset error −6 6 LSBGain error −6 6 LSBNoise 50 µVrmsVOLTAGE REFERENCE (VREF)VREF output programmed = 2.5 V 2.3 2.5 2.7Voltage rangeVREF output programmed = 1.25 V 1.25VExternal reference 1.1 2.5 VReference drift Internal VREF = 1.25 V 50 ppm/°CCurrent drainExtra current drawn when the internal reference isturned on.750 µAAUDIO CODECADC DECIMATION FILTER CHARACTERISTICSFilter gain from 0 to 0.39 Fs ±0.1 dBFilter gain at 0.4125 Fs −0.25 dBFilter gain at 0.45 Fs −3.0 dBFilter gain at 0.5 Fs −17.5 dBFilter gain from 0.55 Fs to 64 Fs −75 dBGroup delay 17/Fs sec4

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004ELECTRICAL CHARACTERISTICS (continued)At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwisenoted (continued)PARAMETER TEST CONDITIONS MIN TYP MAX UNITSMICROPHONE INPUT TO ADCMICIN_HED 1020 Hz sine wave input,Fs = 48 kspsFull-scale input voltage (0 dB) 0.707 VrmsInput common mode 1.5 VSNRMeasured as idle channel noise, 0 dB gain,A-weighted80 90 dBATHD 0.63 Vrms input, 0-dB gain −81 −72 dB217 Hz, 100 mV on AVDD1/2(1) 55 dBPSRR1020 Hz, 100 mV on AVDD1/2(1) 55 dBMute attenuationInput resistanceOutput code with 0.63 Vrms sine wave input at0000H1 kHzOnly ADC on 15 50 kΩADC and Sidetone on 8 16 kΩInput capacitance 10 pFHEADSET MICROPHONE BIASRegister 1DH/Page 2, D7−D8=00 3.3Voltage rangeRegister 1DH/Page 2, D7−D8=01 2.5 VPSRRRegister 1DH/Page 2, D7−D8=1X 2217 Hz, 100 mV on AVDD1/2 55217 Hz, 100 mV on BVDD 741020 Hz, 100 mV on AVDD1/2 551020 Hz, 100 mV on BVDD 74Sourcing current Voltage drop

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004ELECTRICAL CHARACTERISTICS (continued)At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted(continued)PARAMETER TEST CONDITIONS MIN TYP MAX UNITSDAC HEADPHONE OUTPUTLoad = 16 Ω (single-ended), 50 pFFull-scale output voltage (0dB) 0.848 VrmsOutput common mode 1.5 VSNR Measured as idle channel noise, A-weighted 85 95 dBATHD −1 dBFS Input, 0-dB gain −80 −60 dBPSRR217 Hz, 100 mV onAVDD1/AVDD2/DRVDD(1) 55 dB1020 Hz, 100 mV onAVDD1/AVDD2/DRVDD(1) 55 dBInterchannel isolation Coupling from ADC to DAC 80 dBMute attenuation 100 dBMaximum output power Per channel 44 mWDigital volume control −63.5 0 dBDigital volume control step size 0.5 dBChannel separation Between SPK1 and SPK2 −75 dBDAC SPEAKER OUTPUTLoad = 8 Ω (differential), 50 pFFull-scale output voltage (0 dB) 1.838 VrmsOutput common mode 1.75 VSNR Measured as idle channel noise, A-weighted 90 98 dBATHD −1 dBFS Input, 0-dB gain −74 −55 dB217 Hz, 100 mV on AVDD1/2 70PSRR217 Hz, 100 mV on BVDD 701020 Hz, 100 mV on AVDD1/2 701020 Hz, 100 mV on BVDD 70dBInterchannel isolation Coupling from ADC to DAC 90 dBMute attenuation 100 dBMaximum output power 400 mWCELLPHONEMIC INPUT TO CPOUT1020-Hz Sine wave input on MICIN_HND,load on CP_OUT = 10 kΩ, 50 pFFull-scale input voltage (0 dB) 0.707 VrmsInput common mode 1.5 VFull-scale output voltage (0 dB) 0.707 VrmsOutput common mode 1.5 VSNR Measured as idle channel noise, A-weighted 80 89 dBATHD 0 dBFS Input, 0-dB gain −73 −60 dB217 Hz, 100 mV on AVDD1/AVDD2/DRVDD 43PSRR1020 Hz, 100 mV onAVDD1/AVDD2/DRVDD43dBInterchannel isolation CP_IN to CP_OUT 75 dBMute attenuation CP_OUT muted 100 dB(1) DAC PSRR measurement is calculated as:PSRR 20 log 10 VSIG supV SPK126

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004ELECTRICAL CHARACTERISTICS (continued)At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted(continued)PARAMETER TEST CONDITIONS MIN TYP MAX UNITSCP_IN TO 32Ω RECEIVER (SPK1−OUT32N)1020-Hz Sine wave input on CP_IN, Load onSPK1−OUT32N = 32 Ω (differential), 50 pFFull-scale input voltage (0 dB) 0.707 VrmsInput common mode 1.5 VFull-scale output voltage (0 dB) 1.697 VrmsOutput common mode 1.5 VSNR Measured as idle channel noise, A-weighted 85 97 dBATHD 0 dBFs input, 0 dB gain −77 −60 dB217 Hz, 100 mV on AVDD1/AVDD2/DRVDD 43PSRR1020 Hz, 100 mV ondB43AVDD1/AVDD2/DRVDDInterchannel isolation MICIN to RECEIVER 75 dBMute attenuation 100 dBMaximum output power 82 mWDIGITAL INPUT/OUTPUTLogic familyLogic level: VIH IIH = +5 µA 0.7IOVDD VCMOSVIL IIL = +5 µA −0.3 0.3IOVDD VVOH IOH = 2 TTL loads 0.8IOVDD VVOL IOL = 2 TTL loads 0.1IOVDD VCapacitive load 10 pF7

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comSPI TIMING DIAGRAMLSBOUT/SStSt tdLagtSPISELZ S t Lead sckSt ft rSCLKtSwsckt wsckSPISELZ SSMISO SPICLKSt v t ho t disSPISELZ EMSBOUT BIT6...1L t aMOSISPISELZt sut hiMSB IN BIT6...1 LSB INTYPICAL TIMING REQUIREMENTSAll specifications typical at 25°C, DVDD = 1.8 V(1)PARAMETERIOVDD = 1.1 V IOVDD = 3.3 VMIN MAX MIN MAX UNITStwsck SCLK Pulse width 30 18 nstLead Enable Lead Time 18 15 nstLag Enable Lag Time 18 15 nsttd Sequential Transfer Delay 18 15 nsta Slave MISO access time 18 15 nstdis Slave MISO disable time 18 15 nstsu MOSI data setup time 6 6 nsthi MOSI data hold time 6 6 nstho MISO data hold time 4 4 nstv MISO data valid time 25 13 nstr Rise Time 6 4 nstf Fall Time 6 4 ns(1) These parameters are based on characterization and are not tested in production.10

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004WCLKth(WS)ts(WS)th(WS)ts(WS)BCLKtH(BCLK)tL(BCLK)td(DO−BCLK)tP(BCLK)SDOUTSDINts(DI)th(DI)Figure 4. DSP Timing in Slave ModeTypical Timing Requirements (see Figure 4)PARAMETER(1)IOVDD = 1.1 V IOVDD = 3.3 VMIN MAX MIN MAX UNITStH(BCLK) BCLK high period 40 35 nstL(BCLK) BCLK low period 40 35 nstP(BCLK) BCLK period 80 80 nsts(WS) WCLK setup 6 6 nsth(WS) WCLK hold 6 6 nstd(DO−BCLK) BCLK to DOUT delay 30 15 nsts(DI) SDIN setup 6 6 nsth(DI) SDIN hold 6 6 nstr Rise time 5 4 nstf Fall time 5 4 ns(1) These parameters are based on characterization and are not tested in production.13

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comTYPICAL CHARACTERISTICS1.51AVDD1/AVDD2 = 3.3 V,TA = 25C,IR = 2.5 V0.5LSB0−0.5−1−1.50 500 1000 1500 2000 2500 3000 3500 4000CODEFigure 5. SAR INL (T A = 25 C, Internal Reference = 2.5 V, 12 bit, AVDD1/AVDD2 = 3.3 V)10.5AVDD1/AVDD2 = 3.3 V,TA = 25C,IR = 2.5 VLSB0−0.5−10 500 1000 1500 2000 2500 3000 3500 4000CODEFigure 6. SAR DNL (T A = 25 C, Internal Reference = 2.5 V, 12 bit, AVDD1/AVDD2 = 3.3 V)Power − mW2.42.221.81.61.41.210.80.60.40.2AVDD1/AVDD2 = 3.3 V,TA = 25C00 10 20 30 40 50 60 70 80Sampling Rate − KspsFigure 7. SAR ADC Power Consumption vs Speed (T A = 25 C, External Reference, Host Controlled AUXConversion, AVDD1/AVDD2 = 3.3 V)14

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 20040−20−40AVDD1/AVDD2 = 3.3 V,TA = 25C,−60dB−80−100−120−140−1600 500 1000 1500 2000 2500 3000 3500 4000f − Frequency − HzFigure 8. ADC FFT Plot at 8 ksps (T A = 25 C, −1 dB, 1 kHz input, AVDD1/AVDD2 = 3.3 V)0−20−40AVDD1/AVDD2 = 3.3 V,TA = 25C,−60dB−80−100−120−140−1600 5000 10000 15000 20000f − Frequency − HzFigure 9. ADC FFT Plot at 48 ksps (T A = 25 C, −1 dB, 1 kHz input, AVDD1/AVDD2 = 3.3 V)9089.5AVDD1/AVDD2 = 3.3 V,TA = 25C,Dynamic Range − dB8988.58887.58786.5868 18 28 38 48Sampling Rate − KspsFigure 10. ADC Dynamic Range vs Sampling Rate (T A = 25 C, AVDD1/AVDD2 = 3.3 V)15

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004dB200−20−40−60−80−100−120−140AVDD1/AVDD2 = 3.3 V,TA = 25C,RL = 16 −1600 5000 10000 15000 20000f − Frequency − HzFigure 11. DAC FFT Plot (T A = 25 C, −1 dB, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V, R L = 16 Ω)THD − Total Hormonic Distortion − dB−77−78−79−80−81−82−83AVDD1/AVDD2 = 3.3 V,TA = 25C,RL = 16 −845 10 15 20 25 30 35 40 45Power − mWFigure 12. THD vs Power on SPK1/2 (T A = 25 C, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V, R L = 16 Ω)16

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004THD − Total Hormonic Distortion − dB−60−65−70−75−80−85AVDD1/AVDD2/DRDD = 3.3 V,BVDD = 3.9 VTA = 25C,RL = 8 −900 50 100 150 200 250 300 350 400Power − mWFigure 13. THD vs Power on Loudspeaker Driver (T A = 25 C, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V,BVDD = 3.9 V, R L = 8 Ω)450400Max Power Output − mW3503002502001502.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1BVDD − VFigure 14. Loudspeaker Driver Output Power vs BVDD (T A = 25 C, 1 kHz Input,AVDD1/AVDD2/DRVDD = 3.3 V, R L = 8 Ω, THD −40 dB)17

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comOVERVIEW18The TSC2101 is a highly integrated stereo audio DAC and mono audio ADC with touch screen controller forportable computing, communication and entertainment applications. A register-based architecture easesintegration with microprocessor-based systems through a standard SPI bus. All peripheral functions arecontrolled through the registers and on-board state machines.The TSC2101 consists of the following blocks: Audio Codec Headset and Button Detection Touch Screen Interface Battery Monitors Auxiliary Inputs Temperature MonitorCommunication to the TSC2101 is via a standard SPI serial interface. This interface requires that the SlaveSelect signal (SS) be driven low to communicate with the TSC2101. Data is then shifted into or out of theTSC2101 under control of the host microprocessor, which also provides the serial data clock.Control of the TSC2101 and its functions is accomplished by writing to different registers in the TSC2101. Asimple command protocol is used to address the 16-bit registers. Registers control the operation of the SARADC and audio codec.OPERATION—AUDIO CODECAUDIO ANALOG I/OThe TSC2101 has stereo audio DAC and mono audio ADC. It supports a wide range of analog interface tosupport different headsets and analog outputs. The TSC2101 has features to interface output drivers (8-Ω,16-Ω, 32-Ω) and Microphone PGA to Cell-phone. The TSC2101 also has a virtual ground (VGND) output, whichcan be optionally used to connect to the ground terminal of a speaker of headphone to eliminate the ac-couplingcapacitor needed at the speaker or headphone output. A special circuit has also been included in the TSC2101to insert a short keyclick sound into the stereo audio output, even when the audio DAC is powered down. Theykeyclick sound is used to provide feedback to the used when a particular button is pressed or item is selected.The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency,duration, and amplitude.AUDIO DIGITAL I/O INTERFACEDigital audio data samples can be transmitted between the TSC2101 and the CPU via the serial bus (BCLK,WCLK, SDOUT, SDIN) that can be configured to transfer digital data in four different formats: Right justified(RJF), Left justified (LJF), I 2 S and DSP. The four modes are MSB first and operate with variable word lengthbetween 16/20/24/32 bits. The TSC2101’s audio codec can operate in master or slave mode, depending onits register settings. The word-select signal (WCLK) and bit clock signal (BCLK) are configured as outputs whenthe bus is in master mode. They are configured as inputs when the bus is in slave mode. The WCLK isrepresentative of the sampling rate of the audio ADC/DAC and is synchronized with SDOUT. Although theSDOUT signal can contain two channels of information (a left and right channel), the TSC2101 sends the sameADC data in both channels. ADC/DAC Sampling RateThe audio-control-1 register (Register 00H, Page 2) determines the sampling rates of DAC and ADC. Thesampling frequency is scaled down from the reference rate (Fsref). The reference rate is usually either 44.1kHz or 48 kHz which can be selectable using bit D13 of the register Audio Control 3 (06H/Page2). The ADCand DAC can operate with either common WCLK (equal sampling rates) or separate GPIO1 (For ADC) andWCLK (For DAC) for unequal sampling rates. When the audio codec is powered up, it is by default configuredas an I 2 S slave with both the DAC and ADC operating at Fsref.

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Word Select SignalsThe word select signal (WCLK) indicates the channel being transmitted:— WCLK = 0: left channel for I 2 S mode;— WCLK = 1: right channel for I 2 S mode.For other modes refer to the timing diagrams below. Bitclock (BCLK) SignalIn addition to being programmable as master or slave mode, the BCLK can also be configured in two transfermodes, 256-S transfer mode and continuous transfer mode, which are described below. These modes areset using bit D12 of control register 06H/page 2. 256-S Transfer ModeIn the 256-S mode, the BCLK rate always equals 256 times the WCLK frequency. In the 256-S mode, thecombination of ADC/DAC sampling rate equal to Fsref (as selected by bit D5D0 of control register 00H/page2) and left-justified mode is not supported. If IOVDD is equal to 1.1 V, then ADC/DAC sampling rate should beless than 39 kHz for all modes except the left justified mode where it should be less than 24 kHz. Continuous Transfer ModeIn the continuous transfer mode, the BCLK rate always equals two-word length times the frequency ofWCLK. Right Justified ModeIn right-justified mode, the LSB of left channel is valid on the rising edge of BCLK preceding, the falling edgeon WCLK. Similarly the LSB of right channel is valid on the rising edge of BCLK preceding the rising edge ofWCLK.1/fsWCLKBCLKSDIN/SDOUTLeft ChannelRight Channel0 n n−1 n−2 2 1 0n n−1 n−2 2 1 0MSBLSBFigure 15. Timing Diagram for Right-Justified Mode19

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comLeft Justified ModeIn left-justified mode, the MSB of right channel is valid on the rising edge of BCLK, following the falling edge onWCLK. Similarly the MSB of left channel is valid on the rising edge of BCLK following the rising edge ofWCLK.1/fsWCLKBCLKSDIN/SDOUTn n−1 n−2 2 1 0 n n−1 n−2 2 1 0MSBLeft ChannelLSBRight ChannelFigure 16. Timing Diagram for Left-Justified ModeI 2 S ModeIn I 2 S mode, the MSB of left channel is valid on the second rising edge of BCLK, after the falling edge onWCLK. Similarly the MSB of right channel is valid on the second rising edge of BCLK, after the rising edge ofWCLK.1/fsnn−1WCLKBCLKSDIN/SDOUT1 clock before MSBn n−1 n−2 2 1 0 n n−1 n−2 2 1 0MSBLeft ChannelLSBRight ChannelFigure 17. Timing Diagram for Right-Justified ModeDSP ModeIn DSP mode, the falling edge of WCLK starts the data transfer with the left channel data first and immediatelyfollowed by the right channel data. Each data bit is valid on the falling edge of BCLK.1/fsnWCLKBCLKSDIN/SDOUTLeft ChannelRight Channel1 0 n n−1 n−2 2 1 0 n n−1 n−2 2 1 0 n n−1 n−2LSB MSBLSB MSBLSB MSBFigure 18. Timing Diagram for DSP Mode20

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004AUDIO DATA CONVERTERSThe TSC2101 includes a stereo audio DAC and a mono audio ADC. Both ADC and DAC can operate with amaximum sampling rate of 53 kHz and support all audio standard rates of 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz. By utilizing the flexible clock generation capability and internalprogrammable interpolation, a wide variety of sampling rates up to 53 kHz can be obtained from many possibleMCLK inputs. In addition, the DAC and ADC can independently operate at different sampling rates as indicatedin control register 00H/page 2.When the ADC or DAC is operating, the TSC2101 requires an applied audio MCLK input. The user should alsoset bit D13 of control register 06H/page 2 to indicate which Fsref rate is being used. If the codec ADC or DACis powered up, then the touch screen ADC uses MCLK and BCLK for its internal clocking, and the internaloscillator is powered down to save power.Typical audio DACs can suffer from poor out-of-band noise performance when operated at low sampling rates,such as 8 kHz or 11.025 kHz. The TSC2101 includes programmable interpolation circuitry to provide improvedaudio performance at such low sampling rates, by first upsampling low-rate data to a higher rate, filtering toreduce audible images, and then passing the data to the internal DAC, which is actually operating at the Fsrefrate. This programmable interpolation is determined using bit D5D3 of control register 00H/page 2.For example, if playback of 11.025 kHz data is required, the TSC2101 can be configured such that Fsref = 44.1kHz. Then using bit D5D3 of control register/page 2, the DAC sampling rate (Fs) can be set to Fsref/4, or FS= 11.025 kHz. In operation, the 11.025 kHz digital input data is received by the TSC2101, upsampled to 44.1kHz, and filtered for images. It is then provided to the audio DAC operating at 44.1 kHz for playback. In reality,the audio DAC further upsamples the 44.1 kHz data by a ratio of 128 x and performs extensive interpolationfiltering and processing on this data before conversion to a stereo analog output signal.Phase Locked Loop (PLL)The TSC2101 has an on chip PLL to generate the needed internal ADC and DAC operational clocks from awide variety of clocks that may be available in the system. The PLL supports an MCLK varying from 2 MHz to100 MHz and is register programmable to enable generation of required sampling rates with fine precision.ADC and DAC sampling rates are given byDAC_Fs FsrefN1andADC_Fs FsrefN2Where, Fsref must fall between 39 kHz and 53 kHz, and N1, N2=1, 1.5, 2, 3, 4, 5, 5.5, 6 are registerprogrammable.The PLL can be enabled or disabled using register programming. When PLL is disabledFsref MCLK128 QQ = 2, 3…17— Note: For ADC, with N2 = 1.5 or 5.5, odd values of Q are not allowed.— In this mode, the MCLK can operate up to 100 MHz, and Fsref should fall between 39 kHzand 53 kHz.When PLL is enabled21

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004The PGA, for microphone and AUX Inputs, allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB.The PGA gain changes are implemented with an internal soft-stepping. This soft-stepping ensures that volumecontrol changes occur smoothly with no audible artifacts. Upon reset, the PGA gain defaults to a mute condition,and upon power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag (D0control register 04H/Page 2) is set whenever the gain applied by PGA equals the desired value set by theregister. The soft-stepping control can be disabled by programming D15=1 in register 1DH of Page 2. Whensoft stepping is enabled and ADC power down register is written, MCLK should be running to ensure thatsoft-stepping to mute has completed. MCLK can be shut down once Mic PGA power down flag is set.The PGA, for Cell phone Input (CP_IN) allows gain control from –34.5 dB to 12 dB in steps of 0.5 dB. The PGAgain changes are implemented with an internal soft−stepping. This soft-stepping ensures that volume controlchanges occur smoothly with no audible artifacts. Upon reset, the PGA gain defaults to a mute condition, andupon power down, the PGA soft-steps the volume to mute before shutting down. A read−only flag (D7 controlregister 1FH/Page 2) is set whenever the gain applied by PGA equals the desired value set by the register. Thesoft-stepping control can be disabled by the programming D12=1 in register 1DH of Page 2. When soft-steppingis enabled and ADC power down register is written, MCLK should be running to ensure that soft-stepping tomute has completed. MCLK can be shut down once Cell PGA power down flag is set.Delta-Sigma ADCThe analog-to-digital converter has a delta-sigma modulator with a 128 times oversampling ratio. The ADC cansupport maximum output rate of 53 kHz.Decimation FilterThe audio ADC includes an integrated digital decimation filter that removes high frequency content anddownsamples the audio data from an initial sampling rate of 128 times Fs to the final output sampling rate ofFs. The decimation filter provides a linear phase output response with a group delay of 17/Fs. The –3 dBbandwidth of the decimation filter extends to 0.45 Fs and scales with the sample rate (Fs).Programmable High Pass FilterThe ADC channel has a programmable high-pass filter whose cutoff frequency can be programmed throughcontrol register. By default the high pass filter is off. The high-pass filter is a first order IIR filter. This filter canbe used to remove the DC component of the input signal and offset of the ADC channel.Automatic Gain Control (AGC)The TSC2101 includes Automatic gain control (AGC) for Microphone Inputs (MICIN_HED or MICIN_HND) andCell-phone input (CP_IN). AGC can be used to maintain nominally constant output signal amplitude whenrecording speech signals. This circuitry automatically adjusts the PGA gain as the input signal becomes overlyloud or very weak, such as when a person speaking into a microphone moves closer or farther from themicrophone. The AGC algorithm has several programmable settings, including target gain, attack and decaytime constants, noise threshold, and max PGA applicable that allow the algorithm to be fine tuned for anyparticular application. The algorithm uses the absolute average of the signal (which is the average of theabsolute value of the signal) as a measure of the nominal amplitude of the output signal.Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level.The TSC2101 allows programming of eight different target gains, which can be programmed from –5.5 dB to–24 dB relative to a full-scale signal. Since the TSC2101 reacts to the signal absolute average and not to peaklevels, it is recommended that the target gain be set with enough margin to avoid clipping at the occurrenceof loud sounds.Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud.It can be varied from 8 ms to 20 ms.Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be variedin the range from 100 ms to 500 ms.Noise threshold determines level below which if the input speech average value falls, AGC considers it as asilence and hence brings down the gain to 0 dB in steps of 0.5 dB every FS and sets noise threshold flag. Thegain stays at 0 dB unless the input speech signal average rises above noise threshold setting. This ensures23

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comthat noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm isprogrammable from −30dB to −90 dB for microphone input, and from −30 dB to −60 dB for cell-phone input.When AGC Noise Threshold is set to −70 dB, −80 dB, or −90 dB, the microphone input Max PGA applicablesetting must be greater than or equal to 11.5 dB, 21.5 dB, or 31.5 dB respectively. This operation includesdebounce and hysteresis to avoid the AGC gain from cycling between high gain and 0 dB when signals are nearthe noise threshold level. When noise threshold flag is set, status of gain applied by AGC and saturation flagshould be ignored.Max PGA applicable allows user to restrict maximum gain applied by AGC. This can be used for limiting PGAgain in situations where environment noise is greater than programmed noise threshold. Microphone input MaxPGA can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB. Cell-phone input Max PGA can beprogrammed from −34.5 dB to −0.5 dB in steps of 0.5 dB, as well as +12 dB.See Table 1 for various AGC programming options. AGC can be used only if microphone input or Cell-phoneinput is routed to the ADC channel. When both microphone input and Cell-phone input are connected to theADC, AGC is automatically disabled.InputSignalOutputSignalTargetGainAGCGainDecay TimeAttackTimeFigure 19. AGC Characteristics24

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Table 1. AGC SettingsMIC HEADSET INPUT MIC HANDSET INPUT CELL-PHONE INPUTBITCONTROLREGISTERBITCONTROLREGISTERBITCONTROLREGISTERAGC enable D0 01H D0 1EH D0 24HTarget gain D7−D5 01H D7−D5 1EH D7−D5 24HTime constants (attack and decay time) D4−D1 01H D4−D1 1EH D4−D1 24HNoise threshold D13−D11 24H D13−D11 24H D13−D11 24HNoise threshold flag D11 04H D11 04H D14 24HHysteresis D10−D9 1DH D10−D9 1DH D10−D9 24HDebounce time (normal to silence mode) D8−D6 26H D8−D6 26H D8−D6 27HDebounce time (silence to normal mode) D5−D3 26H D5−D3 26H D5−D3 27HMax PGA applicable D15−D9 26H D15−D9 26H D15−D9 27HGain applied by AGC D15−D8 01H D15−D8 1EH D14−D8 1FHSaturation flag D0 04H D0 04H D7 1FHClip stepping disable D3 06H D3 06H D8 24HNOTE: All settings shown in Table 1 are located in Page 2 of control registers.Stereo Audio DACEach channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter,digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhancedperformance at low sample rates through increased oversampling and image filtering, thereby keepingquantization noise generated within the delta-sigma modulator and signal images strongly suppressed withinthe audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 x Fsref andchanging the oversampling ratio as the input sample rate is changed. For Fsref of 48 kHz, the digital delta−sigmamodulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within thedelta-sigma modulator stays within the frequency band below 20 kHz at all sample rates. Similarly, for Fsrefrate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.Digital Audio ProcessingThe DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, orspeaker equalization. The de-emphasis function is only available for sample rates of 32 kHz, 44.1 kHz, and 48kHz. The transfer function consists of a pole with time constant of 50ms and a zero with time constant of 15ms.Frequency response plots are given in the Audio Codec Filter Frequency Responses section of this data sheet.The DAC digital effects processing block consists of a fourth order digital IIR filter with programmablecoefficients (one set per channel). The filter is implemented as cascade of two biquad sections with frequencyresponse given by:N0 2 N1 z 1 N2 z 22 N3 2 N4 z1 N5 z 2232768 2 D1 z 1 D2 z 32768 2 D4 z 1 D5 zThe N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. Thecoefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the mostcommonly used in portable audio applications. The default N and D coefficients in the part are given by:N0 = N3 = 27619N1 = N4 = −27034N2 = N5 = 26461D1 = D4 = 32131D2 = D5 = −3150625

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.com26These coefficients implement a shelving filter with 0 dB gain from dc to approximately 150 Hz, at which pointit rolls off to 3 dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz.The N and D coefficients are represented by 16−bit twos complement numbers with values ranging from –32768to +32767. Frequency response plots are given in the Audio Codec Filter Frequency Responses section of thisdata sheet.Interpolation FilterThe interpolation filter upsamples the output of the digital audio processing block by the required oversamplingratio. It provides a linear phase output with a group delay of 21/Fs.In addition, the digital interpolation filter provides enhanced image filtering to reduce signal images caused bythe upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signalimages at multiples of 8 kHz, i.e., 8 kHz, 16 kHz, 24 kHz, etc. The images at 8 kHz and 16 kHz are below 20kHz and still audible to the listener, therefore, they must be filtered heavily to maintain a good quality output.The interpolation filter is designed to maintain at least 65 dB rejection of images that land below 7.455 Fs. Inorder to utilize the programmable interpolation capability, the Fsref should be programmed to a higher rate(restricted to be in the range of 39 kHz to 53 kHz when the PLL is in use), and the actual FS is set using thedividers in bits D5D3 of control register 00H/page 2. For example, if Fs = 8 kHz is required, then Fsref can beset to 48 kHz, and the DAC Fs set to Fsref/6. This ensures that all images of the 8-kHz data are sufficientlyattenuated well beyond a 20-kHz audible frequency range. Passband ripple for all sample-rate cases (from 20Hz to 0.45 Fs) is +0.06 dB maximum.Delta-Sigma DACThe audio digital-to-analog converter incorporates a third order multi-bit delta-sigma modulator followed by ananalog reconstruction filter. The DAC provides high-resolution, low−noise performance, using oversamplingand noise shaping techniques. The analog reconstruction filter design consists of a 6 tap analog FIR filterfollowed by a continuous time RC filter. The analog FIR operates at 6.144 MHz (128x48 kHz, for Fsref of 48kHz) or at 5.6448 MHz (128x44.1 kHz, for Fsref of 44.1 kHz). The DAC analog performance may be degradedby excessive clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to aminimum (less than 50 ps).DAC Digital Volume ControlThe DAC has a digital volume control block, which implements programmable gain. The volume level can bevaried from 0 dB to –63.5 dB in 0.5 dB steps, in addition to a mute bit, independently for each channel. Thevolume level of both channels can also be changed simultaneously by the master volume control. The gain isimplemented with a soft−stepping algorithm, which only changes the actual volume by one step per inputsample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to onestep per two input samples through D1 of control register 04H/Page 2.Because of soft-stepping, the host does not know when the DAC has been completely muted. This may beimportant if the host wishes to mute the DAC before making a significant change, such as changing samplerates. In order to help with this situation, the part provides a flag back to the host via a read-only register bit(D2−D3 of control register 04H/page 2) that alerts the host when the part has completed the soft-stepping, andthe actual volume has reached the desired volume level. The soft-stepping feature can be disabled byprogramming D14=1 in register 1DH in Page 2. If soft-stepping is enabled, the MCLK signal should be keptapplied to the device, until the DAC power-down flag is set. When this flag is set, the internal soft-steppingprocess and power down sequence is complete, and the MCLK can be stopped if desired.The TSC2101 also includes functionality to detect when the user switches on or off the de-emphasis or digitalaudio processing functions, then (1) soft-mute the DAC volume control, (2) change the operation of the digitaleffects processing and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due toinstantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC. Thecircuit begins operation at power-up with the volume control muted, then soft-steps it up to the desired volumelevel. At power-down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004DAC PowerdownThe DAC powerdown flag (D4D3 of control register 05H/page 2) along with D10 of control register 05H/page2 denotes the powerdown status of the DAC according to Table 2.Table 2. DAC Powerdown StatusD10, D4, D3 POWERUP/POWERDOWN STATE OF DAC0,0,0 DAC left and right are in stable powerup state.0,0,1 DAC left is in stable powerup state.DAC right is in the process of powering up. The length of this state is determined by PLL and output driver powerup delayscontrolled by register programming.0,1,0 DAC left is in the process of powering up. The length of this state is determined by PLL and output driver powerup delayscontrolled by register programming.DAC right is in stable powerup state.0,1,1 DAC left and right are in the process of powering up. The length of this state is determined by PLL and output driverpowerup delays controlled by register programming.1,0,0 DAC left and right are in the process of powering down. The length of this state is determined by soft−stepping of volumecontrol block.1,0,1 DAC left is in the process of powering down. The length of this state is determined by soft−stepping of volume control block.DAC right is in stable powerdown state.1,1,0 DAC left is in stable powerdown state.DAC right is in the process of powering down. The length of this state is determined by soft−stepping of volume controlblock.1,1,1 DAC left and right are in stable powerdown state.Analog OutputsThe TSC2101 has the capability to route the DAC output to any of the selected analog outputs. The TSC2101provides various analog routing capabilities. All analog outputs other than the selected ones are powered downfor optimal power consumption. Headphone DriversThe TSC2101 features stereo headphone drivers (SPK1 and SPK2) that can deliver 44 mW per channel at3.3-V supply, into 16-Ω loads. The TSC2101 provides flexibility to connect either of the DAC channels to eitherof the headphone driver outputs. It also allows mixing of signals from different DAC channels. The headphonescan be connected in a single ended configuration using ac-coupling capacitors, or the capacitors can beremoved and virtual ground (VGND) powered for a cap-less output connection. Note that the VGND amplifiermust be powered up if the cap-less configuration is used.In the case of an ac-coupled output, the value of the capacitors is typically chosen based on the amount oflow−frequency cut that can be tolerated. The capacitor in series with the load impedance forms a high-passfilter with –3 dB cutoff frequency of 1/(2πRC) in Hz, where R is the impedance of the headphones. Use of anoverly small capacitor reduces low-frequency components in the signal output and lead to low-quality audio.When driving 16-Ω headphones, capacitors of 220-µF (a commonly used value) result in a high-pass filter cutofffrequency of 45 Hz, although reducing these capacitors to 50 µF results in a cutoff frequency of 199 Hz, whichis generally considered noticeable when playing music. The cutoff frequency is reduced to half of the abovevalues if 32-Ω headphones are used instead of 16-Ω.The TSC2101 programmable digital effects block can be used to help reduce the size of capacitors needed byimplementing a low frequency boost function to help compensate for the high-pass filter introduced by theac-coupling capacitors. For example, by using 50-µF capacitors and setting the TSC2101 programmable filtercoefficients as shown below, the frequency response can be improved as shown in Figure 21.Filter coefficients (use the same for both channels):N0 = 32767, N1 = −32346, N2 = 31925, N3 = 32767, N4 = 0, N5 = 0D0 = 32738, D1 = −32708, D4 = 0, D5 =027

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.com0−2−4−6Gain − dB−8−10−12−14−16−18−200 200 400 600 800 1000f − Frequency − HzFigure 20. Uncompensated Response For 16-Ω Load and 50-F Decoupling Capacitor0−2−4−6Gain − dB−8−10−12−14−16−18−200 200 400 600 800 1000f − Frequency − HzFigure 21. Frequency Response For 16-Ω Load and 50-F Decoupling Capacitor After GainCompensation Using Above Set of Coefficients For Audio Effects FilterUsing the capless output configuration eliminates the need for these capacitors and removes the accompanyinghigh-pass filter entirely. However, this configuration does have one drawback – if the RETURN terminal of theheadphone jack (which is wired to the TSC2101 VGND pin) is ever connected to a ground that is shorted tothe TSC2101 ground pin, then the VGND amplifier enters short-circuit protection, and the audio output doesnot function properly.The TSC2101 incorporates a programmable short-circuit detection/protection function. In case of short circuit,all analog outputs are disabled and a read only bit D1 of control register 1DH/page 2 is set. In such cases, thereare two ways to return to normal operation:− Hardware or software reset− Power down all the output drivers, which can be achieved by setting bits D12, D11, D 8, D7, and D6 of controlregister 05H/page 2 and then wait for driver power down status flags (bits D15−D10 of control register25H/page 2) to become 1. The wait time is typically less than 50 ms after which, output drivers can beprogrammed as desired.28

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004For the cap interface, this feature can be disabled by setting bit D0 of control register 20H/page 2. In the caseof the cap-less interface, VGND short circuit protection must also be disabled, which can be achieved by settingbit D4 of control register 21H/page 2.The TSC2101 implements a pop reduction scheme to reduce audible artifacts during powerup and powerdownof headphone drivers. The scheme can be controlled by programming bits D5 and D4 of control register25H/page 2. By default, the driver pop reduction scheme is enabled and can be disabled by programming bitD5 of control register 25H/page 2 to 1. When this scheme is enabled and the virtual ground connection is notused (VGND amplifier is powered down), the audio output driver slowly charges up any external ac-couplingcapacitors to reduce audible artifacts. Bit D4 of control register 25H/page 2 provides control of the charging timefor the ac-coupling capacitor as either 0.8 sec or 4 sec. When the virtual ground amplifier is powered up andused, the external ac-coupling capacitor is eliminated, and the powerup time becomes 1 ms. This scheme takeseffect whenever any of the headphone drivers are powered up. Speaker DriverThe TSC2101 has an integrated speaker driver (OUT8P−OUT8N) capable of driving an 8 Ω differential load.The speaker driver, powered directly from the battery supply (3.5 V to 4.2 V) on the BVDD pin can deliver 400mW at 3.9 V supply. It allows connecting one or both DAC channel to speaker driver. The TSC2101 also has ashort circuit protection feature for the speaker driver which can be enabled by setting bit D5 of control register21H/page 2. Receiver DriverThe TSC2101 includes a receiver driver (SPK1−OUT32N), which can drive a 32 Ω differential load. It iscapable of delivering 82 mW into a 32 Ω load. The TSC2101 does not allow both the receiver driver andheadphone drivers to be turned on at the same time. Also, when the receiver driver is being used, theheadphone driver load must be disconnected.Headset InterfaceThe TSC2101 supports all standard headset interfaces. It is capable of interfacing with 3-wire stereo headset,3-wire cellular headset and 4-wire stereo-cellular headsets. It supports both capacitor-coupled (cap) andcapacitor-less (capless) interface for headset through software programming. Capless InterfaceFigure 22 shows the connection diagram to the TSC2101 for capless interface. VGND acts as a ground ofheadset jack. Voltage at VGND is 1.5 V and MICBIAS_HED voltage is programmed to 3.3 V. With this, thevoltage across microphone is configured to be 1.8 V. In order to minimize the effect of routing resistance onVGND inside the device and on the printed circuit board (PCB), SPKFC should be shorted to VGND at thejack. This reduces crosstalk from speaker to microphone because of common ground as VGND.29

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004MICBIAS_HND2.5MICIN_HNDLOUDSPEAKEROUT8POUT8N−1MICBIAS_HEDMIC_DETECT_IN3.3VTo Detection blockStereogssMICIN_HEDCellulargmsStereo +Cellularg m ssRECEIVEROUT32NSPK1−1m = mics = stereg = ground/midbiasSPK2SPKFCVGNDTo Detectionblock1.5 VFigure 22. Connection Diagram for Capless InterfaceCap InterfaceFigure 23 shows connection diagram to device for cap interface.30

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004MICBIAS_HND2.5VMICIN_HNDLOUDSPEAKEROUT8POUT8N−1MICBIAS_HEDMIC_DETECT_IN2.5VTo Detection blockStereogssMICIN_HEDCellulargmsStereo +Cellularg m ssRECEIVEROUT32NSPK1−1m = mics = stereg = ground/midbiasSPK2SPKFCVGNDTo Detectionblock1.5 VFigure 23. Connection Diagram for Cap InterfaceAuto DetectionThe TSC2101 has built in monitors to automatically detect the insertion and removal of headsets. The detectionscheme can differentiate between stereo, cellular and stereo-cellular headsets. Upon detection of headsetinsertion or removal, the TSC2101 updates read-only bit D12 of control register 22H/Page 2. The TSC2101 canbe programmed to send an active high interrupt for insertion and removal of headsets to the host-processorover GPIO1 using bit D3 of control register 22H/Page 2 and GPIO2 using bit D4 of control register 22H/Page2. The headset detection feature can be enabled by setting bit D15 of control register 22H/Page 2. Whenheadset detection is enabled and headset is not detected, SPK1, VGND and MICBIAS_HED are turned offirrespective of control register settings. The TSC2101 also has the capability to detect button press on theheadset microphone. It consumes less than 50 µA while waiting for button press with everything else powereddown. Upon button press, the TSC2101 updates read-only bit D11 of control register 22H/Page 2. It can alsosend an active high interrupt for indicating button press to the processor over GPIO1 using bit D1D0 of controlregister 22H/Page 2. The TSC2101 provides debounce programmability for headset and button detect.Debounce programmability can be used to reject glitches generated, and hence avoids false detection, whileinserting headset or pressing button.Figure 24 shows terminal connections and jack configuration required for various headsets. Care should betaken to avoid any dc path from MIC_DETECT_IN to ground, when a headset is not inserted.31

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comsssgggssmmStereo +Cellularg m ssCellulargmsStereogss32Figure 24. Connection Diagram for JacksHeadset Detection− Interrupt polarity: Active high.− Typical interrupt duration: 1.75 ms.− Debounce programmability on bits D10 and D9 in control register 22H/Page 2:− 00 => 16 ms duration (with 2 ms clock resolution)− 01 => 32 ms duration (with 4 ms clock resolution)− 10 => 64 ms duration (with 8 ms clock resolution)− 11 => 128 ms duration (with 16 ms clock resolution)− Headset detect flag is available till headset is connected.Button Detection− Interrupt polarity: Active high.− Typical interrupt duration: Button pressed time + clock resolution. Clock resolution depends upondebounce programmability.− Typical interrupt delay from button: Debounce duration + 0.5ms− Debounce programmability:− 00 => No glitch rejection− 01 => 8 ms duration (with 1 ms clock resolution)− 10 => 16 ms duration (with 2 ms clock resolution)− 11 => 32 ms duration (with 4 ms clock resolution)− Button detect flag is set when button is pressed. It gets clear when flag read is done after button pressremoval.AUDIO ROUTINGAudio Interface for Smart-Phone ApplicationsThe TSC2101 supports audio routing features to combine various analog inputs and route them to analogoutputs or the ADC for smart−phone applications. In smart-phone applications, the TSC2101 can be used tointerface the cell-phone module to microphones and speakers. The TSC2101 allows the input from thecell-phone module to be routed to different speakers through a PGA which supports a range of 12 dB to –34.5dB in steps of 0.5 dB. The cell-phone input can also be mixed with the microphone input for recording throughthe ADC. The microphone or DAC audio can be routed to the cell-phone output. The buzzer input fromcell-phone can be routed to the speakers through a PGA. The buzzer input supports PGA range of 0 dB to –45dB in steps of 3 dB. The mixing and PGA are under full software control. The mixing feature can be used evenwhen both ADC and DAC are powered down. Cell-phone PGA, microphone PGA and buzzer PGA includessoft-stepping logic. Soft-stepping logic works on Fsref if DAC is powered up otherwise; it works on internaloscillator clocks.

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Analog MixerThe analog mixer can be used to route the analog input selected for the ADC through an analog volume controland then mix it with the audio DAC output. The analog mixer feature is available only if the single endedmicrophone input or the AUX input is selected as the input to the ADC, not when the ADC input is configuredin fully-differential mode. This feature is available even if the ADC and DAC are powered down. The analogvolume control has a range from +12 dB to –34.5 dB in 0.5 dB steps plus mute and includes soft−stepping logic.The internal oscillator is used for soft−stepping whenever the ADC and DAC are powered down.KeyclickA special circuit has been included for inserting a square−wave signal into the analog output signal path basedon register control. This functionality is intended for generating keyclick sounds for user feedback. Register04H/Page 2 contains bits that control the amplitude, frequency, and duration of the square−wave signal. Thefrequency of the signal can be varied from 62.5 Hz to 8 kHz and its duration can be programmed from 2 periodsto 32 periods. Whenever this register is written, the square wave is generated and coupled into the audio output.The keyclick enable bit D15 of control register 04H/Page 2 is reset after the duration of a keyclick is played out.This capability is available even when the ADC and DAC are powered down.OPERATION—TOUCH SCREENA resistive touch screen works by applying a voltage across a resistor network and measuring the change inresistance at a given point on the matrix where a screen is touched by an input stylus, pen, or finger. The changein the resistance ratio marks the location on the touch screen.The TSC2101 supports the resistive 4-wire configurations (see Figure 25). The circuit determines location intwo coordinate pair dimensions, although a third dimension can be added for measuring pressure.The 4-Wire Touch Screen Coordinate Pair MeasurementA 4-wire touch screen is constructed as shown in Figure 25. It consists of two transparent resistive layersseparated by insulating spacers.Conductive BarY+Transparent Conductor (ITO)Bottom SideX+Transparent Conductor (ITO)Top SideX−Silver InkY−Insulating Material (Glass)ITO= Indium Tin OxideFigure 25. 4-Wire Touch Screen ConstructionThe 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.The ADC converts the voltage measured at the point the panel is touched. A measurement of the Y positionof the pointing device is made by connecting the X+ input to an ADC, turning on the Y drivers, and digitizingthe voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at thepoint of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect theconversion due to the high input impedance of the ADC.Voltage is then applied to the other axis, and the ADC converts the voltage representing the X position on thescreen. This provides the X and Y coordinates to the associated processor.33

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comMeasuring touch pressure (Z) can also be done with the TSC2101. To determine pen or finger touch, thepressure of the touch needs to be determined. Generally, it is not necessary to have very high performancefor this test; therefore, the 8-bit resolution mode is recommended (however, calculations are shown with the12-bit resolution mode). There are several different ways of performing this measurement. The TSC2101supports two methods. The first method requires knowing the X-plate resistance, measurement of theX-Position, and two additional cross panel measurements (Z 2 and Z 1 ) of the touch screen (see Figure 26).Using Equation (1) calculates the touch resistance:R R X–positionTOUCH X–plate Z 24096 Z 1–1(1)The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position andY-Position, and Z 1 . Using Equation (2) also calculates the touch resistance:R TOUCHR X−plate X−position4096 4096Z 1 1 R Y−plate1 Y−position4096(2)X+Measure X-PositionY+Measure Z1-PositionX+Y+X+Y+TouchTouchTouchX-PositionX−Y−Z1-PositioniX− Y−Z2-PositionX−Y−Measure Z2-PositionFigure 26. Pressure MeasurementWhen the touch panel is pressed or touched, and the drivers to the panel are turned on, the voltage across thetouch panel often overshoots and then slowly settles (decays) down to a stable DC value. This is due tomechanical bouncing which is caused by vibration of the top layer sheet of the touch panel when the panel ispressed. This settling time must be accounted for, or else the converted value will be in error. Therefore, a delaymust be introduced between the time the driver for a particular measurement is turned on, and the timemeasurement is made.In some applications, external capacitors may be required across the touch screen for filtering noise picked upby the touch screen, i.e., noise generated by the LCD panel or back-light circuitry. The value of these capacitorsprovides a low-pass filter to reduce the noise, but causes an additional settling time requirement when the panelis touched.Several solutions to this problem are available in the TSC2101. A programmable delay time is available whichsets the delay between turning the drivers on and making a conversion. This is referred to as the panel voltagestabilization time, and is used in some of the modes available in the TSC2101. In other modes, the TSC2101can be commanded to turn on the drivers only without performing a conversion. Time can then be allowed beforethe command is issued to perform a conversion.The TSC2101 touch screen interface can measure position (X, Y) and pressure (Z). Determination of thesecoordinates is possible under three different modes of the ADC: (1) conversion controlled by the TSC2101,initiated by detection of a touch; (2) conversion controlled by the TSC2101, initiated by the host responding tothe PINTDAV signal; or (3) conversion completely controlled by the host processor.Touch Screen ADC ConverterThe analog inputs of the TSC2101 are shown in Figure 27. The analog inputs (X, Y, and Z touch panelcoordinates, battery voltage monitors, chip temperature and auxiliary input) are provided via a multiplexer tothe successive approximation register (SAR) analog-to-digital (A/D) converter. The ADC architecture is basedon capacitive redistribution architecture, which inherently includes a sample/hold function.A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide powerand an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input tothe converter and a differential reference input architecture, it is possible to negate errors caused by the driverswitch on- resistances.34

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004The ADC is controlled by an ADC control register. Several modes of operation are possible, depending uponthe bits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion ratemay all be programmed through this register. These modes are outlined in the sections below for each type ofanalog input. The results of conversions made are stored in the appropriate result register.PINTDAV AVDD1 VREFVREFX+X−Y+Y−IN+IN−REFPREFMCONVERTERVBATAUX1AUX2AVSS1Figure 27. Simplified Diagram of the Analog Input SectionData FormatThe TSC2101 output data is in unsigned Binary format and can be read from registers over the SPI interface.ReferenceThe TSC2101 has an internal voltage reference that can be set to 1.25 V or 2.5 V, through the reference controlregister.35

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004The internal reference voltage should only be used in the single-ended mode for battery monitoring,temperature measurement, and for utilizing the auxiliary inputs. Optimal touch-screen performance is achievedwhen using a ratiometric conversion, thus all touch-screen measurements are done automatically in theratiometric mode.An external reference can also be applied to the VREF pin, and the internal reference can be turned off.Variable ResolutionThe TSC2101 provides three different resolutions for the ADC: 8, 10 or 12 bits. Lower resolutions are oftenpractical for measurements such as touch pressure. Performing the conversions at lower resolution reduce theamount of time it takes for the ADC to complete its conversion process, which lowers power consumption.Conversion Clock and Conversion TimeThe TSC2101 contains an internal 8 MHz clock, which is used to drive the state machines inside the devicethat perform the many functions of the part. This clock is divided down to provide a clock to run the ADC. Thedivision ratio for this clock is set in the ADC control register. The ability to change the conversion clock rateallows the user to choose the optimal value for resolution, speed, and power. If the 8 MHz clock is used directly,the ADC is limited to 8-bit resolution; using higher resolutions at this speed does not result in accurateconversions. Using a 4 MHz conversion clock is suitable for 10-bit resolution; 12-bit resolution requires that theconversion clock run at 1 or 2 MHz.Regardless of the conversion clock speed, the internal clock runs nominally at 8 MHz. The conversion time ofthe TSC2101 is dependent upon several functions (see the section Touch Screen Conversion Initiated at TouchDetect in this data sheet). While the conversion clock speed plays an important role in the time it takes for aconversion to complete, a certain number of internal clock cycles are needed for proper sampling of the signal.Moreover, additional times, such as the panel voltage stabilization time, can add significantly to the time it takesto perform a conversion. Conversion time can vary depending upon the mode in which the TSC2101 is used.Throughout this data sheet, internal and conversion clock cycles are used to describe the times that manyfunctions take to execute. Considering the total system design, these times must be taken into account by theuser.When both the audio ADC and DAC are powered down, the touch screen ADC uses an internal oscillator forconversions. However, to save power whenever audio ADC or DAC are powered up, the internal oscillator ispowered down and MCLK and BCLK are used to clock the touch screen ADC.The TSC2101 uses the programmed value of bit D13 in control register 06H/page 2 and the PLLprogrammability to derive a clock from MCLK. The various combinations are listed in Table 3.Table 3. Conversion Clock FrequencyD13=0 (in control register 06H/page 2) D13=1 (in control register 06H/page 2)PLL enabledPLL disabledTouch Detect/Data AvailableMCLK×K × 13P×160MCLK × 13Q×10MCLK × K × 17P×192MCLK × 17Q×12The pen interrupt/data available (PINTDAV) output function is detailed in Figure 28. While in the power-downmode, the Y– driver is ON and connected to AVSS2 and the X+ pin is connected through an on−chip pull-upresistor to AVDD2. In this mode, the X+ pin is also connected to a digital buffer and mux to drive the PINTDAVoutput. When the panel is touched, the X+ input is pulled to ground through the touch screen and pen-interruptsignal goes LOW due to the current path through the panel to AVSS2, initiating an interrupt to the processor.During the measurement cycles for X− and Y− position, the X+ input is disconnected from the pen-interruptcircuit to prevent any leakage current from the pull-up resistor flowing through the touch screen, and thuscausing conversion errors.36

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004AVDD1PINTDAVDATAV50 kΩTEMP1TEMP2Y+HIGH EXCEPT WHENTEMP1. TEMP2ACTIVATEDTEMP DIODEX+Y−ONY+ or X+ DRIVERS ON ORTEMP1 , TEMP2MEASUREMENTS ACTIVATEDFigure 28. PINTDAV Functional Block DiagramIn modes where the TSC2101 needs to detect if the screen is still touched (for example, when doing a PINTDAVinitiated X, Y, and Z conversion), the TSC2101 must reset the drivers so that the 50 KΩ resistor is connected.Because of the high value of this pull-up resistor, any capacitance on the touch screen inputs causes a longdelay time, and may prevent the detection from occurring correctly. To prevent this, the TSC2101 has a circuitthat allows any screen capacitance to be precharged, so that the pull-up resistor does not have to be the onlysource for the charging current. The time allowed for this precharge, as well as the time needed to sense if thescreen is still touched, can be set in the configuration control register D5−D0 of register 05H/Page 1.This does point out, however, the need to use the minimum capacitor values possible on the touch screeninputs. These capacitors may be needed to reduce noise, but too large a value will increase the neededprecharge and sense times, as well as panel voltage stabilization time.The function of PINTDAV output is programmable and controlled by writing to the bits D15−D14 of controlregister 01H/Page 1 as described in the Table 4.37

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.com38D15−D14Table 4. Programmable PINTDAV FunctionalityPINTDAV FUNCTION00 Acts as PEN interrupt (active low) only. When PEN touch is detected, PINTDAV goes low.01 Acts as data available (active low) only. The PINTDAV goes low as soon as one set of ADC conversions are completed for dataof X,Y, XYZ, battery input, or auxiliary input selected by D13−D10 in control register 00H/Page 1. The resulting ADC output is storedin the appropriate registers. The PINTDAV remains low and goes high only after this complete set of registers selected by D13−D10in control register 00H/Page 1 is read out.1011Acts as both PEN interrupt and data available. When PEN touch is detected, PINTDAV goes low and remains low. The PINTDAVgoes high only after one set of A/D conversions is completed for data of X,Y, XYZ, battery input, or auxiliary input selected byD13−D10 in control register 00H/Page 1.NOTE: See the section, Conversion Time Calculations for the TSC2101 in this data sheet for the timing diagrams.Pen-touch detect circuit is disabled during hardware power down.Touch Screen MeasurementsThe touch screen ADC can be either controlled by the host processor or can be self−controlled to offloadprocessing from the host processor. Bit D12 of control register 01H/Page 1 sets the control mode of theTSC2101 touch screen ADC.Conversion Controlled by the TSC2101 Initiated at Touch DetectIn this mode, the TSC2101 detects when the touch panel is touched and causes the PINTDAV line to go low.At the same time, the TSC2101 starts up its internal clock. Assuming the part was configured to convert XYcoordinates, it then turns on the Y drivers, and after a programmed panel voltage stabilization time, powers upthe ADC and converts the Y coordinate. If averaging is selected, several conversions may take place; whendata averaging is complete, the Y coordinate result is stored in the Y register.If the screen is still touched at this time, the X drivers are enabled, and the process repeats, but measuringinstead the X coordinate, storing the result in the X register.If only X and Y coordinates are to be measured, then the conversion process is complete. The time it takes tocomplete this process depends upon the selected resolution, internal conversion clock rate, averaging selected,panel voltage stabilization time, and precharge and sense times.If the pressure of the touch is also to be measured, the process continues in the same way, measuring the Z1and Z2 values, and placing them in the Z1 and Z2 registers. As before, this process time depends upon thesettings described above.See the section Conversion Time Calculation for the TSC2101 in this data sheet for timing diagrams andconversion time calculations.Conversion Controlled by the TSC2101 Initiated by the HostIn this mode, the TSC2101 detects when the touch panel is touched and causes the PINTDAV line to go low.The host recognizes the interrupt request, and then writes to the ADC control register (D13−D10 of controlregister 00H/Page 1) to select one of the touch screen scan functions. The host can either choose to initiateone of the scan functions, in which case the TSC2101 controls the driver turn−on and wait times (e.g. uponreceiving the interrupt the host can initiate the continuous scan function X−Y−Z1−Z2 after which the TSC2101controls the rest of conversion). The host can also choose to control each aspect of conversion by controllingthe driver turn-on and start of conversions. For example, upon receiving the interrupt request, the host turnson the X drivers. After waiting for the settling time, the host then addresses the TSC2101 again, this timerequesting an X coordinate conversion, and so on.The main difference between this mode and the previous mode is that the host, not the TSC2101, controls thetouch screen scan functions.See the section Conversion Time Calculation for the TSC2101 in this data sheet for timing diagrams andconversion time calculations.

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Temperature MeasurementIn some applications, such as battery charging, a measurement of ambient temperature is required. Thetemperature measurement technique used in the TSC2101 relies on the characteristics of a semiconductorjunction operating at a fixed current level. The forward diode voltage (V BE ) has a well-defined characteristicversus temperature. The ambient temperature can be predicted in applications by knowing the 25°C value ofthe V BE voltage and then monitoring the variation of that voltage as the temperature changes.The TSC2101 offers two modes of temperature measurement. The first mode requires a single reading topredict the ambient temperature. A diode, as shown in Figure 29, is used during this measurement cycle. Thisvoltage is typically 600 mV at +25°C with a 20-µA current through it. The absolute value of this diode voltagecan vary a few millivolts. The temperature coefficient of this voltage is typically 2 mV/°C. During the final testof the end product, the diode voltage at a known room temperature should be stored in nonvolatile memory.Further calibration can be done to calculate the precise temperature coefficient of the particular. This methodhas a temperature resolution of approximately 0.3°C/LSB and accuracy of approximately ±2°C withtwo-temperature calibration. Figure 30 and Figure 31 shows typical plots with single and two-temperaturecalibration respectively.X+MUXA/DConverterTemperature SelectTEMP0TEMP1Figure 29. Functional Block Diagram of Temperature Measurement Mode108°CError in Measurement −6420−2−4−6−8−10−40 −20 0 20 40 60 80 100TA − Free-Air Temperature − CFigure 30. Typical Plot of Single Measurement Method After Calibrating for Offset at Room Temperature39

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.com0.200°CError in Measurement −−0.20−0.40−0.60−0.80−1−1.20−40 −20 0 20 40 60 80 100TA − Free-Air Temperature − CFigure 31. Typical Plot of Single Measurement Method After Calibrating for Offset and Gain At TwoTemperaturesThe second mode uses a two-measurement (differential) method. This mode requires a second conversion witha current 82 times larger. The voltage difference between the first (TEMP1) and second (TEMP2) conversion,using 82 times the bias current, is represented by:kTq ln(N)where:N is the current ratio = 82k = Boltzmann’s constant (1.38054 • 10 −23 electrons volts/degrees Kelvin)q = the electron charge (1.602189 • 10 −19 °C)T = the temperature in degrees KelvinThe equation for the relation between differential code and temperature may vary slightly from device to deviceand can be calibrated at final system test by the user. This method provides resolution of approximately1.5°C/LSB and accuracy of approximately ±4°C after calibrating at room temperature.40

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 200443°CError in Measurement −210−1−2−3−4−40 −20 0 20 40 60 80 100TA − Free-Air Temperature − CFigure 32. Typical Plot of Differential Measurement Method After Calibrating for Offset at RoomTemperatureThe TSC2101 supports programmable auto-temperature measurement mode, which can be enabled usingcontrol register 0CH/page 1. In this mode, the TSC2101 can auto-start the temperature measurement after aprogrammable interval. The user can program minimum and maximum threshold values through a register. Ifthe measurement goes outside the threshold range, the TSC2101 sets a flag in the read only control register0CH/page 1, which gets cleared after the flag is read. The TSC2101 can also be configured to send and activehigh interrupt over GPIO1 by setting D9 in control register 0CH/page 1. The duration of the interrupt isapproximately 2 ms.Temperature measurement can only be done in host controlled mode.Battery MeasurementAn added feature of the TSC2101 is the ability to monitor the battery voltage on the other side of a voltageregulator (dc/dc converter), as shown in Figure 33. The battery voltage can vary from 0.5 V to 6 V whilemaintaining the analog supply voltage to the TSC2101 at 3.0 V to 3.6 V. The input voltage (VBAT) is divideddown by a factor of 5 so that a 6.0 V battery voltage is represented as 1.2 V to the ADC. In order to minimizethe power consumption, the divider is only on during the sampling of the battery input.If the battery conversion results in A/D output code of B, the voltage at the battery pin can be calculated as:V BAT B 2 N 5 VREFWhere:N is the programmed resolution of A/DVREF is the programmed value of internal reference or the applied external reference.41

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comBattery0.5 to 6 V+−LDO or DC-DCConverter3.0 V to 3.6 VVDDRVBAT8 kΩ2 kΩADCFigure 33. Battery Measurement Functional Block DiagramBattery measurement can only be done in host−controlled mode.See the section Conversion Time Calculation for the TSC2101 and subsection Non Touch MeasurementOperation in this data sheet for timing diagrams and conversion time calculations.For increased protection and robustness, TI recommends a minimum 100−Ω resistor be added in seriesbetween the system battery and the VBAT pin. The 100-Ω resistor will cause an approximately 1% gain changein the battery voltage measurement, which can easily be corrected in software when the battery conversion datais read by the operating system.Auxiliary MeasurementThe auxiliary voltage inputs (AUX1 and AUX2) can be measured in much the same way as the battery inputsexcept the difference that input voltage is not divided. Applications might include external temperature sensing,ambient light monitoring for controlling the backlight, or sensing the current drawn from the battery. The auxiliaryinput can also be monitored continuously in scan mode.The TSC2101 provides feature to measure resistance using auxiliary inputs. It has two modes of operation:(1) External bias resistance measurement (2) Internal bias resistance measurement. Internal bias resistancemeasurement mode does not need an external bias resistance of 50 kΩ, but provides less accuracy becauseof on chip resistance variation, which is typically ±20%. Figure 34 shows connection diagram for resistancemeasurement mode on AUX1.VREFVREF50 kΩ50 kΩ50 kΩAUX1VsarSARAUX1VsarSARRRa. Internal bias, Resistance Measurementb. External bias, Resistance MeasurementFigure 34. Connection DIagram for Resistance MeasurementResistance can be calculated using following formula:R 50 K VsarVREF Vsar42

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Where:VREF is the SAR ADC referenceVsar is input to the SAR ADCThe TSC2101 supports programmable auto−auxiliary measurement mode, which can be enabled using controlregister 0CH/page 1. In this mode, the TSC2101 can auto start the auxiliary measurement after aprogrammable interval. The user can program minimum and maximum threshold values through a register. Ifthe measurement goes outside the threshold range, the TSC2101 sets a flag in the read only control register0CH/page 1, which gets cleared after the flag is read. The TSC2101 can also be configured to send an activehigh interrupt over GPIO1 by setting D9 of control register 0CH/page 1. The duration of the interrupt isapproximately 2 ms.Auxiliary measurement can only be done in host−controlled mode.See the section Conversion Time Calculation for the TSC2101 and subsection Non Touch MeasurementOperation in this data sheet for timing diagram and conversion time calculationPort ScanIf making measurements of VBAT, AUX1, and AUX2 is desired on a periodic basis, the Port Scan mode canbe used. This mode causes the TSC2101 to sample and convert battery input and both auxiliary inputs. At theend of this cycle, the battery and auxiliary result registers contain the updated values. Thus, with one write tothe TSC2101, the host can cause three different measurements to be made.Port Scan can only be done in host-controlled mode. See the section Issues at the end of this data sheet fordetails of a known issue with this mode.See the section Conversion Time Calculation for the TSC2101 and subsection Port Scan Operation in this datasheet for timing diagrams and conversion time calculations.Buffer ModeThe TSC2101 supports a programmable buffer mode, which is applicable for both touch screen relatedconversion (X, Y, Z1, Z2) and nontouch screen related conversion (BAT, AUX1, AUX2, TEMP1, TEMP2). Buffermode is implemented using a circular FIFO with a depth of 64. The number of interrupts required to be servicedby a host processor can be reduced significantly buffer mode. Buffer mode can be enabled using control register02H/page1.Figure 35. Circular Buffer43

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.com44Converted data is automatically written into the FIFO. To control the writing, reading and interrupt process, awrite pointer (WRPTR), a read pointer (RDPTR) and a trigger pointer (TGPTR) are used. The read pointeralways shows the location, which will be read next. The write pointer indicates the location, in which the nextconverted data is going to be written. The trigger pointer indicates the location at which an interrupt will begenerated if the write pointer reaches that location. Trigger level is the number of the data points needed to bepresent in the FIFO before generating an interrupt. For e.g., X−Y continuous scan mode with trigger level setto 8, the TSC2101 generates interrupt after writing (X1, Y1), (X2, Y2), (X3, Y3), (X4, Y4) i.e. 4 data-pairs or8 data. Figure 35 shows the case when trigger level is programmed as 32. On resetting buffer mode, RDPTRmoves to location 1, WRPTR moves to location 1, and TGPTR moves to location equal to programmed triggerlevel.The user can select the input or input sequence, which needs to be converted, from the ADCSM bits of controlregister 00H/page 1. The converted values are written in a predefined sequence to the circular buffer. The userhas flexibility to program a specific trigger level in order to choose the configuration which best fits theapplication. When the number of converted data, written in FIFO, becomes equal to the programmed triggerlevel then the device generates an interrupt signal on /PINTDAV pin. In buffer mode, the user should programthis pin as Data Available (DATA_AVA). In buffer mode, touch screen related conversions (X, Y, Z1, Z2) areallowed only in self-controlled mode and nontouch screen related conversions (BAT, AUX1, AUX2, TEMP1,TEMP2) are allowed only in host-controlled mode.Buffer mode can be used in single-shot conversion or continuous conversion mode.In single shot conversion mode, once the number of data written reaches programmed trigger level, theTSC2101 generates an interrupt and waits for the user to start reading. As soon as the user starts reading thefirst data from the last converted set, the TSC2101 clears the interrupt and starts a new set of conversions andthe trigger pointer is incremented by the programmed trigger level. An interrupt is generated again when thetrigger condition is satisfied.In continuous conversion mode, once number of data written reaches the programmed trigger level, theTSC2101 generates an interrupt. It immediately starts a new set of conversions and the trigger pointer isincremented by the programmed trigger level. An interrupt gets cleared either by writing the next converted datainto the FIFO or by starting to read from the FIFO.See the section Conversion Time Calculation for the TSC2101 and subsection Buffer Mode Operation in thisdata sheet for timing diagrams and conversion time calculations.Depending upon how the user is reading data, the FIFO can become empty or full. If the user is trying to readdata even if the FIFO is empty, then RDPTR keeps pointing to same location. If the FIFO gets full then the nextlocation is overwritten with newly converted data and the read pointer is incremented by one.While reading the FIFO, the TSC2101 provides FIFO empty and full status flags along with the data. The usercan also read a status flag from control register 02H/page 1.DIGITAL INTERFACERESETThe device requires reset after power up. This requires a low-to-high transition on the RESET pin after powerup for correct operation. Reset initializes all the internal registers, counters and logic.Hardware Power-DownHardware power-down powers down all the internal circuitry to save power. All the register contents aremaintained. Putting the TSC2101 into hardware power-down circuit also disables the pen-touch detect circuit.General Purpose I/OThe TSC2101 has two general purpose I/O (GPIO1 and GPIO2), which can be programmed either as inputsor outputs. As outputs they can be programmed to control external logic through the TSC2101 registers or sendinterrupts to the host processor on events like button detect, headset insertion, headset removal,Auxiliary/temperature outside threshold range etc. As inputs they can be used by the host-processor to monitorlogic states of signals on the system through the TSC2101 registers.

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004SPI Digital InterfaceAll TSC2101 control registers are programmed through a standard SPI bus. The SPI allows full-duplex,synchronous, serial communication between a host processor (the master) and peripheral devices (slaves).The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices dependon a master to start and synchronize transmissions.A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on theslave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shiftsout on the MISO pin to the master shift register.The idle state of the serial clock for the TSC2101 is low, which corresponds to a clock polarity setting of 0 (typicalmicroprocessor SPI control bit CPOL = 0). The TSC2101 interface is designed so that with a clock phase bitsetting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and theslave begins driving its MISO pin on the first serial clock edge. The SS pin can remain low betweentransmissions; however, the TSC2101 only interprets command words which are transmitted after the fallingedge of SS.TSC2101 COMMUNICATION PROTOCOLRegister ProgrammingThe TSC2101 is entirely controlled by registers. Reading and writing these registers is controlled by an SPImaster and accomplished by the use of a 16-bit command, which is sent prior to the data for that register. Thecommand is constructed as shown in Figure 36.The command word begins with an R/W bit, which specifies the direction of data flow on the SPI serial bus. Thefollowing 4 bits specify the page of memory this command is directed to, as shown in Table 5. The next six bitsspecify the register address on that page of memory to which the data is directed. The last five bits are reservedfor future use and should be written only with zeros.Table 5. Page AddressingPG3 PG2 PG1 PG0 PAGE ADDRESSED0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 Reserved0 1 0 1 Reserved0 1 1 0 Reserved0 1 1 1 Reserved1 0 0 0 Reserved1 0 0 1 Reserved1 0 1 0 Reserved1 0 1 1 Reserved1 1 0 0 Reserved1 1 0 1 Reserved1 1 1 0 Reserved1 1 1 1 ReservedTo read all the first page of memory, for example, the host processor must send the TSC2101 the command0x8000 – this specifies a read operation beginning at page 0, address 0. The processor can then start clockingdata out of the TSC2101. The TSC2101 automatically increments its address pointer to the end of the page;if the host processor continues clocking data out past the end of a page, the TSC2101 sends back the value0xFFFF.Likewise, writing to page 1 of memory would consist of the processor writing the command 0x0800, whichspecifies a write operation, with PG0 set to 1, and all the ADDR bits set to 0. This results in the address pointerpointing at the first location in memory on page 1. See the section on the TSC2101 memory map for detailsof register locations.45

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comBIT 15MSBBIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0LSBR/W* PG3 PG2 PG1 PG0 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0 0 0 0 0Figure 36. TSC2101 Command WordSSSCLKMOSICOMMAND WORD DATA DATAFigure 37. Register Write OperationSSSCLKMOSICOMMAND WORDMOSODATADATAFigure 38. Register Read OperationTSC2101 Memory MapThe TSC2101 has several 16-bit registers which allow control of the device as well as providing a location forresults from the TSC2101 to be stored until read by the host microprocessor. These registers are separatedinto four pages of memory in the TSC2101: a data page (page 0), control pages (page 1 and page 2) and a bufferdata page (page 3). The memory map is shown in Table 6.46PAGE 0: TOUCHSCREEN DATAREGISTERPAGE 1: TOUCH SCREENCONTROL REGISTERSTable 6. Memory MapPAGE 2: AUDIO CONTROL REGISTERSPAGE 3: BUFFERDATA REGISTERSADDR REGISTER ADDR REGISTER ADDR REGISTER ADDR REGISTER00 X 00 TSC ADC 00 Audio Control 1 00 Buffer Location01 Y 01 Status 01 Headset PGA Control 01 Buffer Location02 Z1 02 Buffer Mode 02 DAC PGA Control 02 Buffer Location03 Z2 03 Reference 03 Mixer PGA Control 03 Buffer Location04 Reserved 04 Reset Control Register 04 Audio Control 2 04 Buffer Location05 BAT 05 Configuration 05 Power Down Control 05 Buffer Location06 Reserved 06 Temperature Max 06 Audio Control 3 06 Buffer Location07 AUX1 07 Temperature Min 07 Digital Audio Effects Filter Coefficients 07 Buffer Location08 AUX2 08 AUX1 Max 08 Digital Audio Effects Filter Coefficients 08 Buffer Location09 TEMP1 09 AUX1 Min 09 Digital Audio Effects Filter Coefficients 09 Buffer Location0A TEMP2 0A AUX2 Max 0A Digital Audio Effects Filter Coefficients 0A Buffer Location0B Reserved 0B AUX2 Min 0B Digital Audio Effects Filter Coefficients 0B Buffer Location

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004PAGE 0: TOUCHSCREEN DATAREGISTERADDR REGISTERPAGE 1: TOUCH SCREENCONTROL REGISTERSPAGE 2: AUDIO CONTROL REGISTERSPAGE 3: BUFFERDATA REGISTERSADDR REGISTER ADDRREGISTERADDR REGISTER0C Reserved 0C Measurement Configuration 0C Digital Audio Effects Filter Coefficients 0C Buffer Location0D Reserved 0D Programmable Delay 0D Digital Audio Effects Filter Coefficients 0D Buffer Location0E Reserved 0E Reserved 0E Digital Audio Effects Filter Coefficients 0E Buffer Location0F Reserved 0F Reserved 0F Digital Audio Effects Filter Coefficients 0F Buffer Location10 Reserved 10 Reserved 10 Digital Audio Effects Filter Coefficients 10 Buffer Location11 Reserved 11 Reserved 11 Digital Audio Effects Filter Coefficients 11 Buffer Location12 Reserved 12 Reserved 12 Digital Audio Effects Filter Coefficients 12 Buffer Location13 Reserved 13 Reserved 13 Digital Audio Effects Filter Coefficients 13 Buffer Location14 Reserved 14 Reserved 14 Digital Audio Effects Filter Coefficients 14 Buffer Location15 Reserved 15 Reserved 15 Digital Audio Effects Filter Coefficients 15 Buffer Location16 Reserved 16 Reserved 16 Digital Audio Effects Filter Coefficients 16 Buffer Location17 Reserved 17 Reserved 17 Digital Audio Effects Filter Coefficients 17 Buffer Location18 Reserved 18 Reserved 18 Digital Audio Effects Filter Coefficients 18 Buffer Location19 Reserved 19 Reserved 19 Digital Audio Effects Filter Coefficients 19 Buffer Location1A Reserved 1A Reserved 1A Digital Audio Effects Filter Coefficients 1A Buffer Location1B Reserved 1B Reserved 1B PLL Programmability 1B Buffer Location1C Reserved 1C Reserved 1C PLL Programmability 1C Buffer Location1D Reserved 1D Reserved 1D Audio Control 4 1D Buffer Location1E Reserved 1E Reserved 1E Handset PGA Control 1E Buffer Location1F Reserved 1F Reserved 1F Cell & Buzzer PGA Control 1F Buffer Location20 Reserved 20 Reserved 20 Audio Control 5 20 Buffer Location21 Reserved 21 Reserved 21 Audio Control 6 21 Buffer Location22 Reserved 22 Reserved 22 Audio Control 7 22 Buffer Location23 Reserved 23 Reserved 23 GPIO Control 23 Buffer Location24 Reserved 24 Reserved 24 AGC−CP_IN Control 24 Buffer Location25 Reserved 25 Reserved 25 Driver Powerdown Status 25 Buffer Location26 Reserved 26 Reserved 26 Mic AGC control 26 Buffer Location27 Reserved 27 Reserved 27 Cell-phone AGC Control 27 Buffer Location28 Reserved 28 Reserved 28 Reserved 28 Buffer Location29 Reserved 29 Reserved 29 Reserved 29 Buffer Location2A Reserved 2A Reserved 2A Reserved 2A Buffer Location2B Reserved 2B Reserved 2B Reserved 2B Buffer Location2C Reserved 2C Reserved 2C Reserved 2C Buffer Location2D Reserved 2D Reserved 2D Reserved 2D Buffer Location2E Reserved 2E Reserved 2E Reserved 2E Buffer Location2F−3F Reserved 2F−3F Reserved 2F−3F Reserved 2F−3F BufferLocationsTSC2101 Control RegistersThis section describes each of the registers shown in the memory map of Table 6. The registers are groupedaccording to the function they control. Note that in the TSC2101, bits in control registers may refer to slightlydifferent functions depending upon if you are reading the register or writing to it.TSC2101 Data Registers (Page 0)The data registers of the TSC2101 hold data results from conversion of touch screen ADC. All of these registersdefault to 0000H upon reset. These registers are read only.47

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comX, Y, Z1, Z2, BAT, AUX1, AUX2, TEMP1 and TEMP2 RegistersBit 15MSBThe results of all ADC conversions are placed in the appropriate data register. The data format of the resultword, R, of these registers is right-justified, as follows:Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0LSB0 0 0 0 R11MSBR10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0LSBPAGE 1 CONTROL REGISTER MAPREGISTER 00H: Touch-Screen ADC Control48BITNAMERESETVALUEREAD/WRITEFUNCTIOND15 PSTCM 0 R/W Pen Status/Control Mode.READ0 => There is no screen touch (default).1 => The pen is downWRITE0 => Host controlled touch screen conversions (default).1 => The TSC2101 controlled touch screen conversions.D14 ADST 1(for read)0 (for write)R/WADC STATUS.READ0 =>ADC is busy1 => ADC is not busy (default).WRITE0 => Normal mode (default).1 => Stop conversion and power down.D13−D10 ADCSM 0000 R/W ADC Scan Mode.0000 => No scan0001 => Touch screen scan function: X and Y coordinates are converted and the results returnedto X and Y data registers. Scan continues until either the pen is lifted or a stop bit issent.0010 => Touch screen scan function: X, Y, Z1 and Z2 coordinates are converted and the resultsreturned to X, Y, Z1 and Z2 data registers. Scan continues until either the pen is liftedor a stop bit is sent.0011 => Touch screen scan function: X coordinate is converted and the results returned to X dataregister.0100 => Touch screen scan function: Y coordinate is converted and the results returned to Y dataregister.0101 => Touch screen scan function: Z1 and Z2 coordinates are converted and the resultsreturned to Z1 and Z2 data registers0110 => BAT input is converted and the results returned to the BAT data register.0111 => AUX2 input is converted and the results returned to the AUX2 data register1000 => AUX1 input is converted and the results returned to the AUX1 data register.1001 => Auto Scan function: For AUX1, AUX2, TEMP1 or TEMP2 as chosen using controlregister 0CH/page 1. Scan continues until stop bit is sent or D13−D10 are changed.1010 => TEMP1 input is converted and the results returned to the TEMP1 data register.1011 => Port scan function: BAT, AUX1, AUX2 inputs are measured and the results returned tothe appropriate data registers.1100 => TEMP2 input is converted and the results returned to the TEMP2 data register.1101 => Turn on X+, X− drivers1110 => Turn on Y+, Y− drivers1111 => Turn on Y+, X− driversD9−D8 RESOL 00 R/W Resolution Control. The ADC resolution is specified with these bits.00 => 12-bit resolution01 => 8-bit resolution10 => 10-bit resolution11 => 12-bit resolution

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004BITNAMERESETVALUEREAD/WRITEFUNCTIOND7−D6 ADAVG 00 R/W Converter Averaging Control. These two bits allow user to specify the number of averages theconverter will perform selected by bit D0, which selects either Mean Filter or Median Filter.Mean Filter Median Filter00 => No average No average01 => 4-data average 5-data average10 => 8-data average 9-data average11 => 16-data average 15-data averageD5−D4 ADCR 00 R/W Conversion Rate Control. These two bits specify the internal clock rate, which the ADC uses tocontrol performing a single conversion. These bits are the same whether reading or writing.t conv N 4ƒ INTCLKWhere fINTCLK is the internal clock frequency. For example, with 12-bit resolution and a 2 MHzinternal clock frequency, the conversion time is 8 µs. This yields an effective throughput rate of125 kHz.00 => 8 MHz internal clock rate (use for 8-bit resolution only)01 =>4 MHz internal clock rate (use for 8-bit/10-bit resolution only)10 =>2 MHz internal clock rate11 =>1 MHz internal clock rateD3−D1 PVSTC 000 R/W Panel Voltage Stabilization Time Control. These bits allow user to specify a delay time from thetime the touch screen drivers are enabled to the time the voltage is sampled and a conversionis started. This allows the user to adjust for the settling of the individual touch panel and externalcapacitances.000 => 0 µs stabilization time001 => 100 µs stabilization time010 => 500 µs stabilization time011 => 1 ms stabilization time100 => 5 ms stabilization time101 => 10 ms stabilization time110 => 50 ms stabilization time111 => 100 ms stabilization timeD0 AVGFS 0 R/W Average Filter Select0 => Mean Filter1 => Median FilterREGISTER 01H: Status RegisterBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D14 PINTDAV 10 R/W Pen Interrupt or Data Available. These two bits program the function of the PINTDAV pin.00 => Acts as PEN interrupt (active low) only. When PEN touch is detected, PINTDAV goes low.01 => Acts as data available (active low) only. The PINTDAV goes low as soon as one set of ADCconversion(s) is completed. For scan mode, PINTDAV remains low as long as all theappropriate registers have not been read out.10 => Acts as both PEN interrupt and data available. When PEN touch is detected, PINTDAV goeslow. PINTDAV goes high once all the selected conversions are over.11 => Same as 10D13 PWRDN 0 R TSC−ADC Power down status0 => TSC−ADC is active1 => TSC−ADC stops conversion and powers downD12 HCTLM 0 R Host Controlled Mode Status0 => Host controlled mode1 => Self (TSC2101) controlled modeD11 DAVAIL 0 R Data Available Status0 => No data available.1 => Data is available(i.e one set of conversion is done)Note:− This bit gets cleared only after all the converted data have been completely read out. This bitis not valid in case of buffer mode.49

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comBITNAMERESETVALUEREAD/WRITEFUNCTIOND10 XSTAT 0 R X Data Register Status0 => No new data is available in X−data register1 => New data for X−coordinate is available in registerNote: This bit gets cleared only after the converted data of X coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D9 YSTAT 0 R Y Data Register Status0 => No new data is available in Y−data register1 => New data for Y−coordinate is available in registerNote: This bit gets cleared only after the converted data of Y coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D8 Z1STAT 0 R Z1 Data Register Status0 => No new data is available in Z1−data register1 => New data is available in Z1−data registerNote: This bit gets cleared only after the converted data of Z1 coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D7 Z2STAT 0 R Z2 Data Register Status0 => No new data is available in Z2−data register1 => New data is available in Z2−data registerNote: This bit gets cleared only after the converted data of Z2 coordinate has been completely readout of the register. This bit is not valid in case of buffer mode.D6 BSTAT 0 R BAT Data Register Status0 => No new data is available in BAT data register1 => New data is available in BAT data registerNote: This bit gets cleared only after the converted data of BAT has been completely read out of theregister. This bit is not valid in case of buffer mode.D5 0 R ReservedD4 AX1STAT 0 R AUX1 Data Register Status0 => No new data is available in AUX1−data register1 => New data is available in AUX1−data registerNote: This bit gets cleared only after the converted data of AUX1 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D3 AX2STAT 0 R AUX2 Data Register Status0 => No new data is available in AUX2−data register1 => New data is available in AUX2−data registerNote: This bit gets cleared only after the converted data of AUX2 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D2 T1STAT 0 R TEMP1 Data Register Status0 => No new data is available in TEMP1−data register1 => New data is available in TEMP1−data registerNote: This bit gets cleared only after the converted data of TEMP1 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D1 T2STAT 0 R TEMP2 Data Register Status0 => No new data is available in TEMP2−data register1 => New data is available in TEMP2−data registerNote: This bit gets cleared only after the converted data of TEMP2 has been completely read out ofthe register. This bit is not valid in case of buffer mode.D0 0 R Reserved50

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 02H: Buffer ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15 BUFRES 0 R/W Buffer Reset.0 => Buffer mode is disabled and RDPTR, WRPTR & TGPTR set to their reset value.1 => Buffer mode is enabled.D14 BUFCONT 0 R/W Buffer Mode Selection0 => Continuous conversion mode.1 => Single shot mode.D13−D11 BUFTL 000 R/W Trigger Level TL selection of Buffer used for SAR ADC000 => 8001 => 16010 => 24011 => 32100 => 40101 => 48110 => 56111 => 64D10 BUFOVF 0 R Buffer Full Flag0 => Buffer is not full.1 => Buffer is full. This means buffer contains 64 unread converted data.D9 BUFEMF 1 R Buffer Empty Flag0 => Buffer is not empty.1 => Buffer is empty. This means there is no unread converted data in the buffer.D8−D0 0’s R ReservedREGISTER 03H: Reference ControlBITNAMERESETVALUEREAD/WRITED15−D6 0’s R ReservedD5 0 R/W Reserved. Always write 0 to this bit.FUNCTIOND4 VREFM 0 R/W Voltage Reference Mode. This bit configures the VREF pin as either external reference or internalreference.0 => External reference1 => Internal referenceD3−D2 RPWUDL 00 R/W Reference Power Up Delay. These bits allow for a delay time for measurements to be made afterthe reference powers up, thereby assuring that the reference has settled00 => 0 µs01 => 100 µs10 => 500 µs11 => 1000 µsNote: This will be valid only when device is programmed for internal reference and Bit D1 = 1, i.e.,reference is powered down between the conversions if not required.D1 RPWDN 1 R/W Reference Power Down. This bit controls the power down of the internal reference voltage.0 => Powered up at all times.1 => Powered Down between conversions.Note: When D4 = 0 i.e. device is in external reference mode then the internal reference is powereddown always.D0 IREFV 0 R/W Internal Reference Voltage. This bit selects the internal voltage for TSC ADC.0 => VREF = 1.25 V1 => VREF = 2.50 V51

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comREGISTER 04H: Reset ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D0 RSALL R/W FFFFH Reset All. Writing the code 0xBB00, as shown below, to this register causes the TSC2101 to resetall its control registers to their default, power−up values.1011101100000000 => Reset all control registersOthers=> Do not write other sequences to the register.REGISTER 05H: Configuration ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D7 0’s R ReservedD6 SWPDTD 0 R/W Software Powerdown Control for Pen Touch Detection0 => Pen touch detection is enabled.1 => Pen touch detection is disabled.D5−D3 PRECTM 000 R/W Precharge Time. These bits set the amount of time allowed for precharging any pin capacitance onthe touch screen prior to sensing if a screen touch is happening.000 => 20 µs001 => 84 µ010 => 276 µ011 => 340 µs100 => 1.044 ms101 => 1.108 ms110 => 1.300 m111 => 1.364 msD2−D0 RPWUDL 000 R/W Sense Time. These bits set the amount of time the TSC2101 need to wait to sense a screen touchbetween coordinate axes.000 => 32 µs001 => 96 µs010 => 544 µs011 => 608 µs100 => 2.080 ms101 => 2.144 m110 => 2.592 ms111 => 2.656 msREGISTER 06H: Temperature Max Threshold MeasurementBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D13 0’s R ReservedD12 TMXES 0 R/W Max Temperature (TEMP1 or TEMP2) threshold check enable for Auto/Non−Auto−ScanMeasurement.0 => Max Temperature threshold check is disabled.1 => Max Temperature threshold check is enabled.Only valid for TEMP1 or TEMP2. Depends on bit TSCAN of control register 0CH/page 1 in caseof auto−scan measurement and depends on bits ADCSM of control register 00H/page 1 in caseof non−auto−scan measurement.D11−D0 TTHRESH FFFH R/W Temperature Max Threshold. When code due to temperature measurement goes above or equalto programmed threshold value, interrupt is generated.52

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 07H: Temperature Min Threshold MeasurementBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D13 0’s R ReservedD12 TMNES 0 R/W Min Temperature (TEMP1 or TEMP2) threshold check enable for Auto/Non−Auto−ScanMeasurement.0 => Min Temperature threshold check is disabled.1 => Min Temperature threshold check is enabled.Only valid for TEMP1 or TEMP2. Depends on bit TSCAN of control register 0CH/page 1 in caseof auto−scan measurement and depends on bits ADCSM of control register 00H/page 1 in caseof non−auto−scan measurement.D11−D0 TTHRESL 000H R/W Temperature Min Threshold. When code due to temperature measurement goes below or equal toprogrammed threshold value, interrupt is generated.REGISTER 08H: AUX1 Max Threshold MeasurementBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D13 0’s R ReservedD12 A1MXES 0 R/W Max AUX1 threshold check enable for Auto/Non−Auto−Scan Measurement.0 => Max AUX1 threshold check is disabled.1 => Max AUX1 threshold check is enabled.D11−D0 A1THRESH FFFH R/W AUX1 Threshold. When code due to AUX1 measurement goes above or equal to programmedthreshold value, interrupt is generated.REGISTER 09H: AUX1 Min Threshold MeasurementBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D13 0’s R ReservedD12 A1MNES 0 R/W Min AUX1 threshold check enable for Auto/Non−Auto−Scan Measurement.0 => Min AUX1 threshold check is disabled.1 => Min AUX1 threshold check is enabled.D11−D0 A1THRESL 000H R/W AUX1 Threshold. When code due to AUX1 measurement goes below or equal to programmedthreshold value, interrupt is generated.REGISTER 0AH: AUX2 Max Threshold MeasurementBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D13 0’s R ReservedD12 A2MXES 0 R/W Max AUX2 threshold check enable for Auto/Non−Auto−Scan Measurement.0 => Max AUX2 threshold check is disabled.1 => Max AUX2 threshold check is enabled.D11−D0 A1THRESH FFFH R/W AUX2 Threshold. When code due to AUX2 measurement goes above or equal toprogrammed threshold value, interrupt is generated.REGISTER 0BH: AUX2 Max Threshold MeasurementBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D13 0’s R ReservedD12 A2MNES 0 R/W Min AUX2 threshold check enable for Auto/Non−Auto−Scan Measurement.0 => Min AUX2 threshold check is disabled.1 => Min AUX2 threshold check is enabled.D11−D0 A2THRESL 000H R/W AUX2 Threshold. When code due to AUX2 measurement goes below or equal to programmedthreshold value, interrupt is generated.53

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comREGISTER 0CH: Measurement ConfigurationBIT NAME RESETVALUEREAD/WRITEFUNCTIOND15 TSCAN 0 R/W TEMP Configuration when Auto−Temperature is selected0 => TEMP1 is used for auto−temperature function1 => TEMP2 is used for auto−temperature functionD15 A1CONF 0 R/W AUX1 Configuration.0 => AUX1 is used for voltage measurement.1 => AUX1 is used for resistance measurement.D14 A2CONF 0 R/W AUX2 Configuration.0 => AUX2 is used for voltage measurement.1 => AUX2 is used for resistance measurement.D12 ATEMES 0 R/W Auto Temperature (TEMP1 or TEMP2) measurement enable0 => Auto temperature measurement is disabled.1 => Auto temperature measurement is enabled.TEMP1 or TEMP2 selection is depends on TSCAN bit.D11 AA1MES 0 R/W Auto AUX1 measurement enable0 => Auto AUX1 measurement is disabled.1 => Auto AUX1 measurement is enabled.D10 AA2MES 0 R/W Auto AUX2 measurement enable0 => Auto AUX2 measurement is disabled.1 => Auto AUX2 measurement is enabled.D9 IGPIO1 0 R/W Enable GPIO1 for Auto/Non−Auto−Scan interrupt (this programmability is valid only if D11 & D9of control register 23H/page 2 are 0’s)0 => GPIO1 is not selected for interrupt.1 => GPIO1 is used to send an interrupt. Interrupt is generated when any of TEMP (TEMP1 orTEMP2), AUX1 or AUX2 are not passing thresholdD8 THMXFL 0 R Max threshold flag for Temperature (TEMP1 or TEMP2) measurement.0 => Temperature measurement is less than max threshold setting.1 => Temperature measurement is greater than or equal to max threshold setting.D7 THMNFL 0 R Min threshold flag for Temperature (TEMP1 or TEMP2) measurement.0 => Temperature measurement is greater than min threshold setting.1 => Temperature measurement is less than or equal to max threshold setting.D6 A1HMXFL 0 R Max threshold flag for AUX1measurement.0 => AUX1 measurement is less than max threshold setting.1 => AUX1 measurement is greater than or equal to max threshold setting.D5 A1HMNFL 0 R Min threshold flag for AUX1 measurement.0 => AUX1 measurement is greater than min threshold setting.1 => AUX1 measurement is less than or equal to max threshold setting.D4 A2HMXFL 0 R Max threshold flag for AUX2measurement.0 => AUX2 measurement is less than max threshold setting.1 => AUX2 measurement is greater than or equal to max threshold setting.D3 A2HMNFL 0 R Min threshold flag for AUX2 measurement.0 => AUX2 measurement is greater than min threshold setting.1 => AUX2 measurement is less than or equal to max threshold setting.D2 EXTRES 0 R/W External Bias Resistance Measurement mode0 => Internal bias resistance measurement mode is enabled.1 => External bias resistance measurement mode is enabled.D1−D0 0’s R Reserved54

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 0DH: Programmable Delay In-Between Continuous ConversionBITD15NAMENTSPDELENRESETVALUEREAD/WRITEFUNCTION0 R/W Programmable delay for non−touch screen auto measurement mode0 => Programmable delay is disabled for non−touch screen auto measurement mode.1 => Programmable delay is enabled for non−touch screen auto measurement mode.D14−D12 NTSPDINTV 010 R/W Programming delay in−between conversion for non−touch screen auto measurementmode000 => 1.12 min001 => 3.36 min010 => 5.59 min011 => 7.83 min100 => 10.01 min101 => 12.30 min110 => 14.54 min111 => 16.78 minNote: These delays are from end of one set of conversion to the start of another set ofconversion.D11 TSPDELEN 0 R/W Programmable delay for touch screen measurement0 => Programmable delay mode is disabled for touch screen measurement.1 => Programmable delay mode is enabled for touch screen measurement.Note: This mode is valid only for touch screen related conversion in self−controlled modeand in host−controlled mode valid for only continuous scan for X & Y coordinates or forX, Y, Z1 & Z2 coordinates.D10−D8 TSPDINTV 010 R/W Programming delay in−between conversion for touch screen measurement000 => 1 ms001 => 3 ms010 => 5 ms011 => 6.5 ms100 => 8.5 ms101 => 10 ms110 => 12.5 ms111 => 15 msNote: These delays are from end of one set of conversion to the start of another set ofconversion.D7 CLKSEL 0 R/W Clock selection for the touch screen controller0 => Internal oscillator clock is selected.1 => External MCLK is selected.Note: External clock is used only to control the delay programmed in between theconversion.D6−D0 CLKDIV 0000001 R/W Clock Division used to divide MCLK for getting 1 MHz clock for programmable delay, i.e.MCLK/CLKDIV = 1 MHz,0000000 => 128,0000001 => 1,0000010 => 2,……1111110 => 126,1111111 => 127REGISTER 0EH: ReservedBITNAMERESETVALUEREAD/WRITED15−D8 RESV FFh R/W Reserved. Write only FFh to these bits.FUNCTION55

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comPAGE 2 CONTROL REGISTER MAPREGISTER 00H: Audio Control 1BITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D14 ADCHPF 00 R/W ADC High Pass Filter00 => Disabled01 => −3db point = 0.0045xFs10 => −3dB point = 0.0125xFs11 => −3dB point = 0.025xFsNote: Fs is ADC sample rateD13−D12 0’s R ReservedD11−D10 WLEN 00 R/W Codec Word Length00 => Word length = 16−bit01 => Word length = 20−bit10 => Word length = 24−bit11 => Word length = 32−bitD9−D8 DATFM 00 R/W Digital Data Format00 => I2S Mode01 => DSP Mode10 => Right Justified11 => Left JustifiedNote: Right justified valid only when the ratio between DAC and ADC sample rate is an integer. e.g.ADC = 32 kHz and DAC = 24 kHz or vice−versa is invalid for right justified Mode.D7−D6 0’s R ReservedD5−D3 DACFS 000 R/W DAC Sampling Rate000 => DAC FS = Fsref/1001 => DAC FS = Fsref/(1.5)010 => DAC FS = Fsref/2011 => DAC FS = Fsref/3100 => DAC FS = Fsref/4101 => DAC FS = Fsref/5110 => DAC FS = Fsref/(5.5)111 => DAC FS = Fsref/6Note: Fsref is set between 39 kHz and 53 kHzD2−D0 ADCFS 000 R/W ADC Sampling Rate000 => ADC FS = Fsref/1001 => ADC FS = Fsref/(1.5)010 => ADC FS = Fsref/2011 => ADC FS = Fsref/3100 => ADC FS = Fsref/4101 => ADC FS = Fsref/5110 => ADC FS = Fsref/(5.5)111 => ADC FS = Fsref/6Note: Fsref is set between 39 kHz and 53 kHz56

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 01H: Gain Control for Headset/Aux InputBITNAMERESETVALUEREAD/WRITEFUNCTIOND15 ADMUT_HED 1 R/W Headset/Aux Input Mute1 => Headset/Aux Input Mute0 => Headset/Aux Input not mutedNote: If AGC is enabled and Headset/Aux Input is selected then ADMUT_HED+ADPGA_HEDreflects gain being applied by AGC.D14−D8 ADPGA_HED 1111111 R/W ADC Headset/Aux PGA Settings0000000 => 0 dB0000001 => 0.5 dB0000010 => 1.0 dB………1110110 => 59.0 dB..........1111111 => 59.5 dBNote: If AGC is enabled and Headset/Aux Input is selected then ADMUT_HED+ADPGA_HEDreflects gain being applied by AGC.If AGC is on, the decoding for read values is as follows01110111 => +59.5 dB01110110 => +59.0 dB………00000000 => 0 dB……….11101001 => −11.5 dB11101000 => −12 dBD7−D5 AGCTG_HED 000 R/W AGC Target Gain for Headset/Aux Input. These three bits set the AGC’s targeted ADC outputlevel.000 => −5.5 dB001 => −8.0 dB010 => −10 dB011 => −12 dB100 => −14 dB101 => −17 dB110 => −20 dB111 => −24 dBD4−D1 AGCTC_HED 0000 R/W AGC Time Constant for Headset/Aux Input. These four bits set the AGC attack and decay timeconstants. Time constants remain same irrespective of any sampling frequencyAttack time Decay time(ms)(ms)0000 8 1000001 11 1000010 16 1000011 20 1000100 8 2000101 11 2000110 16 2000111 20 2001000 8 4001001 11 4001010 16 4001011 20 4001100 8 5001101 11 5001110 16 5001111 20 500D0 AGCEN_HED 0 R/W AGC Enable for Headset/Aux Input0 => AGC is off for Headset/Aux Input(ADC Headset/Aux PGA is controlled by ADMUT_HED+ADPGA_HED)1 => AGC is on for Headset/Aux Input(ADC Headset/Aux PGA is controlled by AGC)57

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comREGISTER 02H: CODEC DAC Gain Control58BITNAMERESETVALUEREAD/WRITEFUNCTIOND15 DALMU 1 R/W DAC Left Channel Mute1 => DAC Left Channel Muted0 => DAC Left Channel not mutedD14−D8 DALVL 1111111 R/W DAC Left Channel Volume Control0000000 => DAC left channel volume = 0 dB0000001 => DAC left channel volume = −0.5 dB…..1111110 => DAC left channel volume = −63.0 dB1111111 => DAC left channel volume = −63.5 dBD7 DARMU 1 R/W DAC Right Channel Mute1 => DAC Right Channel Muted0 => DAC Right Channel not mutedD6−D0 DARVL 1111111 R/W DAC Right Channel Volume Control0000000 => DAC right channel volume = 0 dB0000001 => DAC right channel volume = −0.5 dB…..1111110 => DAC right channel volume = −63.0 dB1111111 => DAC right channel volume = −63.5 dBREGISTER 03H: Mixer PGA ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15 ASTMU 1 R/W Analog Sidetone Mute Control1 => Analog sidetone mute0 => Analog sidetone not mutedD14−D8 ASTG 1000101 R/W Analog Sidetone Gain Setting0000000 => Analog sidetone = −34.5 dB0000001 => Analog sidetone = −34 dB0000010 => Analog sidetone = −33.5 dB...1000101 => Analog sidetone = 0 dB1000110 => Analog sidetone = 0.5 dB...1011100 => Analog sidetone = 11.5 dB1011101 => Analog sidetone = 12 dB1011110 => Analog sidetone = 12 dB1011111 => Analog sidetone = 12 dB11xxxxx => Analog sidetone = 12 dBD7−D5 MICSEL 000 R/W Selection for Mic Input and Aux Input for ADC/Cell phone−output/Analog side−tone.000 => Single-ended input MICIN_HED selected001 => Single-ended input MICIN_HND selected010 => Single-ended input AUX1 selected011 => Single-ended input AUX2 selected100 => Differential input MICIN_HED and AUX1 connected to ADC.101 => Differential input MICIN_HED and AUX2 connected to ADC.110 => Differential input MICIN_HND and AUX1 connected to ADC.111 => Differential input MICIN_HND and AUX2 connected to ADC.Note: When D7=1 (differential input selected), analog side−tone path is not validD4 MICADC 0 R/W Selection of ADC input0 => Nothing connected1 => Input selected by MICSEL connected to ADC.D3 CPADC 0 R/W Connects Cell phone input to ADC0 => Cell phone input not connected to ADC.1 => Cell phone input connected to ADC.D2−D1 Reserved 0’s R ReservedD0 ASTGF 0 R Analog Sidetone PGA Flag (Read Only)0 => Gain Applied ≠ PGA Register setting1 => Gain Applied = PGA register setting.Note: This flag indicates when the soft−stepping for analog sidetone is completed.

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 04H: Audio Control 2BITNAMERESETVALUEREAD/WRITEFUNCTIOND15 KCLEN 0 R/W Keyclick Enable0 => Keyclick Disabled1 => Keyclick EnabledNote: This bit is automatically cleared after giving out the keyclick signal length equal to theprogrammed value.D14−D12 KCLAC 100 R/W Keyclick Amplitude Control000 => Lowest Amplitude….100 => Medium Amplitude….111 => Highest AmplitudeD11 APGASS 0 R/W Headset/Aux or Handset PGA Soft−stepping control0 => 0.5 dB change every WCLK or ADWS1 => 0.5 dB change every 2 WCLK or 2 ADWSWhen AGC is enabled for Headset/Aux or Handset, this bit is read only and acts as Noise ThresholdFlag. The read value indicates the following0 => signal power greater than noise threshold1 => signal power is less than noise thresholdD10−D8 KCLFRQ 100 R/W Keyclick Frequency000 => 62.5 Hz001 => 125 Hz010 => 250 Hz011 => 500 Hz100 => 1 kHz101 => 2 kHz110 => 4 kHz111 => 8 kHzD7−D4 KCLLN 0001 R/W Keyclick Length0000 => 2 periods key click0001 => 4 periods key click0010 => 6 periods key click0011 => 8 periods key click0100 => 10 periods key click0101 => 12 periods key click0110 => 14 periods key click0111 => 16 periods key click1000 => 18 periods key click1001 => 20 periods key click1010 => 22 periods key click1011 => 24 periods key click1100 => 26 periods key click1101 => 28 periods key click1110 => 30 periods key click1111 => 32 periods key clickD3 DLGAF 0 R DAC Left Channel PGA Flag0 => Gain applied ≠ PGA register setting1 => Gain applied = PGA register setting.Note: This flag indicates when the soft−stepping for DAC left channel is completedD2 DRGAF 0 R DAC Right Channel PGA Flag0 => Gain applied ≠ PGA register setting1 => Gain applied = PGA register setting.Note: This flag indicates when the soft−stepping for DAC right channel is completed59

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comBITNAMERESETVALUEREAD/WRITEFUNCTIOND1 DASTC 0 R/W DAC Channel PGA Soft−stepping control0 => 0.5 dB change every WCLK1 => 0.5 dB change every 2 WCLKD0 ADGAF 0 R Headset/Aux or Handset PGA Flag1 => Gain applied = PGA register setting.0 => Gain applied ≠ PGA Register settingNote: This flag indicates when the soft−stepping for PGA is completed.When AGC is enabled for Headset/Aux or Handset, this bit is read−only and acts as SaturationFlag. The read value of this bit indicates the following0 => AGC is not saturated1 => AGC is saturated (PGA has reached –12 dB or max PGA applicable).REGISTER 05H: CODEC Power Control60BIT NAME RESET VALUE READ/WRITE FUNCTIOND15 MBIAS_HND 1 R/W MICBIAS_HND Power−down Control0 => MICBIAS_HND is powered up.1 => MICBIAS_HND is powered down.D14 MBIAS_HED 1 R/W MICBIAS_HED Power−down Control0 => MICBIAS_HED is powered up.1 => MICBIAS_HED is powered down.D13 ASTPWD 1 R/W Analog Sidetone Power−down Control0 => Analog sidetone powered up1 => Analog sidetone powered downD12 SP1PWDN 1 R/W SPK1(Single−Ended)/OUT32N(Diferential) Power−down Control0 => SPK1/OUT32N is powered up1 => SPK1/OUT32N is powered downD11 SP2PWDN 1 R/W SPK2 Power−down Control0 => SPK2 is powered up1 => SPK2 is powered downD10 DAPWDN 1 R/W DAC Power−down Control0 => DAC powered up1 => DAC powered downD9 ADPWDN 1 R/W ADC Power−down Control0 => ADC powered up1 => ADC powered downD8 VGPWDN 1 R/W Driver Virtual Ground Power−down Control0 => VGND is powered up1 => VGND is powered downD7 COPWDN 1 R/W CP_OUT Power−down Control0 => CP_OUT is powered up1 => CP_OUT is powered downD6 LSPWDN 1 R/W Loudspeaker (8−Ω Driver) Power−down Control0 => Loudspeaker (8−Ω driver) is powered up1 => Loudspeaker (8−Ω driver) is powered downD5 ADPWDF 1 R ADC Power Down Flag0 => ADC power down is not complete1 => ADC power down is completeD4 LDAPWDF 1 R DAC Left Power Down Flag0 => DAC left power down is not complete1 => DAC left power down is completeD3 RDAPWDF 1 R DAC Right Power Down Flag0 => DAC right power down is not complete1 => DAC right power down is completeD2 ASTPWF 1 R Analog Sidetone Power Down Flag0 => Analog sidetone power down is not complete1 => Analog sidetone power down is complete

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004BITNAMERESET VALUEREAD/WRITEFUNCTIOND1 EFFCTL 0 R/W Digital Audio Effects Filter0 => Disable digital audio effects filter1 => Enable digital audio effects filterD0 DEEMPF 0 R/W De−emphasis Filter Enable0 => Disable de−emphasis filter1 => Enable de−emphasis filterNOTE: D15−D6 are all 1’s, then full codec section is powered down.REGISTER 06H: Audio Control 3BITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D14 DMSVOL 00 R/W DAC Channel Master Volume Control00 => Left channel and right channel have independent volume controls01 => Left channel volume control is the programmed value of the right channel volume control.10 => Right channel volume control is the programmed value of the left channel volume control.11 => same as 00D13 REFFS 0 R/W Reference Sampling RateNote: This setting controls the coefficients in the de−emphasis filter, the time−constants in AGC,and internal divider values that generate the clock for the touch screen measurement ADC. If anFsref above 48 kHz is being used, then it is recommended to set this to the 48−kHz setting,otherwise either setting can be used.0 => Fsref = 48.0 kHz1 => Fsref = 44.1 kHzD12 DAXFM 0 R/W Master Transfer Mode0 => Continuous data transfer mode1 => 256−s data transfer modeD11 SLVMS 0 R/W CODEC Master Slave Selection0 => The TSC2101 is slave codec1 => The TSC2101 is master codecD10−D9 0’s R ReservedD8 ADCOVF 0 R ADC Channel Overflow Flag0 => ADC channel data is within saturation limits1 => ADC channel data has exceeded saturation limits.Note: This flag gets reset after register read.D7 DALOVF 0 R DAC Left Channel Overflow Flag0 => DAC left channel data is within saturation limits1 => DAC left channel data has exceeded saturation limitsNote: This flag gets reset after register read.D6 DAROVF 0 R DAC Right Channel Overflow Flag0 => DAC right channel data is within saturation limits1 => DAC right channel data has exceeded saturation limitsNote: This flag gets reset after register read.D5−D4 00 R/W Reserved.D3 CLPST 0 R/W MIC AGC Clip Stepping Disable0 => Disabled1 => EnabledNote: Valid only when AGC is selected for the Headset/Aux or Handset input.D2−D0 REVID XXX R TSC2101 Device Revision IDREGISTER 07H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_N0 27619 R/W Left channel bass-boost coefficient N0.REGISTER 08H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_N1 −27034 R/W Left channel bass-boost coefficient N1.FUNCTIONFUNCTION61

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comREGISTER 09H: Digital Audio Effects Filter Coefficients62BITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_N2 26461 R/W Left channel bass-boost coefficient N2.REGISTER 0AH: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_N3 27619 R/W Left channel bass-boost coefficient N3.REGISTER 0BH: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_N4 −27034 R/W Left channel bass-boost coefficient N4.REGISTER 0CH: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_N5 26461 R/W Left channel bass-boost coefficient N5.REGISTER 0DH: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_D1 32131 R/W Left channel bass-boost coefficient D1.REGISTER 0EH: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_D2 −31506 R/W Left channel bass-boost coefficient D2.REGISTER 0FH: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_D4 32131 R/W Left channel bass-boost coefficient D4.REGISTER 10H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 L_D5 −31506 R/W Left channel bass-boost coefficient D5.REGISTER 11H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_N0 27619 R/W Right channel bass-boost coefficient N0.REGISTER 12H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_N1 −27034 R/W Right channel bass-boost coefficient N1.REGISTER 13H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_N2 26461 R/W Right channel bass-boost coefficient N2.REGISTER 14H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_N3 27619 R/W Right channel bass-boost coefficient N3.FUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTION

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 15H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_N4 −27034 R/W Right channel bass-boost coefficient N4.REGISTER 16H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_N5 26461 R/W Right channel bass-boost coefficient N5.REGISTER 17H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_D1 32131 R/W Right channel bass-boost coefficient D1.REGISTER 18H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_D2 −31506 R/W Right channel bass-boost coefficient D2.REGISTER 19H: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_D4 32131 R/W Right channel bass-boost coefficient D4.REGISTER 1AH: Digital Audio Effects Filter CoefficientsBITNAMERESET VALUE(IN DECIMAL)READ/WRITED15−D0 R_D5 −31506 R/W Right channel bass-boost coefficient D5.REGISTER 1BH: PLL ProgrammabilityFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONFUNCTIONBIT NAME RESET VALUE READ/WRITE FUNCTIOND15 PLLSEL 0 R/W PLL Enable0 => Disable PLL.1 => Enable PLL.D14−D11 QVAL 0010 R/W Q value: Valid when PLL is disabled0000 => 16,0001 => 17,0010 => 2,0011 => 3,…….1100 => 12,1101 => 13,1110 => 14,1111 => 15,D10−D8 PVAL 000 R/W P value: Valid when PLL is enabled000 => 8,001 => 1,010 => 2,011 => 3,100 => 4,101 => 5,110 => 6,111 => 763

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comD7−D2 J_VAL 000001 R/W J value: Valid when PLL is enabled000000 => Not valid,000001 => 1,000010 => 2,000011 => 3,……..111100 => 60,111101 => 61,111110 => 62,111111 => 63D1−D0 00 R Reserved (Write only 00)REGISTER ICH: PLL ProgrammabilityBIT NAME RESET VALUE READ/WRITE FUNCTIOND15−D2 D_VAL 0(decimal)R/W D value: Valid when PLL is enabledD value is valid from 0000 to 9999 in decimal.Greater than 9999 is treated as 9999.D1−D0 Reserved 0 R Reserved (Write only 00)REGISTER IDH: Audio Control 4BIT NAME RESET VALUE READ/WRITE FUNCTIOND15 ADSTPD 0 R/W Headset/Aux or Handset PGA Soft−stepping Control0 => Enable soft−stepping1 => Disable soft−steppingD14 DASTPD 0 R/W DAC PGA Soft−stepping Control0 => Enable soft−stepping1 => Disable soft−steppingD13 ASSTPD 0 R/W Analog Sidetone PGA Soft−stepping Control0 => Enable soft−stepping1 => Disable soft−steppingNote: When soft−stepping is enabled gain is changed 0.5 dB per Fsref.D12 CISTPD 0 R/W Cell−phone PGA Soft−stepping Control0 => Enable soft−stepping1 => Disable soft−steppingNote: When soft−stepping is enabled gain is changed 0.5 dB per Fsref.D11 BISTPD 0 R/W Buzzer PGA Soft−stepping Control0 => Enable soft−stepping1 => Disable soft−steppingNote: When soft−stepping is enabled gain is changed 3 dB per Fsref.D10−D9 AGCHYS 00 R/W MIC AGC Hysteresis selection00 => 1 dB01 => 2 dB10 => 4 dB11 => No HysteresisNote: Valid only when AGC is selected for Headset/Aux or Handset inputD8−D7 MB_HED 00 R/W Micbias for Headset00 => MICBIAS_HED = 3.3 V01 => MICBIAS_HED = 2.5 V10 => MICBIAS_HED = 2.0 V11 => MICBIAS_HED = 2.0 VD6 MB_HND 0 R/W Micbias for Handset0 => MICBIAS_HND = 2.5 V1 => MICBIAS_HND = 2.0 VD5−D2 0’s R Reserved (Write only 0000)D1 SCPFL 0 R Driver Short Circuit Protection Flag.0 => No short circuit happened.1 => Short circuit detected on headphone outputs.D0 X R Reserved (Write only 0)64

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 1EH: Gain Control for Handset InputBIT NAME RESET VALUE READ/WRITE FUNCTIOND15 ADMUT_HND 1 R/W Handset Input Mute1 => Handset Input Mute0 => Handset Input not mutedNote: If AGC is enabled and handset Input is selected thenADMUT_HND+ADPGA_HND will reflect gain being applied by AGC.D14−D8 ADPGA_HND 1111111 R/W ADC Handset PGA Settings0000000 => 0 dB0000001 => 0.5 dB0000010 => 1.0 dB....1110110 => 59.0 dB.............1111111 => 59.5 dBNote: If AGC is enabled and handset Input is selected thenADMUT_HND+ADPGA_HND will reflect gain being applied by AGC.If AGC is on, the decoding for read values is as follows01110111 => +59.5 dB01110110 => +59.0 dB………00000000 => 0 dB……….11101000 => −12 dBD7−D5 AGCTG_HND 000 R/W AGC Target Gain for Handset Input.These three bits set the AGC’s targeted ADC output level.000 => −5.5 dB001 => −8.0 dB010 => −10 dB011 => −12 dB100 => −14 dB101 => −17 dB110 => −20 dB111 => −24 dBD4−D1 AGCTC_HND 0000 R/W AGC Time Constant for Handset Input.These four bits set the AGC attack and decay time constants. Timeconstants remain the same irrespective of any sampling frequency.Attack time Decay time(ms) (ms)0000 8 1000001 11 1000010 16 1000011 20 1000100 8 2000101 11 2000110 16 2000111 20 2001000 8 4001001 11 4001010 16 4001011 20 4001100 8 5001101 11 5001110 16 5001111 20 500D0 AGCEN_HND 0 R/W AGC Enable for Handset Input0 => AGC is off for Handset Input(ADC PGA is controlled by ADMUT_HND+ADPGA_HND)1 => AGC is on for Handset Input(ADC PGA is controlled by AGC)65

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comREGISTER 1FH: Gain Control for Cell Phone Input and Buzzer InputBIT NAME RESET VALUE READ/WRITE FUNCTIOND15 MUT_CP 1 R/W Cell phone Input PGA Power−down1 => Power−down cell-phone input PGA0 => Power−up cell phone input PGAD14−D8 CPGA 1000101 R/W Cell−phone Input PGA Settings.0000000 => −34.5 dB0000001 => −34 dB0000010 => −33.5 dB...1000101 => 0 dB1000110 => 0.5 dB...1011100 => 11.5 dB1011101 => 12 dB1011110 => 12 dB1011111 => 12 dB11xxxxx => 12 dBNote: These bits are read−only when AGC is enabled for CP_IN (cell-phone input)and reflect the gain applied by the AGC.D7 CPGF 0 R Cell phone Input PGA Flag (Read Only)0 => Gain applied ≠ PGA register setting1 => Gain applied = PGA register setting.Note: This flag indicates when the soft−stepping for cell-phone input is completed.When AGC is enabled for Cell−phone input, this bit is read−only and acts asSaturation Flag. The read value of this bit indicates the following0 => AGC is not saturated1 => AGC is saturated (PGA has reached –34.5 dB or max PGA applicable).D6 MUT_BU 1 R/W Buzzer Input PGA Power−down1 => Power−down buzzer input PGA0 => Power−up buzzer input PGAD5−D2 BPGA 1111 R/W Buzzer Input PGA settings.1111 => 0 dB1110 => −3 dB1101 => −6 dB1100 => −9 dB1011 => −12 dB1010 => −15 dB1001 => −18 dB1000 => −21 dB0111 => −24 dB0110 => −27 dB0101 => −30 dB0100 => −33 dB0011 => −36 dB0010 => −39 dB0001 => −42 dB0000 => −45 dBD1 BUGF 0 R Buzzer PGA Flag (Read Only)0 => Gain Applied ≠ PGA Register setting1 => Gain Applied = PGA register setting.Note: This flag indicates when the soft−stepping for buzzer input is completed.D0 0 R Reserved (Write only 0)66

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 20H: Audio Control 5BITNAMERESETVALUEREAD/WRITEFUNCTIOND15 DIFFIN 0 R/W Single-ended or Differential Output Selection.0 => Single-ended output (headset/lineout) selected for SPK1 and SPK2 drivers1 => Differential output (handset) selected for SPK1 and OUT32N driversNote: When bit D15=1, both SPK1 and OUT32N drivers should be power−up. Otherwise theTSC2101 automatically power−down both SPK1 and OUT32N drivers.D14−D13 DAC2SPK1 00 R/W DAC Channel Routing to SPK1 (Single-ended)/ SPK1−OUT32N (Differential)00 => No routing from DAC to SPK1/ SPK1−OUT32N01 => DAC left routed to SPK1/SPK1−OUT32N10 => DAC right routed to SPK1/SPK1−OUT32N11 => DAC (left + right)/2 routed to SPK1/SPK1−OUT32ND12 AST2SPK1 0 R/W Analog Sidetone Routing to SPK1 (Single-ended)/SPK1−OUT32N (Differential)0 => No routing from analog sidetone to SPK1/SPK1−OUT32N1 => Analog sidetone routed to SPK1/SPK1−OUT32ND11 BUZ2SPK1 0 R/W Buzzer PGA Routing to SPK1 (Single-ended)/ SPK1−OUT32N (Differential)0 => No routing from buzzer PGA to SPK1/SPK1−OUT32N1 => Buzzer PGA routed to SPK1/ SPK1−OUT32ND10 KCL2SPK1 0 R/W Keyclick Routing to SPK1 (Single-ended)/SPK1−OUT32N (Differential)0 => No routing from keyclick to SPK1/SPK1−OUT32N1 => Keyclick routed to SPK1/SPK1−OUT32ND9 CPI2SPK1 0 R/W Cell−phone Input Routing to SPK1 (Single-ended)/SPK1−OUT32N (Differential)0 => No routing from cell-phone input to SPK1/SPK1−OUT32N1 => Cell phone input routed to SPK1/SPK1−OUT32ND8−D7 DAC2SPK2 00 R/W DAC Channel Routing to SPK2 (Valid for Only Single-ended)00 => No routing from DAC to SPK201 => DAC left routed to SPK210 => DAC right routed to SPK211 => DAC (left + right)/2 routed to SPK2D6 AST2SPK2 0 R/W Analog Sidetone Routing to SPK2 (Valid for Only Single-ended)0 => No routing from analog sidetone to SPK21 => Analog sidetone routed to SPK2D5 BUZ2SPK2 0 R/W Buzzer PGA Routing to SPK2 (Valid for Only Single-ended)0 => No routing from buzzer PGA to SPK21 => Buzzer PGA routed to SPK2D4 KCL2SPK2 0 R/W Keyclick Routing to SPK2 (Valid for Only Single-ended)0 => No routing from keyclick to SPK21 => Keyclick routed to SPK2D3 CPI2SPK2 0 R/W Cell−phone Input Routing to SPK2 (Valid for Only Single-ended)0 => No routing from cell-phone input to SPK21 => Cell−phone input routed to SPK2D2 MUTSPK1 1 R/W Mute Control for SPK1 (Single-ended)/SPK1−OUT32N (Differential)0 => SPK1/SPK1−OUT32N is not muted.1 => SPK1/SPK1−OUT32N is muted.D1 MUTSPK2 1 R/W Mute Control for SPK2 (Valid for Only Single-ended)0 => SPK2 is not muted.1 => SPK2 is muted.D0 HDSCPTC 0 W Headphone Short−circuit Protection Control0 => Enable short−circuit protection1 => Disable short−circuit protection67

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comREGISTER 21H: Audio Control 6BITNAMERESETVALUEREAD/WRITEFUNCTIOND15 SPL2LSK 0 R/W Routing Selected for SPK1 Goes to OUT8P−OUT8N (Loudspeaker) Also.0 => None of the routing selected for SPK1 goes to OUT8P−OUT8N.1 => Routing selected for SPK1 using D14−D9 of control register 20H/page 2 goes toOUT8P−OUT8N.Note: This programming is valid only if SPK1/OUT32N and SPK2 are powered down.D14 AST2LSK 0 R/W Analog Sidetone Routing to OUT8P−OUT8N (Loudspeaker)0 => No routing from analog sidetone to OUT8P−OUT8N1 => Analog sidetone routed to OUT8P−OUT8ND13 BUZ2LSK 0 R/W Buzzer PGA Routing to OUT8P−OUT8N (Loudspeaker)0 => No routing from buzzer PGA to OUT8P−OUT8N1 => Buzzer PGA routed to OUT8P−OUT8ND12 KCL2LSK 0 R/W Keyclick Routing to OUT8P−OUT8N (Loudspeaker)0 => No routing from keyclick to OUT8P−OUT8N1 => Keyclick routed to OUT8P−OUT8ND11 CPI2LSK 0 R/W Cell−phone Input Routing to OUT8P−OUT8N (Loudspeaker)0 => No routing from cell-phone input to OUT8P−OUT8N1 => Cell−phone input routed to OUT8P−OUT8ND10 MIC2CPO 0 R/W MICSEL (Programmed Using Control Register 04H/Page 2) Routed to Cell-phone Output.0 => No routing from MICSEL to CP_OUT.1 => MICSEL routed to CP_OUT.D9 SPL2CPO 0 R/W Routing Selected for SPK1 (Other Than Cell−phone Input) Goes to Cell-phone Output Also.0 => None of the routing selected for SPK1 goes to cell-phone output.1 => Routing selected for SPK1 using D14−D10 of control register 20H/page 2 goes toCP_OUT.Note: This programming is valid even if SPK1/OUT32N and SPK2 are powered down.D8 SPR2CPO 0 R/W Routing Selected for SPK2 Goes to Cell−phone Output Also (Valid for Only Single-ended).0 => None of the routing selected for SPK2 goes to cell-phone output.1 => Routing selected for SPK2 using D8−D3 of control register 20H/page2 goes to CP_OUT.Note: 1. This programming is valid even if SPK2 is power-down.2. This programming is not valid when routing selected for SPK1 is routed to loudspeakerD7 MUTLSPK 1 R/W Mute Control for OUT8P−OUT8N Loudspeaker0 => OUT8P−OUT8N is not muted.1 => OUT8P−OUT8N is muted.D6 MUTSPK2 1 R/W Mute Control for Cell−phone Output0 => CPOUT is not muted.1 => CPOUT is muted.D5 LDSCPTC 1 R/W Loudspeaker Short−circuit Protection Control0 => Enable short−circuit protection for loudspeaker1 => Disable short−circuit protection for loudspeakerD4 VGNDSCPTC 0 R/W VGND Short−circuit Protection Control0 => Enable short−circuit protection for VGND driver1 => Disable short−circuit protection for VGND driverD3 CAPINTF 0 R/W Cap/Cap−less Interface Select for Headset.0 => Select cap−less interface.1 => Select cap interface.D2−D0 0’s R Reserved (Write only 000)68

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 22H: Audio Control 7BITNAMERESETVALUEREAD/WRITEFUNCTIOND15 DETECT 0 R/W Headset Detection0 => Disable headset detection1 => Enable headset detectionD14−D13 HESTYPE 00 R Type of Headset Detected.00 => No headset detected.01 => Stereo headset detected.10 => Cellular headset detected11 => Stereo+cellular headset detectedNote: These two bits are valid only if the headset detection is enabled.D12 HDDETFL 0 R Headset Detection Flag.0 => Headset is not detected1 => Headset is detected.D11 BDETFL 0 R Button Press Detection Flag.0 => Button press is not detected1 => Button press is detected.D10−D9 HDDEBNPG 01 R/W De−bouncing Programmability for Glitch Rejection During Headset Detection.00 => 16 ms duration (with 2 ms clock resolution)01 => 32 ms duration (with 4 ms clock resolution)10 => 64 ms duration (with 8 ms clock resolution)11 => 128 ms duration (with 16 ms clock resolution)D8 0 R Reserved (Write only 0)D7−D6 BDEBNPG 00 R/W De−bouncing Programmability for Glitch Rejection During Button Press Detection.00 => No glitch rejection.01 => 8 ms duration (with 1 ms clock resolution)10 => 16 ms duration (with 2 ms clock resolution)11 => 32 ms duration (with 4 ms clock resolution)D5 0 R Reserved (Write only 0)D4 DGPIO2 0 R/W Enable GPIO2 for Headset Detection Interrupt0 => Disable GPIO2 for headset detection interrupt1 => Enable GPIO2 for headset detection interruptNote: This programmability is valid only if D15 and D13 of control register 23H/page 2 are set to0D3 DGPIO1 0 R/W Enable GPIO1 for Headset Detection Interrupt0 => Disable GPIO1 for Detection interrupt1 => Enable GPIO1 for Detection interruptNote: This programmability is valid only if D11 and D9 of control register 23H/page 2 are set to0D2 CLKGPIO2 0 R/W Enable GPIO2 for CLKOUT0 => Disable GPIO2 for CLKOUT mode.1 => Enable GPIO2 for CLKOUT mode.In CLKOUT mode the frequency of output signal is equal to the 256xDAC_FS if DAC_FS is fasterthan ADC_FS otherwise equal to the 256xADC_FS. This is valid even if ADC or DAC ispower−down.Note: This programmability is valid only if PLL is enabled, D15 and D13 of register 23H/page 2are set to 0 and GPIO2 is not enabled for detection interrupt.D1−D0 ADWSF 00 R/W ADWS Selection0X => GPIO1 pin output is three−stated.10 => GPIO1 pin acts as button press detect interrupt.11 => GPIO1 pin acts as ADC word−select (ADWS).Note: 1. This programmability is valid only if D11 and D9 of control register 23H/page 2 are setto 0.2. These bits should be programmed ‘11’ only if different ADC and DAC sample rates are desired.In this mode WCLK acts as DAWS i.e. DAC sample rate and GPIO1 acts as ADWS i.e. ADCsample rate.69

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comREGISTER 23H: GPIO ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15 GPO2EN 0 R/W GPIO2 Enable for General Purpose Output Port0 => GPIO2 is not programmed as general purpose output port1 => GPIO2 programmed as general purpose output portD14 GPO2SG 0 R/W GPIO2 Output Signal Programmability0 => GPIO2 goes to low if GPIO2 enable for general purpose output port1 => GPIO2 goes to high if GPIO2 enable for general purpose output portD13 GPI2EN 0 R/W GPIO2 Enable for General Purpose Input Port0 => GPIO2 is not programmed as general purpose input port1 => GPIO2 programmed as general purpose input portD12 GPI2SGF 0 R GPIO2 Input Signal Flag0 => GPIO2 input is low.1 => GPIO2 input is high.Note: Valid only if GPIO2 is enable for general purpose input portD11 GPO1EN 0 R/W GPIO1 Enable for General Purpose Output Port0 => GPIO1 is not programmed as general purpose output port1 => GPIO1 programmed as general purpose output portD10 GPO1SG 0 R/W GPIO1 Output Signal Programmability0 => GPIO1 goes to low if GPIO1 enable for general purpose output port1 => GPIO1 goes to high if GPIO1 enable for general purpose output portD9 GPI1EN 0 R/W GPIO1 Enable for General Purpose Input Port0 => GPIO1 is not programmed as general purpose input port1 => GPIO1 programmed as general purpose input portD8 GPI1SGF 0 R GPIO1 Input Signal Flag0 => GPIO1 input is low.1 => GPIO1 input is high.Note: Valid only if GPIO1 is enable for general purpose input portD7−D0 0 R Reserved (Write only 00000000)REGISTER 24H: AGC for Cell-Phone Input Control70BITNAMERESETVALUEREAD/WRITED15 0 R Reserved (Write only 0)FUNCTIOND14 AGCNF_CELL 0 R Noise Threshold Flag.The read values indicate the following0 => Signal power greater than noise threshold1 => Signal power is less than noise thresholdNote: Valid only if AGC is selected for the Cell−phone input (CP_IN).D13−D11 AGCNL 000 R/W AGC Noise Threshold.These settings apply to both Headset/Aux/Handset and Cell−phone input.000 => −30 dB001 => −30 dB010 => −40 dB011 => −50 dB100 => −60 dB101 => −70 dB (not valid for Cell−phone AGC)110 => −80 dB (not valid for Cell−phone AGC)111 => −90 dB (not valid for Cell−phone AGC)D10−D9 AGCHYS_CELL 00 R/W AGC Hysteresis Selection for Cell−phone Input00 => 1 dB01 => 2 dB10 => 4 dB11 => No HysteresisD8 CLPST_CELL 0 R/W AGC Clip Stepping Disable for Cell−phone Input0 => Disable clip stepping for cell-phone input1 => Enable clip stepping for cell-phone input

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004BITNAMERESETVALUEREAD/WRITEFUNCTIOND7−D5 AGCTG_CELL 000 R/W AGC Target Gain for Cell−phone Input.These three bits set the AGC’s targeted ADC output level.000 => −5.5 dB001 => −8.0 dB010 => −10 dB011 => −12 dB100 => −14 dB101 => −17 dB110 => −20 dB111 => −24 dBD4−D1 AGCTC_CELL 0000 R/W AGC Time Constant for Cell Input.These four bits set the AGC attack and decay time constants. Time constants remainthe same irrespective of any sampling frequencyAttack time Decay time(ms) (ms)0000 8 100001 11 1000010 16 1000011 20 1000100 8 2000101 11 2000110 16 2000111 20 2001000 8 4001001 11 4001010 16 4001011 20 4001100 8 5001101 11 5001110 16 5001111 20 500D0 AGCEN_CELL 0 R/W AGC Enable for Cell−phone Input0 => AGC is off for Cell−phone input1 => AGC is on for Cell−phone input(Cell PGA is controlled by AGCREGISTER 25H: Driver Power-Down StatusNote: All values reflected in control register 25H/page2 are valid only if short circuit is not detected (bit D1 ofcontrol register 1DH/page2 is set to 0)BITNAMERESETVALUEREAD/WRITEFUNCTIOND15 SPK1FL 1 R SPK1 Driver Power-down Status0 => SPK1 driver not powered down.1 => SPK1 driver powered down.D14 SPK2FL 1 R SPK2 Driver Power-down Status0 => SPK2 driver not powered down.1 => SPK2 driver powered down.D13 HNDFL 1 R OUT32N (Handset) Driver Power-down Status0 => OUT32N driver not powered down.1 => OUT32N driver powered down.D12 VGNDFL 1 R VGND Driver Power-down Status0 => VGND driver not powered down.1 => VGND driver powered down.D11 LSPKFL 1 R Loudspeaker Driver Power-down Status0 => Loudspeaker driver not powered down.1 => Loudspeaker driver powered down.D10 CELLFL 1 R Cell−phone Output (CP_OUT) Driver Power-down Status0 => Cell-phone output driver not powered down.1 => Cell-phone output driver powered down.71

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comBITNAMERESETVALUEREAD/WRITED9−D6 0000 R Reserved (Write only 0000)FUNCTIOND5 PSEQ 0 R/W Disable Drivers (SPK1/SPK2/OUT32N/VGND) Pop Sequencing0 => Enable drivers pop sequencing1 => Disable drivers pop sequencingD4 PSTIME 0 R/W Drivers (SPK1/SPK2) Pop Sequencing Duration in Cap Mode0 => 802 ms.1 => 4006 ms.D3−D0 0000 R Reserved (Write only 0000)REGISTER 26H: Mic AGC ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D9 MMPGA 1111111 R/W Max PGA Value Applicable for Headset/Aux or Handset AGC0000000 => 0 dB0000001 => 0.5 dB0000010 => 1.0 dB....1110110 => 59.0 dB............1111111 => 59.5 dBD8−D6 MDEBNS 000 R/W Debounce Time for Transition from Normal Mode to Silence Mode (Input Level is Below NoiseThreshold Programmed by AGCNL). This is Valid for Headset/Aux or Handset AGC.000 => 0 ms001 => 0.5 ms010 => 1.0 ms011 => 2.0 ms100 => 4.0 ms101 => 8.0 ms110 => 16.0 ms111 => 32.0 msD5−D3 MDEBSN 000 R/W De−bounce Time for Transition from Silence Mode to Normal Mode. This is Valid for Headset/Auxor Handset AGC.000 => 0 ms001 => 0.5 ms010 => 1.0 ms011 => 2.0 ms100 => 4.0 ms101 => 8.0 ms110 => 16.0 ms111 => 32.0 msD2−D0 000 R Reserved (Write only 000)72

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004REGISTER 27H: Cell-Phone AGC ControlBITNAMERESETVALUEREAD/WRITEFUNCTIOND15−D9 CMPGA 1111111 R/W Max. Cell‘−phone input PGA value applicable for Cell‘−phone AGC0000000 => −34.5 dB0000001 => −34 dB0000010 => −33.5 dB...1000100 => −0.5 dB1000101 => invalid1000110 => invalid...1011100 => Invalid1011101 => 12 dB1011110 => 12 dB1011111 => 12 dB11xxxxx => 12 dBD8−D6 CDEBNS 000 R De−bounce Time for Transition from Normal Mode to Silence Mode (Input Level isBelow Noise Threshold Programmed by AGCNL). This is Valid for Cell−phone AGC.000 => 0 ms001 => 0.5 ms010 => 1.0 ms011 => 2.0 ms100 => 4.0 ms101 => 8.0 ms110 => 16.0 ms111 => 32.0 msD5−D3 CDEBSN 000 R De−bounce Time for Transition from Silence Mode to Normal Mode. This is Valid forCell−phone AGC.000 => 0 ms001 => 0.5 ms010 => 1.0 ms011 => 2.0 ms100 => 4.0 ms101 => 8.0 ms110 => 16.0 ms111 => 32.0 msD2−D0 000 R Reserved (Write only 000)TSC2101 Buffer Data Registers (Page 3)The buffer data registers of the TSC2101 hold data results from the SAR ADC conversions in buffer mode. Uponreset, bit D15 is set to 0, bit D14 is set to 1 and the remaining bits are don’t−care. These registers are read only.If buffer mode is enabled, then the results of all ADC conversions are placed in the buffer data register. Thedata format of the result word (R) of these registers is right-justified which is as follows:D15MSBD14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0LSBFUF EMF X ID R11MSBBITNAMERESETVALUEREAD/WRITER10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0LSBFUNCTIOND15 FUF 0 R Buffer Full FlagThis flag indicates that all the 64 locations of the buffer are having unread data.D14 EMF 1 R Buffer Empty FlagThis flag indicates that there is no unread data available in FIFO. This is generated while reading thelast converted data.D13 X R Reserved73

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.com74BITNAMERESETVALUEREAD/WRITEFUNCTIOND12 ID X R Data Identification0 => X or Z1 coordinate or BAT or AUX2 data in R11−R01 => Y or Z2 coordinate or AUX1 or TEMP data in R11−R0Order for Writing Data in Buffer When Multiple Inputs are SelectedFor XY Conversion: Y, XFor XYZ1Z2 Conversion: Y, X, Z1, Z2For Z1Z2 Conversion: Z1, Z2For Auto Scan Conversion: AUX1 (if selected), AUX2 (if selected), TEMP (if selected)For Port Scan Conversion: BAT, AUX1, AUX2D11−D0 R11−R0 X’s R Converted DataLAYOUTThe following layout suggestions should provide optimum performance from the TSC2101. However, manyportable applications have conflicting requirements concerning power, cost, size, and weight. In general, mostportable devices have fairly clean power and grounds because most of the internal components are very lowpower. This situation would mean less bypassing for the converter’s power and less concern regardinggrounding. Still, each situation is unique and the following suggestions should be reviewed carefully.For optimum performance, care should be taken with the physical layout of the TSC2101 circuitry. The basicSAR architecture is sensitive to glitches or sudden changes on the power supply, reference, groundconnections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore,during any single conversion for an n-bit SAR converter, there are n windows in which large external transientvoltages can easily affect the conversion result. Such glitches might originate from switching power supplies,nearby digital logic, and high power devices. The degree of error in the digital output depends on the referencevoltage, layout, and the exact timing of the external event. The error can change if the external event changesin time with respect to the timing of the critical n windows.With this in mind, power to the TSC2101 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitorshould be placed as close to the device as possible. A 1 µF to 10 µF capacitor may also be needed if theimpedance of the connection between the TSC2101 supply pins and system power supply is high.A bypass capacitor on the VREF pin is generally not needed because the reference is buffered by an internalop amp, although it can be useful to reduce reference noise level. If an external reference voltage originatesfrom an op amp, make sure that it can drive any bypass capacitor that is used without oscillation.The TSC2101 architecture offers no inherent rejection of noise or voltage variation in regards to using anexternal reference input. This is of particular concern when the reference input is tied to the power supply. Anynoise and ripple from the supply appears directly in the digital results. While high frequency noise can be filteredout, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.The ground pins should be connected to a clean ground point. In many cases, this is the analog ground. Avoidconnections, which are too near the grounding point of a microcontroller or digital signal processor. If needed,run a ground trace directly from the converter to the power supply entry or battery connection point. The ideallayout includes an analog ground plane dedicated to the converter and associated analog circuitry.In the specific case of use with a resistive touch screen, care should be taken with the connection between theconverter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnectionshould be as short and robust as possible. Loose connections can be a source of error when the contactresistance changes with flexing or vibrations.As indicated previously, noise can be a major source of error in touch-screen applications (e.g., applicationsthat require a back-lit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screenand cause flickering of the converted ADC data. Several things can be done to reduce this error, such as utilizinga touch screen with a bottom−side metal layer connected to ground. This couples the majority of noise toground. Additionally, filtering capacitors, from Y+, Y–, X+, and X– to ground, can also help. Note, however, thatthe use of these capacitors increases screen settling time and require longer panel voltage stabilization times,as well as increased precharge and sense times for the PINTDAV circuitry of the TSC2101.

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004CONVERSION TIME CALCULATIONS FOR THE TSC2101Touch Screen Conversion Initiated at Touch DetectThe time needed to get a converted X/Y coordinate for reading can be calculated by (not including the timeneeded to send the command over the SPI bus):t t tt 2 coordinate PRE SNS PVS125 ns t OSC 2 N AVGN BITS1 8MHz n 1 12 ƒ conv1 t OSC 18 t OSC n 2 t OSC n 3 t OSCwhere:t coordinate = time to convert X/Y coordinatet PVS = Panel voltage stabilization timet PRE = precharge timet SNS = sense timeN AVG = number of averages; for no averaging, N AVG = 1N BITS = number of bits of resolutionƒ conv = A/D converter clock frequencyt OSC = Oscillator clock periodn 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHzn 2 = 4 ; if t PVS = 0 µs0 ; if t PVS ≠ 0 µsn 3 = 0 ; if t SNS = 32 µs2 ; if t SNS ≠ 32 µst PGDEL = Programmable delay in between conversion for touch screen measurement= 0: if programmable delay mode is disabled for touch screen measurement(1)t PGDEL delay is generated by using: Internal oscillator clock whose typical frequency is 1 MHz, in internal clockmode, or MCLK/CLKDIV (as programmed in control register 14H/pag1) in external clock mode.(2)The above formula is valid exactly only when the codec is powered down. Also after touch detect the formula holdstrue from second conversion onwards.(3)If D15−D14 of control register 01H/page 1 = 00, then in case of continuous touch PINTDAV remains high fort PRE t SNS t OSC125 ns . If D15−D14 of control register 01H/page 1 = 10/11, then in case of continuous touchPINTDAC remains high for t PRE t SNS t OSC 125 ns t PGDEL .Programmedfor SelfControlledX−Y ScanModeSS DEACTIVATEDReadingX−DataRegisterReadingY−DataRegisterDetecting TouchSample,Conversion &Averaging forY−CoordinateDetectingTouchSample,Conversion &Averaging forX−CoordinateDetectingTouchSample,Conversion &Averaging forY−CoordinateDetectingTouchPINTDAV(As PENIRQ[D15−D14 = 00])PINTDAV(As DATA_AVA[D15−D14 = 01])Touch Is DetectedPINTDAV(As PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch Is DetectedTouch Is Detected75

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comThe time for a complete X/Y/Z1/Z2 coordinate conversion is given by(not including the time needed to sendthe command over the SPI bus):Programmedfor HostControlledModeREG−00 ofPAGE−01Is UpdatedforX−Y ScanModeSS DEACTIVATEDReadingX−DataRegisterReadingY−DataRegisterDetecting TouchWaiting for Host toWrite into REG−00 ofPAGE−01Sample,Conversion &Averaging forY−CoordinateDetectingTouchSample,Conversion &Averaging forX−CoordinateDetectingTouchSample,Conversion &Averaging forY−CoordinateDetectingTouchPINTDAV(As PENIRQ[D15−D14 = 00])Touch Is DetectedTouch Is DetectedPINTDAV(As DATA_AVA[D15−D14 = 01])PINTDAV(As PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch Is Detectedt t tt 3 coordinate PRE SNS PVS125 ns t OSC 4 N AVGN BITS1 8MHz n 1 12 ƒ conv1 t OSC 33 t OSC n 2 t OSC n 3 t OSC t PGDELn 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHzn 2 = 4 ; if t PVS = 0 µs0 ; if t PVS ≠ 0 µsn 3 = 0 ; if t SNS = 32 µs3 ; if t SNS ≠ 32 µsProgrammedfor SelfControlledX−Y−Z1−Z2ScanModeSS DEACTIVATEDReading Reading Reading ReadingX−Data Y−Data Z1−Data Z2−DataRegister Register Register RegisterSample,Conversion &Detecting Touch Averaging forY−CoordinateDetectingTouchSample,Conversion &DetectingAveraging forTouchX−CoordinateTouch Is Detected Touch Is Detected Touch Is DetectedSample,Conversion &Averaging forZ1−Coordinate & Z2−CoordinateDetectingTouchSample,Conversion &Averaging forY−CoordinateDetectingTouchPINTDAV(As PENIRQ[D15−D14 = 00])PINTDAV(As DATA_AVA[D15−D14 = 01])PINTDAV(As PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch Is DetectedThe time needed to convert any single coordinate either X or Y under self-controlled (not including the time needed to sendthe command over the SPI bus) is given by:76t t tt coordinate PRE SNS PVS125 ns t OSC N AVGN BITS1 8MHz n 1 12 ƒ conv1n 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHz t OSC 16 t OSC n 2 t OSC n 3 t OSC t PGDEL

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004n 2 = 2 ; if t PVS = 0 µs0 ; if t PVS ≠ 0 µsn 3 = 0 ; if t SNS = 32 µs0 ; if t SNS ≠ 32 µsProgrammedfor SelfControlledX ScanMode/SS DEACTIVATEDReadingX−Data RegisterDetecting TouchSample,Conversion &Averaging forX−CoordinateDetectingTouchSample,Conversion &Averaging forX−Coordinate/PINTDAV(As /PENIRQ[D15−D14 = 00])Touch is detectedTouch is detected/PINTDAV(As DATA_AVA[D15−D14 = 01])/PINTDAV(As /PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch is detectedThe time needed to convert the Z coordinate under self-controlled mode (not including the time needed to send thecommand over the SPI bus) is given by:t t tt coordinate PRE SNS PVS125 ns t OSC 2 N AVGN BITS1 8MHz n 1 12 ƒ conv1 t OSC 22 t OSC n 2 t OSC n 3 t OSC t PGDELn 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHzn 2 = 2 ; if t PVS = 0 µs0 ; if t PVS ≠ 0 µsn 3 = 0 ; if t SNS = 32 µs1 ; if t SNS ≠ 32 µsProgrammedfor SelfControlledZ ScanMode/SS DEACTIVATEDReading ReadingZ1−Data Z2−DataRegister RegisterDetecting TouchSample,Conversion &Averaging forZ1−Coordinate & Z2−CoordinateDetectingTouchSample,Conversion &Averaging forZ1−Coordinate & Z2−Coordinate/PINTDAV(As /PENIRQ[D15−D14 = 00])Touch is detectedTouch is detected/PINTDAV(As DATA_AVA[D15−D14 = 01])/PINTDAV(As /PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch is detected77

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comTouch Screen Conversion Initiated by the HostThe time needed to convert any single coordinate either X or Y under host-controlled mode (not including the timeneeded to send the command over the SPI bus) is given by:t t coordinate PVS125 ns t OSC N AVGN BITS1 8MHz n 1 12 1ƒ convn 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHzn 2 = 2 ; if t PVS = 0 µs0 ; if t PVS ≠ 0 µs t OSC 14 t OSC n 2 t OSCProgrammedfor HostControlledModeREG−00 ofPAGE−01is updatedforX ScanMode/SS DEACTIVATEDReadingX−DataRegisterDetecting TouchWaiting for Host to writeinto REG−00 of PAGE−01Sample,Conversion &Averaging forX−CoordinateDetectingTouchWaiting for Host to write intoREG−00 of PAGE−01/PINTDAV(As /PENIRQ[D15−D14 = 00])Touch is detected/PINTDAV(As /DATA_AVA[D15−D14 = 01])/PINTDAV(As /PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch is still theret t coordinate PVS125ns t OSC 2 N AVGN BITS1 8MHz t 20 t n OSC OSC 2 t OSCn 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHzn 2 = 2 ; if t PVS = 0 µs0 ; if t PVS ≠ 0 µsƒ conv n 1 12 178

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Programmedfor HostControlledModeREG−00 ofPAGE−01is updatedforZ1−Z2 ScanMode/SS DEACTIVATEDReading ReadingZ1−Data Z2−DataRegister RegisterDetecting TouchWaiting for Host to writeinto REG−00 of PAGE−01Sample,Conversion &Averaging forZ1−Coordinate & Z2−CoordinateDetectingTouchWaiting for Host to write intoREG−00 of PAGE−01/PINTDAV(As /PENIRQ[D15−D14 = 00])Touch is detected/PINTDAV(As /DATA_AVA[D15−D14 = 01])/PINTDAV(As /PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch is still thereProgrammedfor HostControlledModeREG−00 ofPAGE−01Is UpdatedforX−Y ScanModeSS DEACTIVATEDReadingX−DataRegisterReadingY−DataRegisterDetecting TouchWaiting for Host toWrite into REG−00 ofPAGE−01Sample,Conversion &Averaging forY−CoordinateDetectingTouchSample,Conversion &Averaging forX−CoordinateDetectingTouchSample,Conversion &Averaging forY−CoordinateDetectingTouchPINTDAV(As PENIRQ[D15−D14 = 00])Touch Is DetectedTouch Is DetectedPINTDAV(As DATA_AVA[D15−D14 = 01])PINTDAV(As PENIRQ & DATA_AVA[D15−D14 = 10/11])Touch Is DetectedNon-Touch Screen Measurement OperationThe time needed to make temperature, auxiliary, or battery measurements is given by:t N AVGN BITS 1 8MHzƒ conv n 1 n 2 1 t OSC 15 t OSC n 3 t OSCwhere:n 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHzn 2 = 24 ; if measurement is for TEMP1 case12 ; if measurement is for other than TEMP1 case400 ns; if measurement is for the external/internal resistance using AUX1/AUX2n 3 = 0 ; if external reference mode is selected3 ; if t REF = 0 µs or reference is programmed for power up all the time.1 + t REF /125 ns; if t REF ≠ 0 µs and reference needs to power down between conversions.t REF is the reference power up delay time.79

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comProgrammed forHost ControlledMode With InvalidA/D FunctionSelectedREG−00 ofPAGE−01Is UpdatedforBAT1 ScanModeSS DEACTIVATEDReadingBAT1−DataRegisterDetecting TouchWaiting for Host to Writeinto REG−00 of PAGE−01Wait for Reference Power-Up Delay in Caseof Internal Ref Mode if ApplicableSample,Conversion &Averaging forBAT1 inputWaiting for Host toWrite into REG−00of PAGE−01PINTDAV(As DATA_AVA[D15−D14 = 01])The time needed for continuous autoscan mode is given by:t N INPN AVGN BITS 1 8MHzƒ conv n 1 12 1 t OSC 8 t OSC n 2 t t n OSC DEL 3 t n OSC 4 t OSCwhere:N INP = 1; if autoscan is selected for only one input AUX1, AUX2, TEMP1 or TEMP2= 2; if autoscan is selected for two inputs AUX1−AUX2, AUX1−TEMP1, AUX1−TEMP2 etc= 3; if autoscan is selected for three inputs AUX1−AUX2−TEMP1 or AUX1−AUX2−TEMP2n 1 = 6 ; if f conv = 8 MHz7 ; if f conv p 8 MHzn 2 = 12 ; if one of the input selected is TEMP10 ; if measurement is for other than TEMP1n 3 = 0 ; if external reference mode is selected or t DEL = 0.3 ; if t REF = 0 ms or reference is programmed for power up all the times.1 + t REF /125 ns ; if t REF p 0us and reference needs to power down between conversions.t REF is the reference power up delay time.n 4 = 0 ; if t DEL = 0.= 7 ; if t DEL p 0t DEL = Programmable delay in between conversion for nontouchscreen measurement= 0 ; if programmable delay mode is disabled for nontouchscreen measurement(1)The above equation is valid only from second conversion onwards.(2)t DEL delay is generated by using internal oscillator clock whose typical frequency is 1 MHz in internal clock mode,or MCLK/CLKDIV (as programmed in control register 14H/page 1) in external clock mode.Programmed forHost ControlledMode With InvalidA/D FunctionSelectedREG−00 ofPAGE−01Is Updatedfor ContinousAUX SCANModeSS DEACTIVATEDReadingAUX−DataRegisterReadingAUX−DataRegisterDetecting TouchWaiting for Host toWrite into REG−00of PAGE−01Wait for Reference Power-Up Delay in Caseof Internal Ref Mode if ApplicableSample,Conversion &Averaging forAUX inputSample,Conversion &Averaging forAUX inputSample,Conversion &Averaging forAUX inputPINTDAV(As DATA_AVA[D15−D14 = 01])80

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Port Scan OperationThe time needed to complete one set of port scan conversions is given by:t 3 N N coordinate AVG BITS1 8MHz n 1 12 1 t 31 t n OSC OSC 2 t OSCƒ convwhere:n 1 = 6 ; if ƒ conv = 8 MHz7 ; if ƒ conv ≠ 8 MHzn 2 = 0 ; if external reference mode is selected3 ; if t REF = 0 µs or reference is programmed for power up all the time.1 + t REF /125 ns; if t REF ≠ 0 µs and reference needs to power down between conversions.t REF is the reference power up delay time.Programmed forHost ControlledMode With InvalidA/D FunctionSelectedREG−00 ofPAGE−01is updatedforPORT SCANModeSS DEACTIVATEDReadingBAT1−DataRegisterReadingBAT2−DataRegisterReadingAUX−DataRegisterDetecting TouchWaiting for Host toWrite into REG−00of PAGE−01Wait for Reference Power-Up Delay in Caseof Internal Ref Mode if ApplicableSample,Conversion &Averaging forBAT1 & BAT2 & AUX inputWaiting for Host to Write into REG−00of PAGE−01PINTDAV(As DATA_AVA[D15−D14 = 01])ADC CHANNEL DIGITAL FILTER FREQUENCY RESPONSESFigure 39. Pass-Band Frequency Response of ADC Digital Filter81

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comFigure 40. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.0045 Fs)Figure 41. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.0125 Fs)82

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Figure 42. Frequency Response of ADC High-Pass Filter (Fcutoff = 0.025 Fs)DAC CHANNEL DIGITAL FILTER FREQUENCY RESPONSESFigure 43. DAC Channel Digital Filter Frequency Response83

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comFigure 44. DAC Channel Digital Filter Pass-Band Frequency ResponseFigure 45. Default Digital Audio Effects Filter Frequency Response at 48 Ksps84

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Figure 46. De-Emphasis Filter Response at 32 KspsFigure 47. De-Emphasis Error at 32 Ksps85

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comFigure 48. De-Emphasis Filter Frequency Response at 44.1 KspsFigure 49. De-Emphasis Error at 44.1 Ksps86

www.ti.comSLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004Figure 50. De-Emphasis Frequency Response at 48 KspsFigure 51. De-Emphasis Error at 48 Ksps87

SLAS392C− JUNE 2003 − REVISED SEPTEMBER 2004www.ti.comPLL PROGRAMMINGThe on-chip PLL in the TSC2101 can be used to generate sampling clocks from a wide range of MCLK’savailable in a system. The PLL works by generating oversampled clocks with respect to Fsref (44.1 kHz or48 kHz). Frequency division generates all other internal clocks. Table 7 and Table 8 gives a sampleprogramming for PLL registers for some standard MCLK’s when PLL is required. Whenever the MCLK is of theform of N × 128 × Fsref (N=2,3,...), the PLL is not required.Table 7. Fsref = 44.1 kHzMCLK (MHz) P J D ACHIEVED FSREF % ERROR2.8224 1 32 0 44100.00 0.00005.6448 1 16 0 44100.00 0.000012 1 7 5264 44100.00 0.000013 1 6 9474 44099.71 0.000716 1 5 6448 44100.00 0.000019.2 1 4 7040 44100.00 0.000019.68 1 4 5893 44100.30 −0.000748 4 7 5264 44100.00 0.0000Table 8. Fsref = 48 kHzMCLK (MHz) P J D ACHIEVED FSREF % ERROR2.048 1 48 0 48000.00 0.00003.072 1 32 0 48000.00 0.00004.096 1 24 0 48000.00 0.00006.144 1 16 0 48000.00 0.00008.192 1 12 0 48000.00 0.000012 1 8 1920 48000.00 0.000013 1 7 5618 47999.71 0.000616 1 6 1440 48000.00 0.000019.2 1 5 1200 48000.00 0.000019.68 1 4 9951 47999.79 0.000448 4 8 1920 48000.00 0.000088

PACKAGE OPTION ADDENDUMwww.ti.com4-Apr-2005PACKAGING INFORMATIONOrderable Device Status (1) PackageTypePackageDrawingPins PackageQtyEco Plan (2) Lead/Ball Finish MSL Peak Temp (3)TSC2101IRGZ ACTIVE QFN RGZ 48 297 TBD CU NIPDAU Level-2-235C-1 YEARTSC2101IRGZR ACTIVE QFN RGZ 48 2500 TBD CU NIPDAU Level-2-235C-1 YEARTSC2101IRGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS &no Sb/Br)CU NIPDAULevel-2-260C-1 YEAR(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.Addendum-Page 1

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