intermittency detection and mitigation in ball grid array (bga) packages
intermittency detection and mitigation in ball grid array (bga) packages
intermittency detection and mitigation in ball grid array (bga) packages
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INTERMITTENCY DETECTION AND MITIGATION IN BALL GRIDARRAY (BGA) PACKAGESJames P. HofmeisterSr. Pr<strong>in</strong>cipal Eng<strong>in</strong>eerRidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300hoffy@ridgetopgroup.comEdgar G. OrtizApplication Eng<strong>in</strong>eerRidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300edgar@ridgetopgroup.comPradeep LallThomas Walter ProfessorAuburn UniversityDept of MechanicalEng<strong>in</strong>eer<strong>in</strong>g <strong>and</strong> CAVEAuburn, AL 36849(334) 844-3424lall@eng.auburn.eduMathieu G.P. AdamsDesign Eng<strong>in</strong>eerRidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300mathieu@ridgetopgroup.comDouglas GoodmanCEORidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300doug@ridgetopgroup.comTerry A. TracySr. Pr<strong>in</strong>cipal Eng<strong>in</strong>eerRaytheon MissileSystemsBldg. M02, MS T151151 Hermans RoadTucson, AZ 85706-1151(520) 794-3962TATracy@Raytheon.comAbstract – An update on a method (SJ BIST)to detect <strong>in</strong>termittencies <strong>in</strong> Ball Grid Array(BGA) <strong>packages</strong> is presented, <strong>and</strong> anothermethod (SJ Monitor) is <strong>in</strong>troduced. SJBIST is primarily firmware embedded <strong>in</strong> theFPGA application; SJ Monitor is hardwareon an IC chip.Failure of monitored I/O p<strong>in</strong>s on operational,fully-programmed FPGAs is reported by SJBIST <strong>and</strong> SJ Monitor to provide positive<strong>in</strong>dication of damage to one or more I/Osolder-jo<strong>in</strong>t networks of an FPGA on anelectronic digital board. The board can thenbe replaced before accumulated fatiguedamage results <strong>in</strong> <strong>in</strong>termittent or long-last<strong>in</strong>goperational faults.INTRODUCTIONSJ BIST is an <strong>in</strong>novative, solder-jo<strong>in</strong>t built-<strong>in</strong>self-test that is <strong>in</strong>-situ with<strong>in</strong> an FPGA to detecthigh-resistance damage to solder-jo<strong>in</strong>t networksof fully operational Field Programmable GateArrays (FPGAs) <strong>in</strong> <strong>ball</strong>-<strong>grid</strong> <strong>array</strong> (BGA) <strong>packages</strong>such as a XILINX® FG1152/FG1156 [1]. SJMonitor uses <strong>in</strong>novative circuit design on an ICchip <strong>in</strong>-situ on an FPGA board to provide amethod to monitor I/O p<strong>in</strong>s 24x7 at much lesspower than SJ BIST. FPGAs are used <strong>in</strong> allmanner <strong>and</strong> k<strong>in</strong>ds of control systems <strong>in</strong> bothdefense <strong>and</strong> commercial applications.SJ BIST is a two-port firmware core to be <strong>in</strong>cluded<strong>in</strong> operational, fully-programmed FPGAs: SJMonitor is a transistor-level circuit to be realizedas an Integrated Circuit (IC) on a chip. Bothcorrectly detect <strong>and</strong> report <strong>in</strong>stances of resistanceat least as low as 100 Ω without false alarms. TheCenter for Advanced Vehicle Electronics (CAVE)at Auburn University is runn<strong>in</strong>g Highly AcceleratedLife Test (HALT) experiments to verify correctoperation <strong>and</strong> to collect statistics; RaytheonMissile Systems, Tucson, Arizona, has purchasedSJ BIST demonstration boxes; <strong>and</strong> a largeautomobile manufacturer has contracted for SJBIST experiment <strong>and</strong> evaluation assistance.Mechanics-of-FailureSolder-jo<strong>in</strong>t damage under thermo-mechanical<strong>and</strong> shock stresses is cumulative <strong>and</strong> ismanifested as plastic work lead<strong>in</strong>g to voids <strong>and</strong>cracks, as seen <strong>in</strong> Figure 1; cracks propagate tobecome fractures [2-5] which cause FPGAoperational faults. Thermo-mechanical stresses
are ground connection p<strong>in</strong>s. The next nearest I/Oports at each corner are strong c<strong>and</strong>idates fortest<strong>in</strong>g by SJ BIST <strong>and</strong> monitor<strong>in</strong>g by SJ Monitorbecause those I/O ports are likely to fail first.State of the ArtThe use of lead<strong>in</strong>g <strong>in</strong>dicators of failure forprognostication of electronics has been previouslydemonstrated [12-15]. One important reason forus<strong>in</strong>g <strong>in</strong>-situ solder-jo<strong>in</strong>t fault sensors is thatstress magnitudes are hard to derive, much lesskeep track of, which leads to <strong>in</strong>accurate lifeexpectancy predictions [16]. Another reason isthat even though a particular damaged solder-jo<strong>in</strong>tport might not result <strong>in</strong> immediate FPGAoperational faults, detected faults by sensors<strong>in</strong>dicates the FPGA is likely to have, or will soonhave, other I/O ports that are damaged – theFPGA is no longer reliable. SJ BIST can be used<strong>in</strong> newly designed manufactur<strong>in</strong>g reliability tests toaddress a concern that failure modes caused bythe PWB-FPGA assembly are not be<strong>in</strong>g detecteddur<strong>in</strong>g component qualification [7].These sensor methods are the first known fordetect<strong>in</strong>g faults <strong>in</strong> solder-jo<strong>in</strong>t networks of I/Oports of operational, fully-programmed FPGAs.Furthermore, FPGAs are not amenable to themeasurement techniques typically used <strong>in</strong>manufactur<strong>in</strong>g reliability tests such as HighlyAccelerated Life Tests (HALTs) [5]. This isbecause, for example, a 4-po<strong>in</strong>t probemeasurement requires devices to be powered-off;<strong>and</strong> because FPGA I/O ports are digital, ratherthan analog, circuits (see Figure 4).Modern BGA FPGAs have more than a thous<strong>and</strong>p<strong>in</strong>s <strong>and</strong> very small pitch <strong>and</strong> <strong>ball</strong> sizes, forexample, Figure 5 shows the bottom of a XILINXFG1156 with a footpr<strong>in</strong>t of 35x35 mm 2 , <strong>and</strong> an<strong>array</strong> of 34x34 solder <strong>ball</strong>s.The dense <strong>array</strong> of f<strong>in</strong>e-pitch <strong>and</strong> ultra f<strong>in</strong>e-pitchBGA <strong>packages</strong> with very small pitch <strong>and</strong> solder<strong>ball</strong> tends to make physical, optical <strong>and</strong> other<strong>in</strong>spection techniques impractical for detect<strong>in</strong>g theonset of damage.ReadLogicWriteLogicIO PORTFigure 4: FPGA Diagram, I/O Buffer [17,18].Figure 5: XILINX FG1156: Size is 35x35 mm 2 ;Pitch: 1.0 mm. Ball: 0.6 mm [17,18].SJ BISTSJ BIST requires the attachment of a smallcapacitor to an unused I/O port as near aspossible to a corner of the package. Figure 6 is ablock diagram of an FPGA conta<strong>in</strong><strong>in</strong>g SJ BISTwith a capacitor connected to two I/O p<strong>in</strong>s.FPGAInput BufferOutput BufferDieSJ BISTSolder Bump/Bond<strong>in</strong>g:Die to BaseSimplifiedESDSOLDER BALLDiePadCeramic BaseBoardSolder BallPCBL<strong>and</strong>PCBBoardFAULTCAPACITOR VOLTAGEFigure 6: SJ BIST Block Diagram
Referr<strong>in</strong>g to Figure 6, SJ BIST writes a logical ‘1’to charge the capacitor <strong>and</strong> then reads the voltageacross the charged capacitor. If the solder-jo<strong>in</strong>tnetwork of the I/O port of the FPGA isundamaged, the write causes the capacitor to befully charged <strong>and</strong> a logical ‘1’ is read by SJ BIST.When the solder-jo<strong>in</strong>t network is damaged, theeffective resistance of the SJ network <strong>in</strong>creases,the charg<strong>in</strong>g time constant <strong>in</strong>creases, the writefails to sufficiently charge the capacitor, <strong>and</strong> alogical ‘0’ <strong>in</strong>stead of a logical ‘1’ is read: a faultoccurs, is detected by SJ BIST <strong>and</strong> is reported.capacitance of the I/O port was sufficient – noexternal capacitance needed to be connected,<strong>and</strong> SJ BIST correctly detected faults with noalarms.(A)Test ResultsSJ BIST was synthesized, programmed <strong>in</strong>to testFPGAs <strong>and</strong> tested at various clock frequenciesrang<strong>in</strong>g from 10 KHz to 100 MHz <strong>and</strong> for vary<strong>in</strong>gsolder-jo<strong>in</strong>t network conditions rang<strong>in</strong>g from nofault to over 100 Ω of fault resistance: All faults of100 Ω or larger were detected, <strong>and</strong> there were nofalse alarms.(B)Solder Jo<strong>in</strong>t No Fault <strong>and</strong> Fault TestsReferr<strong>in</strong>g to Figure 7, two sets of voltages on a1.0 µF capacitor connected to a group of two I/Oports are shown. Figure 7A shows the capacitorvoltage when one of the two ports connected tothe capacitor has a 1 Ω resistor connected <strong>in</strong>series with the solder jo<strong>in</strong>t: the resistance is nothigh enough cause a write fault to occur, <strong>and</strong> SJBIST correctly did not report a detected fault.Figure 7: SJ BIST: 1 MHz Capacitor Signal.Top is for a No Fault Condition; Bottom is for aFault Condition (100 Ω) ) − 0.5 µs x 2.0V Grid.Figure 7B shows the capacitor voltage when theresistance is <strong>in</strong>creased to 100 Ω, a write faultoccurs. SJ BIST correctly reported the fault <strong>and</strong><strong>in</strong>cremented the fault count for that I/O p<strong>in</strong>.Clock Frequency, Capacitor Value <strong>and</strong>Detectable Fault ResistanceThere is a relationship between the frequency ofthe FPGA clock, the value of the connectedcapacitor to each group of two I/O p<strong>in</strong>s, <strong>and</strong> thedetectable fault resistance. Figure 8 shows theresults of tests conducted <strong>in</strong> September of 2006:For a given clock frequency, there is a capacitorvalue that will cause SJ BIST to always detect afault resistance at least as low as 100 Ω.For clock frequencies of one-half or higher of themaximum clock frequency of the FPGA, theFigure 8: Clock Frequency, External CapacitorValue <strong>and</strong> Detectable Fault Resistance – Sep.2006.
SJ BIST Sensitivity <strong>and</strong> ResolutionGiven a correctly selected pair of CLK frequencies<strong>and</strong> capacitor values, SJ BIST is guaranteed todetect all faults at least as low as 100 Ω(sensitivity) when the fault lasts at least two clockperiods (resolution). For faults of shorter duration,the fault is detectable when it occurs shortlybefore the write <strong>and</strong> when it lasts about one-halfof the clock period.SJ BIST SignalsSJ BIST needs to present at least one error signal(a fault <strong>in</strong>dicator) either to an external FPGA I/Oport or to an <strong>in</strong>ternal fault management program.At least one control signal is required: an enable(disable) BIST.SJ Monitor is a passive detector capable ofdetect<strong>in</strong>g a voltage perturbation <strong>in</strong> a solder-jo<strong>in</strong>tnetwork caused by a resistance spike at least aslow as 100 Ω. We have successfully designed<strong>and</strong> simulated SJ Monitor at 3.3 V for a TSMC®0.25-µm process, <strong>and</strong> at 1.2 V <strong>and</strong> 2.5 V for anIBM® 130-nm process node.We <strong>in</strong>tend to realize, package, test <strong>and</strong>characterize SJ Monitor for a 1.2 V, 130-nmprocess. We have not made any decision as tothe number of SJ Monitor cells to put on each ICchip. Board wir<strong>in</strong>g constra<strong>in</strong>ts might require us toonly put 4 cells on each IC chip; this might thenrequire the plac<strong>in</strong>g of two SJ Monitor chips on theboard.Error Signals <strong>and</strong> Fault CountsIn addition to record<strong>in</strong>g fault counts, the SJ BISTcore has two error signals: (1) at least one faulthas been detected <strong>in</strong> the 2-port network be<strong>in</strong>gtested <strong>and</strong> (2) at least one fault is currently active.A fault counter (1:255) is provided. For adeployed SJ BIST, we anticipate mostapplications would only use the two error signals.We also believe a deployed SJ BIST applicationwould most likely use at least four groups of cores– one group of two I/O p<strong>in</strong>s near each corner ofan FPGA.Control SignalsIn addition to CLK, the SJ BIST core has two <strong>in</strong>putsignals: ENABLE <strong>and</strong> RESET. ENABLE is usedto turn SJ BIST <strong>detection</strong> on <strong>and</strong> off; RESET isused to reset both the fault signal latches <strong>and</strong> thefault counters. For a deployed SJ BIST, RESETmight not be used.SJ MONITORSJ Monitor is designed <strong>and</strong> is be<strong>in</strong>g developed asan Integrated Circuit (IC) chip, which must bemounted next to <strong>and</strong> connected to the FPGA onthe board. SJ Monitor is a low-power, cont<strong>in</strong>uousmonitor<strong>in</strong>g sensor: at 1.2 V to 2.5 V, it uses lessthan 5.0 mW to monitor 8 I/O p<strong>in</strong>s. SJ BIST has apower requirement of over 100 mW to test 8 I/Op<strong>in</strong>s. A block diagram representation of SJMonitor is shown <strong>in</strong> Figure 9.Figure 9: SJ Monitor Block DiagramAlthough an active I/O port is shown <strong>in</strong> Figure 9,an active port is not a requirement: the onlyrequirement is the port must be at logical zerolevel.Simulation ResultsMeasurements <strong>and</strong> evaluations of various FPGAsfrom more than one manufacturer <strong>in</strong>dicate that forI/O ports pulled low <strong>and</strong> sourced with externalcurrents of less than 0.5 mA, the noise on anoutput I/O port is much less than 2.5 mV. Thisallowed us to design SJ Monitor to source lessthan 200 µA to each monitored I/O p<strong>in</strong> of anFPGA. We have verified we can easily changethe design to h<strong>and</strong>le a higher level of sourcecurrent to overcome a greater-than-expectednoise marg<strong>in</strong>.A complementary version of SJ Monitor us<strong>in</strong>gnegative 1.2 V power was designed <strong>and</strong>simulated: It provides a monitor<strong>in</strong>g capability forFPGAs that are powered off.
Noise Rejection <strong>and</strong> Fault DetectionWe simulated DC pull-down levels from 0 to over300 mV with noise perturbations of 2.0 to 3.0 mV,which is about 3 times larger than the maximumlevel of noise we measured.Referr<strong>in</strong>g to Figure 10, (A) shows an I/O p<strong>in</strong> with apull-down voltage level of 10 mV <strong>and</strong> (B) showsan I/O p<strong>in</strong> with a pull-down voltage level of 100mV. Superimposed on each of the pull-downvoltage levels are 3.0 mV noise pulses <strong>and</strong> 9.5mV fault perturbations. The fault perturbationsare caused by <strong>in</strong>ject<strong>in</strong>g a 100 Ω fault <strong>in</strong>to thesolder-jo<strong>in</strong>t network.(A)<strong>and</strong> 100 o C; <strong>and</strong> (4) the complementary version ofSJ Monitor was simulated us<strong>in</strong>g negative powervoltages of -1.08V, -1.20 V <strong>and</strong> -1.32 V. For allvariations, SJ Monitor produced correct results: allfaults detected <strong>and</strong> no false alarms.Figure 11: SJ Monitor Fault Signal Responseto Figure 10 A <strong>and</strong> B.SJ Monitor Sensitivity <strong>and</strong> Resolution(B)The value of the m<strong>in</strong>imum detectable faultresistance is primarily dependent on the durationof the fault <strong>and</strong> the operat<strong>in</strong>g temperature asshown <strong>in</strong> Figure 12. The results <strong>in</strong>dicate that SJMonitor is able to detect a fault resistance at leastas low as 100 Ω when the fault duration is at leastas long as 20 ns.Figure 10: FPGA I/O P<strong>in</strong> Voltages: (A) Pulldownis 10 mV <strong>and</strong> (B) Pull-down is 100 mV;Noise is 3.0 mV, Fault Perturbation is 19.5 mV.SJ Monitor is <strong>in</strong>sensitive to a specific value of pulldownvoltage: Both of the <strong>in</strong>put conditions seen <strong>in</strong>Figure 10 result <strong>in</strong> the output shown <strong>in</strong> Figure 11.SJ Monitor uses signal condition<strong>in</strong>g to ignore thepull-down voltage level, to suppress noise <strong>and</strong> toamplify the fault perturbation to produce a digitalfault signal.Simulations were performed us<strong>in</strong>g variations <strong>in</strong>circuit parameters: (1) 10 to 20 percent variation<strong>in</strong> transistor widths <strong>and</strong> lengths were used; (2)three different power supply voltage levels wereused – 1.08 V, 1.20 V <strong>and</strong> 1.32 V; (3) threedifferent temperatures were used – -25 o C, 27 o CFigure 12: Temperature, Fault Resistance <strong>and</strong>Fault Duration Curves.SJ Monitor SignalsSJ Monitor is designed to have the same <strong>in</strong>put<strong>and</strong> outputs as SJ BIST: (1) currently active fault;
(2) at least one fault detected s<strong>in</strong>ce last reset; (3)enable <strong>in</strong>put; (4) reset <strong>in</strong>put; (5) count of thenumber of faults detected (1:255).SJ Monitor PowerTest simulations showed SJ Monitor has a powerrequirement of between 0.9 mW <strong>and</strong> 2.4 mW tomonitor 8 I/O p<strong>in</strong>s, depend<strong>in</strong>g on temperature <strong>and</strong>voltage. This low power requirement makes SJMonitor suitable for cont<strong>in</strong>uous monitor<strong>in</strong>g <strong>and</strong> forshort test applications.The primary objectives are the follow<strong>in</strong>g: (1)perform f<strong>in</strong>al sensitivity, resolution <strong>and</strong> clockfrequency measurements to update Figure 8; (2)collect, evaluate <strong>and</strong> publish statistical datarelated to test I/O port location, first failure <strong>and</strong>probability of failure distribution.Figure 14 is a footpr<strong>in</strong>t for a XILINX FG1156FPGA show<strong>in</strong>g the I/O p<strong>in</strong>s (shaded) we selectedfor test<strong>in</strong>g by SJ BIST. Sixty-four I/O p<strong>in</strong>s wereselected, so there are 32 groups of SJ BIST cores<strong>in</strong> our test program.Figure 13: Power Used vs Temperature <strong>and</strong>Supply Voltage (VCC).INTERMITTENCY MITIGATIONSJ BIST <strong>and</strong> SJ Monitor are very useful sensorsfor mitigat<strong>in</strong>g <strong>in</strong>termittencies when corner I/O p<strong>in</strong>sof a BGA package are monitored. Early <strong>detection</strong>of failure of an unused I/O p<strong>in</strong> allows theelectronic board to be replaced before subsequentfatigue damage causes an application I/O p<strong>in</strong> tofail, <strong>and</strong> therefore <strong>in</strong>termittent operationalanomalies are avoided. Reported <strong>detection</strong> ofone or more faults can be used to confirm that theelectronic board with that FPGA is a likelyc<strong>and</strong>idate for replacement to address reportedopearational anomalies.PRESENT ACTIVITIESExtensive experiments, <strong>in</strong>clud<strong>in</strong>g HALTs, havebeen planned <strong>and</strong> are presently be<strong>in</strong>g conducted.Figure 14: FG1156 Footpr<strong>in</strong>t Show<strong>in</strong>g SelectedSJ BIST I/O P<strong>in</strong>s: 32 Groups, 64 P<strong>in</strong>s.Figure 15 is a block diagram of the HALT testboard we designed. We load the SJ BIST testprogram <strong>in</strong>to a PROM, which then loads theprogram <strong>in</strong>to each FPGA when the board ispowered on. Each FPGA generates 640 bits ofdata (64 x (2 faults signals + 8 bits of count));each board generates 2560 bits of data, <strong>and</strong> wehave 4 boards <strong>in</strong> the HALT oven = 10,240 bits ofdata for each sample period. We wrote aLabVIEW® program to control the collection ofdata, <strong>and</strong> we wrote a MATLAB® program toprocess the data.Figure 16 shows a manufactured, populated <strong>and</strong>soldered HALT test board. There are threeconnectors: (1) XILINX programmer connection,(2) power <strong>in</strong>put <strong>and</strong> (3) experiment controlconnections.
Figure 17: 25 MHz CLK, 47 pF, 300 Ω Test.Figure 15: HALT Test Board Block Diagram.Figure 16: HALT Experiment Board with FourXILINX FG1156 FPGAs.Figure 17 shows a test result us<strong>in</strong>g a known faultof 300 Ω, a 25 MHz clock <strong>and</strong> a 47 pF capacitor.The result is actually better than that predicted byFigure 8: for a 300 Ω fault, a 20 MHz clock <strong>and</strong> a100 pF capacitor.Figure 18: SJ BIST Demonstration Box.Figure 19 is a picture of the XILINX SPARTAN®-3board <strong>in</strong>side of the SJ demonstration box. Weprogrammed the FGPA to monitor 8 I/O p<strong>in</strong>s.Error! Reference source not found. is a pictureof one of the SJ BIST demonstration boxes be<strong>in</strong>gtested for delivery to Raytheon Missile Systems.The front panel shows a fault count of 7, apreviously detected fault <strong>in</strong> an upper-right p<strong>in</strong>, <strong>and</strong>both an active (the fault <strong>in</strong>ject button isdepressed) <strong>and</strong> a previously detected fault <strong>in</strong> alower-right p<strong>in</strong>. The purpose of the box is to allowfor portable demonstrations, <strong>and</strong> to allow non-Ridgetop personnel to <strong>in</strong>dependently demonstrate<strong>and</strong> evaluate SJ BIST.Figure 19: SJ BIST Demonstration Box,XILINX Spartan 3 Board.
Figure 20 is a picture of the display control boardfor the SJ BIST demonstration board. The boardprovides the <strong>in</strong>terface <strong>and</strong> control between thebox front panel <strong>and</strong> the FPGA. Not shown is asmall board upon which the 7-segment LED ismounted. Future versions of the SJ BISTdemonstration box will use a pr<strong>in</strong>ted circuit board<strong>in</strong>stead of a bread board.longer reliable. SJ BIST can also be used <strong>in</strong>newly designed manufactur<strong>in</strong>g reliability tests to<strong>in</strong>vestigate failure modes related to the PWB-FPGA assembly.ACKNOWLEDGMENTThe work presented <strong>in</strong> this paper was funded bySmall Bus<strong>in</strong>ess Innovation Research contractawards from the Department of Defense, NavalAir, Jo<strong>in</strong>t Strike Fighter program: Contract No.N68335-06-C-0356 P00002. F<strong>in</strong>al patentapplications have been filed: one for SJ BISTtechnology <strong>and</strong> one for SJ Monitor technology.U.S. Patent 7,196,294, Mar. 27, 2007, has beenissued for a related technology.REFERENCESFigure 20: SJ BIST Demonstration Box,Display Board.SUMMARYIn this paper we provided updated <strong>in</strong>formation onSJ BIST, which was orig<strong>in</strong>ally presented <strong>in</strong> 2006,<strong>and</strong> we <strong>in</strong>troduced a new solder-jo<strong>in</strong>t fault sensor,SJ Monitor. A brief overview of the mechanics-offailurewas <strong>in</strong>cluded: the primary contributor tofatigue damage is thermo-mechanical stressesrelated to CTE mismatches, shock <strong>and</strong> vibration,<strong>and</strong> power on-off sequenc<strong>in</strong>g. Solder-jo<strong>in</strong>t fatiguedamage can result <strong>in</strong> fractures that cause<strong>in</strong>termittent <strong>in</strong>stances of high-resistance spikesthat are hard-to-diagnose. In reliability test<strong>in</strong>g,OPENS (faults) are often characterized by spikesof a 100Ω or more last<strong>in</strong>g for less than 100 ns to 1µs or longer.Prior to SJ BIST <strong>and</strong> SJ Monitor, there were noknown methods for detect<strong>in</strong>g high-resistancefaults <strong>in</strong> solder-jo<strong>in</strong>t networks belong<strong>in</strong>g to the I/Oports of operational, fully-programmed FPGAs.An <strong>in</strong>-situ SJ BIST or SJ Monitor to test or monitorselected I/O p<strong>in</strong>s is useful because stressmagnitudes are hard to derive, which leads to<strong>in</strong>accurate life expectancy predictions; <strong>and</strong> eventhough a particular damaged solder-jo<strong>in</strong>t portmight not result <strong>in</strong> immediate FPGA operationalfailure, the damage <strong>in</strong>dicates the FPGA is no[1]. J.P. Hofmeister, P. Lall <strong>and</strong> Russ Graves,“In-Situ, Real-Time Detector for Faults <strong>in</strong> SolderJo<strong>in</strong>ts Belong<strong>in</strong>g to Operational, FullyProgrammed FPGAs,” Proceed<strong>in</strong>gs, IEEEAUTOTESTCON 2006, Anaheim, CA, Sep. 18-21,2006, pp-237-243.[2]. Accelerated Reliability Task IPC-SM-785,SMT Force Group St<strong>and</strong>ard, Product ReliabilityCommittee of the IPC, Published by AnalysisTech., Inc., 2005, www.analysistech.com/eventtech-IPC-SM-785.[3]. P. Lall, M.N. Islam, N. S<strong>in</strong>gh, J.C. Suhl<strong>in</strong>g<strong>and</strong> R. Darveaux, “Model for BGA <strong>and</strong> CSPReliability <strong>in</strong> Automotive Underhood Applications,”IEEE Trans. Comp. <strong>and</strong> Pack. Tech.,Vol. 27, No.3, Sep. 2004, pp. 585-593.[4]. R. Gannamani, V. Valluri, Sidharth <strong>and</strong> M-LZhang, “Reliability evaluation of chip scale<strong>packages</strong>,” Advanced Micro Devices, Sunnyvale,CA, <strong>in</strong> Daisy Cha<strong>in</strong> Samples, Application Note,Spansion, July 2003, pp. 4-9.[5]. Sony Semiconductor Quality <strong>and</strong> ReliabilityH<strong>and</strong>book, Revised May 2001,http://www.sony.net/products/SC-HP/tec/catalog,Vol. 2, pp. 66-67, Vol. 4, pp. 120-129.[6]. Use Condition Based Reliability Evaluation:An Example Applied to Ball Grid Array (BGA)Packages, SEMATECH Technology Transfer#99083813A-XFR, International SEMATECH,1999, pg. 6.[7]. Comparison of Ball Grid Array (BGA)Component <strong>and</strong> Assembly Level QualificationTests <strong>and</strong> Failure Modes, SEMATECH
Technology Transfer #00053957A-XFR,International SEMATECH, May 31, 2000, pp. 1-4.[8]. R. Roergren, P-E. Teghall <strong>and</strong> P. Carlsson,“Reliability of BGA Packages <strong>in</strong> an AutomotiveEnvironment,” IVF-The Swedish Institute ofProduction Eng<strong>in</strong>eer<strong>in</strong>g Research, Argongatan30, SE-431 53 Moelndal, Sweden,http://www.ivf.se, accessed Dec. 25, 2005.[9]. D.E. Hodges Popp, A. Mawer <strong>and</strong> G.Presas, “Flip chip PBGA solder jo<strong>in</strong>t reliability:power cycl<strong>in</strong>g versus thermal cycl<strong>in</strong>g,” MotorolaSemiconductor Products Sector, Aust<strong>in</strong>, TX, Dec.19, 2005.[10]. The Reliability Report, XILINX,xgoogle.xil<strong>in</strong>x.com, Sep. 1, 2003, pp. 225-229.[11]. J-P. Clech, D.M. Noctor, J.C. Manock, G.W.Lynott <strong>and</strong> F.E. Bader, “Surface mount assemblyfailure statistics <strong>and</strong> failure-free times,” <strong>in</strong>Proceed<strong>in</strong>gs, 44 th ECTC, Wash<strong>in</strong>gton, D.C., May1-4, 1994, pp. 487-497.[12]. P. Lall, P. Choudhary <strong>and</strong> S. Gupte, “HealthMonitor<strong>in</strong>g for Damage Initiation & Progressiondur<strong>in</strong>g Mechanical Shock <strong>in</strong> ElectronicAssemblies,” Proceed<strong>in</strong>gs of the 56 th IEEEElectronic Components <strong>and</strong> TechnologyConference, San Diego, California, pp. 85-94,May 30-June 2, 2006.[13]. P. Lall, M. H<strong>and</strong>e, M.N. S<strong>in</strong>gh, J. Suhl<strong>in</strong>g<strong>and</strong> J. Lee, “Feature Extraction <strong>and</strong> Damage Datafor Prognostication of Leaded <strong>and</strong> LeadfreeElectronics,” Proceed<strong>in</strong>gs of the 56 th IEEEElectronic Components <strong>and</strong> TechnologyConference, San Diego, California, pp.718-727,May 30-June 2, 2006.[14]. P. Lall, N. Islam <strong>and</strong> J. Suhl<strong>in</strong>g, “Lead<strong>in</strong>gIndicators of Failure for Prognostication of Leaded<strong>and</strong> Lead-Free Electronics <strong>in</strong> HarshEnvironments,” Proceed<strong>in</strong>gs of the ASMEInterPACK Conference, San Francisco, CA, PaperIPACK2005-73426, pp. 1-9, July 17-22, 2005.[15]. P. Lall, M.N. Islam, K. Rahim <strong>and</strong> J.Suhl<strong>in</strong>g, “Prognostics <strong>and</strong> Health Management ofElectronic Packag<strong>in</strong>g,” Accepted for Publication <strong>in</strong>IEEE Transactions on Components <strong>and</strong>Packag<strong>in</strong>g Technologies, Paper Available <strong>in</strong>Digital Format on IEEE Explore, pp. 1-12, March2005.[16]. P. Lall, “Challenges <strong>in</strong> Accelerated LifeTest<strong>in</strong>g,” Inter Society Conf., ThermalPhenomena, 2004, pg. 727.[17]. XILINX F<strong>in</strong>e-Pitch BGA (FG1156/FGG1156)Package, PK039 (v1.2), June 25, 2004.[18]. R.R Tummala, EJ. Rymaszewski <strong>and</strong> A.G.Klopfenste<strong>in</strong>, Ed., Microelectronics Packag<strong>in</strong>gH<strong>and</strong>book, Semiconductor Packag<strong>in</strong>g Part II,Kluwer Academic Publishers, 2 nd Ed., 1999, pp. II-62 to II-185.IBM is a registered trade mark of IBM Corp.LabVIEW is a registered trade mark of NationalInstrumentsMATLAB is a registered trade mark of Mathworks, Inc.SPARTAN is a registered trade mark of Xil<strong>in</strong>x, Inc.TSMC is a registered trade mark of TaiwanSemiconductor Manufactur<strong>in</strong>g Corporation.XILINX is a registered trade mark of Xil<strong>in</strong>x, Inc.