intermittency detection and mitigation in ball grid array (bga) packages

INTERMITTENCY DETECTION AND MITIGATION IN BALL GRIDARRAY (BGA) PACKAGESJames P. HofmeisterSr. Principal EngineerRidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300hoffy@ridgetopgroup.comEdgar G. OrtizApplication EngineerRidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300edgar@ridgetopgroup.comPradeep LallThomas Walter ProfessorAuburn UniversityDept of MechanicalEngineering and CAVEAuburn, AL 36849(334) 844-3424lall@eng.auburn.eduMathieu G.P. AdamsDesign EngineerRidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300mathieu@ridgetopgroup.comDouglas GoodmanCEORidgetop Group, Inc.6595 N. Oracle Rd.Tucson, AZ 85750(520) 742-3300doug@ridgetopgroup.comTerry A. TracySr. Principal EngineerRaytheon MissileSystemsBldg. M02, MS T151151 Hermans RoadTucson, AZ 85706-1151(520) 794-3962TATracy@Raytheon.comAbstract – An update on a method (SJ BIST)to detect intermittencies in Ball Grid Array(BGA) packages is presented, and anothermethod (SJ Monitor) is introduced. SJBIST is primarily firmware embedded in theFPGA application; SJ Monitor is hardwareon an IC chip.Failure of monitored I/O pins on operational,fully-programmed FPGAs is reported by SJBIST and SJ Monitor to provide positiveindication of damage to one or more I/Osolder-joint networks of an FPGA on anelectronic digital board. The board can thenbe replaced before accumulated fatiguedamage results in intermittent or long-lastingoperational faults.INTRODUCTIONSJ BIST is an innovative, solder-joint built-inself-test that is in-situ within an FPGA to detecthigh-resistance damage to solder-joint networksof fully operational Field Programmable GateArrays (FPGAs) in ball-grid array (BGA) packagessuch as a XILINX® FG1152/FG1156 [1]. SJMonitor uses innovative circuit design on an ICchip in-situ on an FPGA board to provide amethod to monitor I/O pins 24x7 at much lesspower than SJ BIST. FPGAs are used in allmanner and kinds of control systems in bothdefense and commercial applications.SJ BIST is a two-port firmware core to be includedin operational, fully-programmed FPGAs: SJMonitor is a transistor-level circuit to be realizedas an Integrated Circuit (IC) on a chip. Bothcorrectly detect and report instances of resistanceat least as low as 100 Ω without false alarms. TheCenter for Advanced Vehicle Electronics (CAVE)at Auburn University is running Highly AcceleratedLife Test (HALT) experiments to verify correctoperation and to collect statistics; RaytheonMissile Systems, Tucson, Arizona, has purchasedSJ BIST demonstration boxes; and a largeautomobile manufacturer has contracted for SJBIST experiment and evaluation assistance.Mechanics-of-FailureSolder-joint damage under thermo-mechanicaland shock stresses is cumulative and ismanifested as plastic work leading to voids andcracks, as seen in Figure 1; cracks propagate tobecome fractures [2-5] which cause FPGAoperational faults. Thermo-mechanical stresses

are ground connection pins. The next nearest I/Oports at each corner are strong candidates fortesting by SJ BIST and monitoring by SJ Monitorbecause those I/O ports are likely to fail first.State of the ArtThe use of leading indicators of failure forprognostication of electronics has been previouslydemonstrated [12-15]. One important reason forusing in-situ solder-joint fault sensors is thatstress magnitudes are hard to derive, much lesskeep track of, which leads to inaccurate lifeexpectancy predictions [16]. Another reason isthat even though a particular damaged solder-jointport might not result in immediate FPGAoperational faults, detected faults by sensorsindicates the FPGA is likely to have, or will soonhave, other I/O ports that are damaged – theFPGA is no longer reliable. SJ BIST can be usedin newly designed manufacturing reliability tests toaddress a concern that failure modes caused bythe PWB-FPGA assembly are not being detectedduring component qualification [7].These sensor methods are the first known fordetecting faults in solder-joint networks of I/Oports of operational, fully-programmed FPGAs.Furthermore, FPGAs are not amenable to themeasurement techniques typically used inmanufacturing reliability tests such as HighlyAccelerated Life Tests (HALTs) [5]. This isbecause, for example, a 4-point probemeasurement requires devices to be powered-off;and because FPGA I/O ports are digital, ratherthan analog, circuits (see Figure 4).Modern BGA FPGAs have more than a thousandpins and very small pitch and ball sizes, forexample, Figure 5 shows the bottom of a XILINXFG1156 with a footprint of 35x35 mm 2 , and anarray of 34x34 solder balls.The dense array of fine-pitch and ultra fine-pitchBGA packages with very small pitch and solderball tends to make physical, optical and otherinspection techniques impractical for detecting theonset of damage.ReadLogicWriteLogicIO PORTFigure 4: FPGA Diagram, I/O Buffer [17,18].Figure 5: XILINX FG1156: Size is 35x35 mm 2 ;Pitch: 1.0 mm. Ball: 0.6 mm [17,18].SJ BISTSJ BIST requires the attachment of a smallcapacitor to an unused I/O port as near aspossible to a corner of the package. Figure 6 is ablock diagram of an FPGA containing SJ BISTwith a capacitor connected to two I/O pins.FPGAInput BufferOutput BufferDieSJ BISTSolder Bump/Bonding:Die to BaseSimplifiedESDSOLDER BALLDiePadCeramic BaseBoardSolder BallPCBLandPCBBoardFAULTCAPACITOR VOLTAGEFigure 6: SJ BIST Block Diagram

Referring to Figure 6, SJ BIST writes a logical ‘1’to charge the capacitor and then reads the voltageacross the charged capacitor. If the solder-jointnetwork of the I/O port of the FPGA isundamaged, the write causes the capacitor to befully charged and a logical ‘1’ is read by SJ BIST.When the solder-joint network is damaged, theeffective resistance of the SJ network increases,the charging time constant increases, the writefails to sufficiently charge the capacitor, and alogical ‘0’ instead of a logical ‘1’ is read: a faultoccurs, is detected by SJ BIST and is reported.capacitance of the I/O port was sufficient – noexternal capacitance needed to be connected,and SJ BIST correctly detected faults with noalarms.(A)Test ResultsSJ BIST was synthesized, programmed into testFPGAs and tested at various clock frequenciesranging from 10 KHz to 100 MHz and for varyingsolder-joint network conditions ranging from nofault to over 100 Ω of fault resistance: All faults of100 Ω or larger were detected, and there were nofalse alarms.(B)Solder Joint No Fault and Fault TestsReferring to Figure 7, two sets of voltages on a1.0 µF capacitor connected to a group of two I/Oports are shown. Figure 7A shows the capacitorvoltage when one of the two ports connected tothe capacitor has a 1 Ω resistor connected inseries with the solder joint: the resistance is nothigh enough cause a write fault to occur, and SJBIST correctly did not report a detected fault.Figure 7: SJ BIST: 1 MHz Capacitor Signal.Top is for a No Fault Condition; Bottom is for aFault Condition (100 Ω) ) − 0.5 µs x 2.0V Grid.Figure 7B shows the capacitor voltage when theresistance is increased to 100 Ω, a write faultoccurs. SJ BIST correctly reported the fault andincremented the fault count for that I/O pin.Clock Frequency, Capacitor Value andDetectable Fault ResistanceThere is a relationship between the frequency ofthe FPGA clock, the value of the connectedcapacitor to each group of two I/O pins, and thedetectable fault resistance. Figure 8 shows theresults of tests conducted in September of 2006:For a given clock frequency, there is a capacitorvalue that will cause SJ BIST to always detect afault resistance at least as low as 100 Ω.For clock frequencies of one-half or higher of themaximum clock frequency of the FPGA, theFigure 8: Clock Frequency, External CapacitorValue and Detectable Fault Resistance – Sep.2006.

SJ BIST Sensitivity and ResolutionGiven a correctly selected pair of CLK frequenciesand capacitor values, SJ BIST is guaranteed todetect all faults at least as low as 100 Ω(sensitivity) when the fault lasts at least two clockperiods (resolution). For faults of shorter duration,the fault is detectable when it occurs shortlybefore the write and when it lasts about one-halfof the clock period.SJ BIST SignalsSJ BIST needs to present at least one error signal(a fault indicator) either to an external FPGA I/Oport or to an internal fault management program.At least one control signal is required: an enable(disable) BIST.SJ Monitor is a passive detector capable ofdetecting a voltage perturbation in a solder-jointnetwork caused by a resistance spike at least aslow as 100 Ω. We have successfully designedand simulated SJ Monitor at 3.3 V for a TSMC®0.25-µm process, and at 1.2 V and 2.5 V for anIBM® 130-nm process node.We intend to realize, package, test andcharacterize SJ Monitor for a 1.2 V, 130-nmprocess. We have not made any decision as tothe number of SJ Monitor cells to put on each ICchip. Board wiring constraints might require us toonly put 4 cells on each IC chip; this might thenrequire the placing of two SJ Monitor chips on theboard.Error Signals and Fault CountsIn addition to recording fault counts, the SJ BISTcore has two error signals: (1) at least one faulthas been detected in the 2-port network beingtested and (2) at least one fault is currently active.A fault counter (1:255) is provided. For adeployed SJ BIST, we anticipate mostapplications would only use the two error signals.We also believe a deployed SJ BIST applicationwould most likely use at least four groups of cores– one group of two I/O pins near each corner ofan FPGA.Control SignalsIn addition to CLK, the SJ BIST core has two inputsignals: ENABLE and RESET. ENABLE is usedto turn SJ BIST detection on and off; RESET isused to reset both the fault signal latches and thefault counters. For a deployed SJ BIST, RESETmight not be used.SJ MONITORSJ Monitor is designed and is being developed asan Integrated Circuit (IC) chip, which must bemounted next to and connected to the FPGA onthe board. SJ Monitor is a low-power, continuousmonitoring sensor: at 1.2 V to 2.5 V, it uses lessthan 5.0 mW to monitor 8 I/O pins. SJ BIST has apower requirement of over 100 mW to test 8 I/Opins. A block diagram representation of SJMonitor is shown in Figure 9.Figure 9: SJ Monitor Block DiagramAlthough an active I/O port is shown in Figure 9,an active port is not a requirement: the onlyrequirement is the port must be at logical zerolevel.Simulation ResultsMeasurements and evaluations of various FPGAsfrom more than one manufacturer indicate that forI/O ports pulled low and sourced with externalcurrents of less than 0.5 mA, the noise on anoutput I/O port is much less than 2.5 mV. Thisallowed us to design SJ Monitor to source lessthan 200 µA to each monitored I/O pin of anFPGA. We have verified we can easily changethe design to handle a higher level of sourcecurrent to overcome a greater-than-expectednoise margin.A complementary version of SJ Monitor usingnegative 1.2 V power was designed andsimulated: It provides a monitoring capability forFPGAs that are powered off.

Noise Rejection and Fault DetectionWe simulated DC pull-down levels from 0 to over300 mV with noise perturbations of 2.0 to 3.0 mV,which is about 3 times larger than the maximumlevel of noise we measured.Referring to Figure 10, (A) shows an I/O pin with apull-down voltage level of 10 mV and (B) showsan I/O pin with a pull-down voltage level of 100mV. Superimposed on each of the pull-downvoltage levels are 3.0 mV noise pulses and 9.5mV fault perturbations. The fault perturbationsare caused by injecting a 100 Ω fault into thesolder-joint network.(A)and 100 o C; and (4) the complementary version ofSJ Monitor was simulated using negative powervoltages of -1.08V, -1.20 V and -1.32 V. For allvariations, SJ Monitor produced correct results: allfaults detected and no false alarms.Figure 11: SJ Monitor Fault Signal Responseto Figure 10 A and B.SJ Monitor Sensitivity and Resolution(B)The value of the minimum detectable faultresistance is primarily dependent on the durationof the fault and the operating temperature asshown in Figure 12. The results indicate that SJMonitor is able to detect a fault resistance at leastas low as 100 Ω when the fault duration is at leastas long as 20 ns.Figure 10: FPGA I/O Pin Voltages: (A) Pulldownis 10 mV and (B) Pull-down is 100 mV;Noise is 3.0 mV, Fault Perturbation is 19.5 mV.SJ Monitor is insensitive to a specific value of pulldownvoltage: Both of the input conditions seen inFigure 10 result in the output shown in Figure 11.SJ Monitor uses signal conditioning to ignore thepull-down voltage level, to suppress noise and toamplify the fault perturbation to produce a digitalfault signal.Simulations were performed using variations incircuit parameters: (1) 10 to 20 percent variationin transistor widths and lengths were used; (2)three different power supply voltage levels wereused – 1.08 V, 1.20 V and 1.32 V; (3) threedifferent temperatures were used – -25 o C, 27 o CFigure 12: Temperature, Fault Resistance andFault Duration Curves.SJ Monitor SignalsSJ Monitor is designed to have the same inputand outputs as SJ BIST: (1) currently active fault;

(2) at least one fault detected since last reset; (3)enable input; (4) reset input; (5) count of thenumber of faults detected (1:255).SJ Monitor PowerTest simulations showed SJ Monitor has a powerrequirement of between 0.9 mW and 2.4 mW tomonitor 8 I/O pins, depending on temperature andvoltage. This low power requirement makes SJMonitor suitable for continuous monitoring and forshort test applications.The primary objectives are the following: (1)perform final sensitivity, resolution and clockfrequency measurements to update Figure 8; (2)collect, evaluate and publish statistical datarelated to test I/O port location, first failure andprobability of failure distribution.Figure 14 is a footprint for a XILINX FG1156FPGA showing the I/O pins (shaded) we selectedfor testing by SJ BIST. Sixty-four I/O pins wereselected, so there are 32 groups of SJ BIST coresin our test program.Figure 13: Power Used vs Temperature andSupply Voltage (VCC).INTERMITTENCY MITIGATIONSJ BIST and SJ Monitor are very useful sensorsfor mitigating intermittencies when corner I/O pinsof a BGA package are monitored. Early detectionof failure of an unused I/O pin allows theelectronic board to be replaced before subsequentfatigue damage causes an application I/O pin tofail, and therefore intermittent operationalanomalies are avoided. Reported detection ofone or more faults can be used to confirm that theelectronic board with that FPGA is a likelycandidate for replacement to address reportedopearational anomalies.PRESENT ACTIVITIESExtensive experiments, including HALTs, havebeen planned and are presently being conducted.Figure 14: FG1156 Footprint Showing SelectedSJ BIST I/O Pins: 32 Groups, 64 Pins.Figure 15 is a block diagram of the HALT testboard we designed. We load the SJ BIST testprogram into a PROM, which then loads theprogram into each FPGA when the board ispowered on. Each FPGA generates 640 bits ofdata (64 x (2 faults signals + 8 bits of count));each board generates 2560 bits of data, and wehave 4 boards in the HALT oven = 10,240 bits ofdata for each sample period. We wrote aLabVIEW® program to control the collection ofdata, and we wrote a MATLAB® program toprocess the data.Figure 16 shows a manufactured, populated andsoldered HALT test board. There are threeconnectors: (1) XILINX programmer connection,(2) power input and (3) experiment controlconnections.

Figure 17: 25 MHz CLK, 47 pF, 300 Ω Test.Figure 15: HALT Test Board Block Diagram.Figure 16: HALT Experiment Board with FourXILINX FG1156 FPGAs.Figure 17 shows a test result using a known faultof 300 Ω, a 25 MHz clock and a 47 pF capacitor.The result is actually better than that predicted byFigure 8: for a 300 Ω fault, a 20 MHz clock and a100 pF capacitor.Figure 18: SJ BIST Demonstration Box.Figure 19 is a picture of the XILINX SPARTAN®-3board inside of the SJ demonstration box. Weprogrammed the FGPA to monitor 8 I/O pins.Error! Reference source not found. is a pictureof one of the SJ BIST demonstration boxes beingtested for delivery to Raytheon Missile Systems.The front panel shows a fault count of 7, apreviously detected fault in an upper-right pin, andboth an active (the fault inject button isdepressed) and a previously detected fault in alower-right pin. The purpose of the box is to allowfor portable demonstrations, and to allow non-Ridgetop personnel to independently demonstrateand evaluate SJ BIST.Figure 19: SJ BIST Demonstration Box,XILINX Spartan 3 Board.

Figure 20 is a picture of the display control boardfor the SJ BIST demonstration board. The boardprovides the interface and control between thebox front panel and the FPGA. Not shown is asmall board upon which the 7-segment LED ismounted. Future versions of the SJ BISTdemonstration box will use a printed circuit boardinstead of a bread board.longer reliable. SJ BIST can also be used innewly designed manufacturing reliability tests toinvestigate failure modes related to the PWB-FPGA assembly.ACKNOWLEDGMENTThe work presented in this paper was funded bySmall Business Innovation Research contractawards from the Department of Defense, NavalAir, Joint Strike Fighter program: Contract No.N68335-06-C-0356 P00002. Final patentapplications have been filed: one for SJ BISTtechnology and one for SJ Monitor technology.U.S. Patent 7,196,294, Mar. 27, 2007, has beenissued for a related technology.REFERENCESFigure 20: SJ BIST Demonstration Box,Display Board.SUMMARYIn this paper we provided updated information onSJ BIST, which was originally presented in 2006,and we introduced a new solder-joint fault sensor,SJ Monitor. A brief overview of the mechanics-offailurewas included: the primary contributor tofatigue damage is thermo-mechanical stressesrelated to CTE mismatches, shock and vibration,and power on-off sequencing. Solder-joint fatiguedamage can result in fractures that causeintermittent instances of high-resistance spikesthat are hard-to-diagnose. In reliability testing,OPENS (faults) are often characterized by spikesof a 100Ω or more lasting for less than 100 ns to 1µs or longer.Prior to SJ BIST and SJ Monitor, there were noknown methods for detecting high-resistancefaults in solder-joint networks belonging to the I/Oports of operational, fully-programmed FPGAs.An in-situ SJ BIST or SJ Monitor to test or monitorselected I/O pins is useful because stressmagnitudes are hard to derive, which leads toinaccurate life expectancy predictions; and eventhough a particular damaged solder-joint portmight not result in immediate FPGA operationalfailure, the damage indicates the FPGA is no[1]. J.P. Hofmeister, P. Lall and Russ Graves,“In-Situ, Real-Time Detector for Faults in SolderJoints Belonging to Operational, FullyProgrammed FPGAs,” Proceedings, IEEEAUTOTESTCON 2006, Anaheim, CA, Sep. 18-21,2006, pp-237-243.[2]. Accelerated Reliability Task IPC-SM-785,SMT Force Group Standard, Product ReliabilityCommittee of the IPC, Published by AnalysisTech., Inc., 2005, www.analysistech.com/eventtech-IPC-SM-785.[3]. P. Lall, M.N. Islam, N. Singh, J.C. Suhlingand R. Darveaux, “Model for BGA and CSPReliability in Automotive Underhood Applications,”IEEE Trans. Comp. and Pack. Tech.,Vol. 27, No.3, Sep. 2004, pp. 585-593.[4]. R. Gannamani, V. Valluri, Sidharth and M-LZhang, “Reliability evaluation of chip scalepackages,” Advanced Micro Devices, Sunnyvale,CA, in Daisy Chain Samples, Application Note,Spansion, July 2003, pp. 4-9.[5]. Sony Semiconductor Quality and ReliabilityHandbook, Revised May 2001,http://www.sony.net/products/SC-HP/tec/catalog,Vol. 2, pp. 66-67, Vol. 4, pp. 120-129.[6]. Use Condition Based Reliability Evaluation:An Example Applied to Ball Grid Array (BGA)Packages, SEMATECH Technology Transfer#99083813A-XFR, International SEMATECH,1999, pg. 6.[7]. Comparison of Ball Grid Array (BGA)Component and Assembly Level QualificationTests and Failure Modes, SEMATECH

Technology Transfer #00053957A-XFR,International SEMATECH, May 31, 2000, pp. 1-4.[8]. R. Roergren, P-E. Teghall and P. Carlsson,“Reliability of BGA Packages in an AutomotiveEnvironment,” IVF-The Swedish Institute ofProduction Engineering Research, Argongatan30, SE-431 53 Moelndal, Sweden,http://www.ivf.se, accessed Dec. 25, 2005.[9]. D.E. Hodges Popp, A. Mawer and G.Presas, “Flip chip PBGA solder joint reliability:power cycling versus thermal cycling,” MotorolaSemiconductor Products Sector, Austin, TX, Dec.19, 2005.[10]. The Reliability Report, XILINX,xgoogle.xilinx.com, Sep. 1, 2003, pp. 225-229.[11]. J-P. Clech, D.M. Noctor, J.C. Manock, G.W.Lynott and F.E. Bader, “Surface mount assemblyfailure statistics and failure-free times,” inProceedings, 44 th ECTC, Washington, D.C., May1-4, 1994, pp. 487-497.[12]. P. Lall, P. Choudhary and S. Gupte, “HealthMonitoring for Damage Initiation & Progressionduring Mechanical Shock in ElectronicAssemblies,” Proceedings of the 56 th IEEEElectronic Components and TechnologyConference, San Diego, California, pp. 85-94,May 30-June 2, 2006.[13]. P. Lall, M. Hande, M.N. Singh, J. Suhlingand J. Lee, “Feature Extraction and Damage Datafor Prognostication of Leaded and LeadfreeElectronics,” Proceedings of the 56 th IEEEElectronic Components and TechnologyConference, San Diego, California, pp.718-727,May 30-June 2, 2006.[14]. P. Lall, N. Islam and J. Suhling, “LeadingIndicators of Failure for Prognostication of Leadedand Lead-Free Electronics in HarshEnvironments,” Proceedings of the ASMEInterPACK Conference, San Francisco, CA, PaperIPACK2005-73426, pp. 1-9, July 17-22, 2005.[15]. P. Lall, M.N. Islam, K. Rahim and J.Suhling, “Prognostics and Health Management ofElectronic Packaging,” Accepted for Publication inIEEE Transactions on Components andPackaging Technologies, Paper Available inDigital Format on IEEE Explore, pp. 1-12, March2005.[16]. P. Lall, “Challenges in Accelerated LifeTesting,” Inter Society Conf., ThermalPhenomena, 2004, pg. 727.[17]. XILINX Fine-Pitch BGA (FG1156/FGG1156)Package, PK039 (v1.2), June 25, 2004.[18]. R.R Tummala, EJ. Rymaszewski and A.G.Klopfenstein, Ed., Microelectronics PackagingHandbook, Semiconductor Packaging Part II,Kluwer Academic Publishers, 2 nd Ed., 1999, pp. II-62 to II-185.IBM is a registered trade mark of IBM Corp.LabVIEW is a registered trade mark of NationalInstrumentsMATLAB is a registered trade mark of Mathworks, Inc.SPARTAN is a registered trade mark of Xilinx, Inc.TSMC is a registered trade mark of TaiwanSemiconductor Manufacturing Corporation.XILINX is a registered trade mark of Xilinx, Inc.