section 7 - Index of
section 7 - Index of section 7 - Index of
-DATA ARITHMETIC LOGIC UNITINPUT REGISTERS47 X 0 47 Y 0l3XlIXO VlVOI I I Io 23 0 23 o 23 0,ACCUMULATOR REGISTERS55 A 0I A2 IAlIAOI23 87 o 23 023 055 B 0I,I 62 I61I80I23 87 o 23 023 0ADDRESS GENERATION UNIT23 1615 0 23 1615 0 23 1615 0********R7R6R5R4R3R2R1RO--------********N7N6N5N4N3N2N1NO---------********M7M6M5M4M3M2M1MOUPPER FILE----- ---------.--_.LOWER FILEPOINTERREGISTERSOFFSETREGISTERSMODIFIERREGISTERSIPROGRAM CONTROL UNITLOOP ADDRESSREGISTER (LA)23 1615LOOP COUNTER (LC)023 1615 8723 8 7 6. 5 4 3 2 1 0PROGRAMCOUNTER (PC)/I * I MR I CCRSTATUSREGISTER (SR)I I *ISOI*I MC I VO IOEIM6IMAIOPERATING MODE REGISTER (OMR)31SSH1615SSL123 6 5--1 * ISTACK POINTER (SP)SYSTEM STACK* READ AS ZERO, SHOULD BE WRITTENWITH ZERO FOR FUTURE COMPATIBILITY, READ AS SIGN EXTENSION BITS,5 WRITTEN AS DON'T CARE1Figure 5-9 DSP56K Central Processing Module Programming Model
SECTION 6INSTRUCTION SET INTRODUCTION
- Page 47 and 48: _--- N BITS ---_TWOS COMPLEMENT INT
- Page 49 and 50: CASE I: IF AO < $800000 (1/2), THEN
- Page 51 and 52: one instruction cycle. The ANDI ins
- Page 53: 3.5 DATA ALU PROGRAMMING MODELThe D
- Page 57 and 58: 4.1 ADDRESS GENERATION UNIT AND ADD
- Page 59 and 60: !---LOWADDRESS ALU -----I~.j.I.....
- Page 61 and 62: •••••••• _ ........
- Page 63 and 64: 4.4.1 Address Register Indirect Mod
- Page 65 and 66: EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
- Page 67 and 68: EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
- Page 69 and 70: EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
- Page 71 and 72: Table 4-2 Address Modifier SummaryM
- Page 73 and 74: ADDRESS -f-_POINTERUPPER BOUNDARYiM
- Page 75 and 76: EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
- Page 77 and 78: oundary gives a 16-bit binary numbe
- Page 79 and 80: 4.4.2.4 Address-Modifier-Type Encod
- Page 81: SECTION 5PROGRAM CONTROL UNIT-
- Page 84 and 85: X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
- Page 86 and 87: interruptible since they are fetche
- Page 88 and 89: PROGRAM CONTROL UNIT-23 1615 023 16
- Page 90 and 91: The GGR is a special purpose contro
- Page 92 and 93: If S 1 =0 and SO=O (no scaling)then
- Page 94 and 95: -23 876543210I * 1* JSO I * I Mel y
- Page 96 and 97: 5.4.5.1 Stack Pointer (Bits 0-3)The
- Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
- Page 103 and 104: shown in Figure 6-2. Most instructi
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 130 and 131: Each instruction requires a minimum
- Page 132 and 133: second instruction of the downloade
- Page 134 and 135: The DO instruction is another instr
- Page 136 and 137: SP and SSH/SSL register manipulatio
- Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
- Page 144 and 145: interrupts makes it very useful for
- Page 146 and 147: MAINPROGRAMFETCHESLONG INTERRUPTSER
SECTION 6INSTRUCTION SET INTRODUCTION
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