section 7 - Index of
section 7 - Index of section 7 - Index of
-23 876543210I * 1* JSO I * I Mel yoJ OE1MBIMAII I IFigure 5-6 OMR FormatOPERATING MODE A, BDATA ROM ENABLEINTERNAL Y MEMORY DISABLEOPERATING MODE CRESERVEDSTOP DELAYRESERVEDRESERVED5.4.3 Operating Mode RegisterThe OMR is a 24-bit register (only six bits are d~fined) that sets the current operatingmode of the processor. Each chip in the DSP56K family of processors has its own set ofoperating modes which determine the memory maps for program and data memories, andthe startup procedure that occurs when the chip leaves the reset state. The OMR bits areonly affected by processor reset and by the ANDI, ORI, and MOVEC instructions, whichdirectly reference the OMR.The OMR format with all of its defined bits is shown in Figure 5-6. For product-specificOMR bit definitions, see the individual chip's user manual for details on its respective operatingmodes.5.4.4 System StackThe SS is a separate 15X32-bit internal memory divided into two banks, the SSH and theSSL, each 16 bits wide. The SSH stores the PC contents, and the SSL stores the SR contentsfor subroutine calls, long interrupts, and program looping. The SS will alsC? store theLA and LC registers. The SS is in stack memory space; its address is always inherent andimplied by the current instruction.The contents of the PC and SR are pushed on the top location of the SS when a subroutinecall or long interrupt occurs. When a return from subroutine (RTS) occurs, thecontents of the top location in the SS are pulled and put in the PC; the SR is not affected.When an RTI occurs, the conte~ts of the top location in the SS are pulled to both the PCand SR.The SS is also used to implement no-overhead nested hardware DO loops. When the DOinstruction is executed, the LA:LC are pushed on the SS, then the PC:SR are pushed on
the SS. Since each SS location can be addressed as separate 16-bit registers (SSH andSSL), software stacks can be created for unlimited nesting.The SS can accommodate up to 15 long interrupts, seven DO loops, 15 JSRs, or combinationsthereof. When the SS limit is exceeded, a nonmaskable stack error interruptoccurs, and the PC is pushed to SS location zero, which is not implemented in hardware.The PC will be lost, and there will be no SP from the stack interrupt routine to the programthat was executing when the error occurred.5 4 3 2 oSTACK POINTERSTACK ERROR FLAGUNDERFLOW FLAGFigure 5-7 Stack Pointer Register Format5.4.5 Stack Pointer RegisterThe 6-bit SP register indicates the location of the top of the SS and the status of the SS(underflow, empty, full, and overflow). The SP register is referenced implicitly by some instructions(DO, REP, JSR, RTI, etc.) or directly by the MOVEC instruction. The SPregister format is shown in Figure 5-7. The SP register works as a 6-bit counter that addresses(selects) a 15-location stack with its four LSBs. The possible SP values areshown in Figure 5-8 and described in the following paragraphs.UF SE P3 P2 P1 POSTACK UNDERFLOW CONDITION AFTER DOUBLE PULL1 STACK UNDERFLOW CONDITION0 0 0 STACK EMPTY (RESET); PULL CAUSES UNDERFLOW0 0 0 STACK LOCATION 10 0 STACK LOCATION 140 0 STACK LOCATION 15; PUSH CAUSES OVERFLOW0 0 0 0 STACK OVERFLOW CONDITION0 0 0 0 STACK OVERFLOW CONDITION AFTER DOUBLE PUSHFigure 5-8 SP Register Values
- Page 43 and 44: 3.2.4 Accumulator ShifterThe accumu
- Page 45 and 46: Table 3-1 Limited Data ValuesDestin
- Page 47 and 48: _--- N BITS ---_TWOS COMPLEMENT INT
- Page 49 and 50: CASE I: IF AO < $800000 (1/2), THEN
- Page 51 and 52: one instruction cycle. The ANDI ins
- Page 53: 3.5 DATA ALU PROGRAMMING MODELThe D
- Page 57 and 58: 4.1 ADDRESS GENERATION UNIT AND ADD
- Page 59 and 60: !---LOWADDRESS ALU -----I~.j.I.....
- Page 61 and 62: •••••••• _ ........
- Page 63 and 64: 4.4.1 Address Register Indirect Mod
- Page 65 and 66: EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
- Page 67 and 68: EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
- Page 69 and 70: EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
- Page 71 and 72: Table 4-2 Address Modifier SummaryM
- Page 73 and 74: ADDRESS -f-_POINTERUPPER BOUNDARYiM
- Page 75 and 76: EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
- Page 77 and 78: oundary gives a 16-bit binary numbe
- Page 79 and 80: 4.4.2.4 Address-Modifier-Type Encod
- Page 81: SECTION 5PROGRAM CONTROL UNIT-
- Page 84 and 85: X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
- Page 86 and 87: interruptible since they are fetche
- Page 88 and 89: PROGRAM CONTROL UNIT-23 1615 023 16
- Page 90 and 91: The GGR is a special purpose contro
- Page 92 and 93: If S 1 =0 and SO=O (no scaling)then
- Page 96 and 97: 5.4.5.1 Stack Pointer (Bits 0-3)The
- Page 98 and 99: -DATA ARITHMETIC LOGIC UNITINPUT RE
- Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
- Page 103 and 104: shown in Figure 6-2. Most instructi
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
- Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
- Page 127: SECTION 7PROCESSING STATES-
- Page 130 and 131: Each instruction requires a minimum
- Page 132 and 133: second instruction of the downloade
- Page 134 and 135: The DO instruction is another instr
- Page 136 and 137: SP and SSH/SSL register manipulatio
- Page 138 and 139: 7.3.1 Interrupt TypesThe DSP56K rel
- Page 140 and 141: Table 7-2 Status Register Interrupt
- Page 142 and 143: 7.3.3 Interrupt SourcesInterrupts c
the SS. Since each SS location can be addressed as separate 16-bit registers (SSH andSSL), s<strong>of</strong>tware stacks can be created for unlimited nesting.The SS can accommodate up to 15 long interrupts, seven DO loops, 15 JSRs, or combinationsthere<strong>of</strong>. When the SS limit is exceeded, a nonmaskable stack error interruptoccurs, and the PC is pushed to SS location zero, which is not implemented in hardware.The PC will be lost, and there will be no SP from the stack interrupt routine to the programthat was executing when the error occurred.5 4 3 2 oSTACK POINTERSTACK ERROR FLAGUNDERFLOW FLAGFigure 5-7 Stack Pointer Register Format5.4.5 Stack Pointer RegisterThe 6-bit SP register indicates the location <strong>of</strong> the top <strong>of</strong> the SS and the status <strong>of</strong> the SS(underflow, empty, full, and overflow). The SP register is referenced implicitly by some instructions(DO, REP, JSR, RTI, etc.) or directly by the MOVEC instruction. The SPregister format is shown in Figure 5-7. The SP register works as a 6-bit counter that addresses(selects) a 15-location stack with its four LSBs. The possible SP values areshown in Figure 5-8 and described in the following paragraphs.UF SE P3 P2 P1 POSTACK UNDERFLOW CONDITION AFTER DOUBLE PULL1 STACK UNDERFLOW CONDITION0 0 0 STACK EMPTY (RESET); PULL CAUSES UNDERFLOW0 0 0 STACK LOCATION 10 0 STACK LOCATION 140 0 STACK LOCATION 15; PUSH CAUSES OVERFLOW0 0 0 0 STACK OVERFLOW CONDITION0 0 0 0 STACK OVERFLOW CONDITION AFTER DOUBLE PUSHFigure 5-8 SP Register Values
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