section 7 - Index of
section 7 - Index of section 7 - Index of
Table of Contents (Continued)ParagraphPageNumber Title Number3.5 DATA ALU PROGRAMMING MODEL ............................. 3-193.6 DATA ALU SUMMARy ......................................... 3-19SECTION 4ADDRESS GENERATION UNIT4.1 ADDRESS GENERATION UNIT AND ADDRESSING MODES .......... .4-34.2 AGU ARCHITECTURE .......................................... 4-34.3 PROGRAMMING MODEL ...................................... .4-64.4 ADDRESSING ................................................ 4-8SECTION 5PROGRAM CONTROL UNIT5.1 PROGRAM CONTROL UNIT ..................................... 5-35.2 OVERVIEW ................................................... 5-35.3 PROGRAM CONTROL UNIT (PCU) ARCHITECTURE ................. 5-55.4 PROGRAMMING MODEL ....................................... 5-8SECTION 6INSTRUCTION SET INTRODUCTION6.1 INSTRUCTION SET INTRODUCTION .............................. 6-36.2 SYNTAX ..................................................... 6-36.3 INSTRUCTION FORMATS ....................................... 6-36.4 INSTRUCTION GROUPS -....................................... 6-20SECTION 7PROCESSING STATES7.1 PROCESSING STATES ......................................... 7-37.2 NORMAL PROCESSING STATE .................................. 7-37.3' EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) ...... 7-10
Table of Contents (Continued)ParagraphPageNumber Title Number7.4 RESET PROCESSING STATE ................................... 7-337.5 WAIT PROCESSING STATE .................................... 7-367.6 STOP PROCESSING STATE .................................... 7-37SECTION 8PORTA8.1 PORT A OVERVIEW ........................................... 8-38.2 PORT A INTERFACE ........................................... 8-3SECTION 9PLL CLOCK OSCILLATOR9.1 PLL CLOCK OSCILLATOR INTRODUCTION ........................ 9-39.2 PLL COMPONENTS ............................................ 9-39.3 PLL PINS .................................................... 9-99.4 PLL OPERATION CONSIDERATIONS ............................ 9-11SECTION 10ON-CHIP EMULATION (OnCE)10.1 ON-CHIP EMULATION INTRODUCTION .......................... 10-310.2 ON-CHIP EMULATION (OnCE) PINS ............................. 10-310.3 OnCE CONTROLLER AND SERIAL INTERFACE .................... 10-610.4 OnCE MEMORY BREAKPOINT LOGIC ........................... 10-1110.5 OnCE TRACE LOGIC ......................................... 10-13 '10.6 METHODS OF ENTERING THE DEBUG MODE .................... 10-1410.7 PIPELINE INFORMATION AND GLOBAL DATA BUS REGiSTER ...... 10-1610.8 PROGRAM ADDRESS BUS HISTORY BUFFER ................... 10-1810.9 SERIAL PROTOCOL DESCRIPTION ............................. 10-1910.10 DSP56K TARGET SITE DEBUG SYSTEM REQUIREMENTS ......... 10-1910.11 USING THE OnCE ........................................... 10-20
- Page 3 and 4: DSP56K FAMILY INTRODUCTIONDSP56K CE
- Page 5: Motorola reserves the right to make
- Page 10 and 11: ParagraphNumberTable of Contents (C
- Page 13 and 14: FigureNumberList of Figures (Contin
- Page 15: List of Tables (Continued)TablePage
- Page 19 and 20: 1.1 INTRODUCTIONThe DSP56K family i
- Page 21 and 22: Fewer componentsStable, determinist
- Page 23 and 24: Digital FilteringFinite Impulse Res
- Page 25 and 26: architecture matches the shape of t
- Page 27 and 28: • DSP56001 Compatibility - All me
- Page 29: SECTION 2DSP56K CENTRAL ARCHITECTUR
- Page 32 and 33: --I«a:w:ca.ffi~a. a.24-Bit 56KModu
- Page 34 and 35: -rectly addressable registers: the
- Page 37 and 38: 3.1 DATA ARITHMETIC LOGIC UNITThis
- Page 39 and 40: 3.2.1 Data ALU Input Registers (X1,
- Page 41 and 42: """""" 24 BITS;:~:>~~::~~~:~:~:~:::
- Page 43 and 44: 3.2.4 Accumulator ShifterThe accumu
- Page 45 and 46: Table 3-1 Limited Data ValuesDestin
- Page 47 and 48: _--- N BITS ---_TWOS COMPLEMENT INT
- Page 49 and 50: CASE I: IF AO < $800000 (1/2), THEN
- Page 51 and 52: one instruction cycle. The ANDI ins
- Page 53: 3.5 DATA ALU PROGRAMMING MODELThe D
- Page 57 and 58: 4.1 ADDRESS GENERATION UNIT AND ADD
Table <strong>of</strong> Contents (Continued)ParagraphPageNumber Title Number7.4 RESET PROCESSING STATE ................................... 7-337.5 WAIT PROCESSING STATE .................................... 7-367.6 STOP PROCESSING STATE .................................... 7-37SECTION 8PORTA8.1 PORT A OVERVIEW ........................................... 8-38.2 PORT A INTERFACE ........................................... 8-3SECTION 9PLL CLOCK OSCILLATOR9.1 PLL CLOCK OSCILLATOR INTRODUCTION ........................ 9-39.2 PLL COMPONENTS ............................................ 9-39.3 PLL PINS .................................................... 9-99.4 PLL OPERATION CONSIDERATIONS ............................ 9-11SECTION 10ON-CHIP EMULATION (OnCE)10.1 ON-CHIP EMULATION INTRODUCTION .......................... 10-310.2 ON-CHIP EMULATION (OnCE) PINS ............................. 10-310.3 OnCE CONTROLLER AND SERIAL INTERFACE .................... 10-610.4 OnCE MEMORY BREAKPOINT LOGIC ........................... 10-1110.5 OnCE TRACE LOGIC ......................................... 10-13 '10.6 METHODS OF ENTERING THE DEBUG MODE .................... 10-1410.7 PIPELINE INFORMATION AND GLOBAL DATA BUS REGiSTER ...... 10-1610.8 PROGRAM ADDRESS BUS HISTORY BUFFER ................... 10-1810.9 SERIAL PROTOCOL DESCRIPTION ............................. 10-1910.10 DSP56K TARGET SITE DEBUG SYSTEM REQUIREMENTS ......... 10-1910.11 USING THE OnCE ........................................... 10-20
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