section 7 - Index of

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interruptible since they are fetched only once. A single-instruction DO loop can be usedin place of a REP instruction if interrupts must be allowed.5.3.3 Program Interrupt ControllerThe PIC receives all interrupt requests, arbitrates among them, and generates the interruptvector address.-Interrupts have a flexible priority structure with levels that can range from zero to three.Levels 0 (lowest level), 1, and 2 are maskable. Level 3 is the highest interrupt priority level(IPL) and is not maskable. Two interrupt mask bits in the SR reflect the current IPL andindicate the level needed for an interrupt source to interrupt the processor. Interruptscause the DSP to enter the exception processing state which is discussed fully in SECTION 7 - PROCESSING STATES.The four external interrupt sources include three external interrupt request inputs (IROA,IROS, and NMI) and the RESET pin. IROA and IROS can be either level sensitive or negativeedge triggered. The nonmaskable interrupt (NMI) is edge sensitive and is a level 3interrupt. MODNIROA, MODS/IROS, and MODC/NMI pins are sampled when RESET isdeasserted. The sampled values are stored in the operating mode register (OMR) bitsMA, MB, and MC, respectively (see Section 5.4.3 ,for information on the OMR). Only thefourth external interrupt, RESET, and Illegal Instruction have higher priority than NMI.The PIC also arbitrates between the different I/O peripherals. The currently selected peripheralsupplies the correct vector address to the PIC.5.3.4 Instruction Pipeline FormatThe program control unit uses a three-level pipe lined architecture in which concurrent instructionfetch, decode, and execution occur. This pipelined operation remains essentiallyhidden from the user and makes programming straightforward. The pipeline is illustratedin Figure 5-3, which shows the operations of each of the execution units and all initial conditionsnecessary to follow the execution of the instruction sequence shown in the figure.The pipeline is described in more detail in Section 7.2.1 Instruction Pipeline.The first instruction, 11, should be interpreted as follows: multiply the contents of XO by thecontents of VO, add the product to the contents already in accumulator A, round the resultto the "nearest even," store the result back in accumulator A, move the contents in X datamemory (pointed to by RO) into XO and postincrement RO, and move the contents in Vdata memory (pointed to by R4) into V1 and postincrement R4. The second instruction,12, should be interpreted as follows: clear accumulator A, move the contents in XO into thelocation in X data memory pointed to by RO and postincrement RO. Sefore the clear oper-
EXAMPLE pROGRAM SEGMENTInstruction 1Instruction 2Instruction 3MACRCLRMACXO,Y1,AAXO,Y1,AX:(RO)+,XOXO,X:(RO)+X:(RO)+,XOY:(R4)+,Y1A,Y:(R4)Y:(R4)+,Y1SEQUENCE OF OPERATIONSSERIAL EXECUTION OF INSTRUCTIONSCI)zo§~a:~~u.oCJzfgwga:D....JW::I~~Instruction/Data FetchInstruction DecodeInstruction ExecutionEXECUTION OF EXAMPLE PROGRAM-1~~~1~~~Tb~NcfEEJ"g6'e -INSTRUCTION EXECUTION=:Instruction Cycle 1 Instruction Cycle 2 Instruction Cycle 3 Instruction Cycle 4 Instruction Cycle 511 __ 12 __13 __--i1__I~--15====:12 __--i~__11 --12 ~~4 13PARALLELOPERATIONSINITIALCONDITIONSADDRESSUPDATE(AGU)RO=$0005R4=$0008RO=5+1R4=8+1RO=6+1R4=9-1RO=7+1R4=8+1INSTRUCTIONEXECUTIONA:A2=$OOA1=$000066AO:$OOOOOOA:A2=$00A1=$0000A2AO=$OOOOOOA:A2=$00A1=$000000AO=$OOOOOOA:A2=$00A1=$000000AO=$000050(DATAALU)XO=$400000Y1=$000077XO=$000005Y1=$000008XO=$000005Y1=$000008XO=$000007Y1=$000008X MEMORY DATAAT ADDRESS$0005 $000005$0006 $000006$0007 $000007~000005000006$000007$000005$000005$000007$000005$000005$000007YMEMORY DATAAT ADDRESS$0008 $000008$0009 $000009$000008$000009$000008$0000A2$000008$0000A2Figure 5-3 Three-Stage Pipeline
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
Page 37 and 38: 3.1 DATA ARITHMETIC LOGIC UNITThis
Page 39 and 40: 3.2.1 Data ALU Input Registers (X1,
Page 41 and 42: """""" 24 BITS;:~:>~~::~~~:~:~:~:::
Page 43 and 44: 3.2.4 Accumulator ShifterThe accumu
Page 45 and 46: Table 3-1 Limited Data ValuesDestin
Page 47 and 48: _--- N BITS ---_TWOS COMPLEMENT INT
Page 49 and 50: CASE I: IF AO < $800000 (1/2), THEN
Page 51 and 52: one instruction cycle. The ANDI ins
Page 53: 3.5 DATA ALU PROGRAMMING MODELThe D
Page 57 and 58: 4.1 ADDRESS GENERATION UNIT AND ADD
Page 59 and 60: !---LOWADDRESS ALU -----I~.j.I.....
Page 61 and 62: •••••••• _ ........
Page 63 and 64: 4.4.1 Address Register Indirect Mod
Page 65 and 66: EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
Page 67 and 68: EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
Page 69 and 70: EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
Page 71 and 72: Table 4-2 Address Modifier SummaryM
Page 73 and 74: ADDRESS -f-_POINTERUPPER BOUNDARYiM
Page 75 and 76: EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
Page 77 and 78: oundary gives a 16-bit binary numbe
Page 79 and 80: 4.4.2.4 Address-Modifier-Type Encod
Page 81: SECTION 5PROGRAM CONTROL UNIT-
Page 84 and 85: X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
Page 88 and 89: PROGRAM CONTROL UNIT-23 1615 023 16
Page 90 and 91: The GGR is a special purpose contro
Page 92 and 93: If S 1 =0 and SO=O (no scaling)then
Page 94 and 95: -23 876543210I * 1* JSO I * I Mel y
Page 96 and 97: 5.4.5.1 Stack Pointer (Bits 0-3)The
Page 98 and 99: -DATA ARITHMETIC LOGIC UNITINPUT RE
Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
Page 103 and 104: shown in Figure 6-2. Most instructi
Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
Page 107 and 108: The MR and CCR may be accessed indi
Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
Page 111 and 112: Some address register indirect mode
Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
Page 119 and 120: Table 6-1 Addressing Modes SummaryA
Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
Page 125 and 126: OPCODE/OPERANDSPARALLEL MOVE EXAMPL
Page 127: SECTION 7PROCESSING STATES-
Page 130 and 131: Each instruction requires a minimum
Page 132 and 133: second instruction of the downloade
Page 134 and 135: The DO instruction is another instr
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SP and SSH/SSL register manipulatio
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7.3.1 Interrupt TypesThe DSP56K rel
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Table 7-2 Status Register Interrupt
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7.3.3 Interrupt SourcesInterrupts c
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interrupts makes it very useful for
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MAINPROGRAMFETCHESLONG INTERRUPTSER
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7.3.3.3 Other Interrupt SourcesOthe
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7.3.4 Interrupt ArbitrationInterrup
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7.3.7 Interrupt Instruction Executi
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MAINPROGRAMMEMORYINTERRUPT SYNCHRON
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MAINPROGRAMFETCHESINTERRUPTSYNCHRON
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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7.5 WAIT PROCESSING STATEThe WAIT i
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The stop processing state halts all
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the first instruction fetch). If th
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RESET -----------------------------
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16 - BIT INTERNALADDRESS BUSESX ADD
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8.2.2.1 Address (AO-A15)These three
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SECTION 9PLL CLOCK OSCILLATOR-
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X MEMORYRAM/ROMEXPANSION24-Bit56KMo
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23 22 21 20 19 18 17 16 15 14 13 12
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cleared. To enable rapid recovery w
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-CLVCCVCC for the CKOUT output. The
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4. For all input frequencies which
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While the PLL is regaining lock, th
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10.1 ON-CHIP EMULATION INTRODUCTION
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10.2.2 Debug Serial Clock/Chip Stat
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76543210I R/W I GO I EX I RS41 RS31
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shifted in (so a new command is ava
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10.3.4.4 Software Debug Occurrence
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10.4.4 Memory High Address Comparat
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10.6.1 External Debug Request Durin
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PABCIRCULARBUFFERPOINTERDSCKDSOFigu
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are serially available to the exter
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k. ACKI. ClKm. Send command READ FI
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19. ACK20. Send command READ GDB RE
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10.11.6.1 Case 1: Return To The Pre
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SECTION 11ADDITIONAL SUPPORTDr. BuB
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The following is a partial list of
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• In-line assembler language code
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I Document 10 I Version Synopsis I
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I Document ID I Version Synopsis I
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11.5 MOTOROLA DSP NEWSThe Motorola
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DIGITAL SIGNAL PROCESSINGAlan V. Op
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C Programming Language:Controls:. C
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Image Processing:DIGITAL IMAGE PROC
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LINEAR PREDICTION OF SPEECHJ. D. Ma
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A.1 APPENDIX A INTRODUCTIONThis app
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XnYnTable A-1 Instruction Descripti
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Table A-1 Instruction Description N
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Table A-1 Instruction Description N
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Table A-2 DSP56K Addressing ModesAd
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The address register indirect addre
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A.SCONDITION CODE COMPUTATION15 14
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S1 SO Scaling Mode Signed Integer P
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Table A-5 Condition Code Computatio
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A.7 INSTRUCTION DESCRIPTIONSThe fol
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ABSAbsolute ValueABSInstruction For
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ADC Add Long with Carry ADCresult.
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ADD Add ADDCondition Codes:15 14 13
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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ANDLogical ANDANDInstruction Format
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGExplan
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and ChangeBCHGInstruct
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BCHG Bit Test and Change BCHGNotes:
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BCLR Bit Test and Clear BCLRExplana
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BClRBit Test and ClearBClRInstructi
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BClRBit Test and ClearBClRInstructi
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BClR Bit Test and Clear BClRNotes:
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BSET Bit Test and Set BSETExplanati
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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BSET Bit Test and Set BSETNotes: If
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BTSTBit TestBTSTCondition Codes:115
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8TSTBit Test8TSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLRClear AccumulatorCLRInstruction
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CMP Compare CMPCondition Codes:15 1
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CMPM Compare Magnitude CMPMConditio
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DEBUGEnter Debug ModeDEBUGOpcode:23
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DEBUGcc Enter Debug Mode Conditiona
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DEC Decrement by One DECInstruction
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DIV Divide Interation DIVThe DIV in
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DIV Divide Interation DIVNote that
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DIVInstruction Format:DIV S,DDivide
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DO Start Hardware Loop DOexecuted 6
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DOStart Hardware LoopDOAt LAOther R
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DOStart Hardware LoopDOInstruction
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DOStart Hardware LoopDOInstruction
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DO Start Hardware Loop DONotes: If
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ENDDO End Current DO Loop ENDDOExpl
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EOR Logical Exclusive OR EORInstruc
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCInstruction
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Jcc Jump Conditionally JccRestricti
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JccJump ConditionallyJccEffectiveAd
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JCLR Jump If Bit Clear JCLRRestrict
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JCLRJump If Bit ClearJCLRInstructio
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JCLR Jump If Bit Clear JCLRInstruct
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JMPJumpJMPInstruction Fields:xxx=12
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JSccJump to Subroutine Conditionall
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine If Bit Clea
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JSCLRJump to Subroutine If Bit Clea
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JSCLR Jump to Subroutine If Bit Cle
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JSET Jump if Bit Set JSETRestrictio
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JSETJump if Bit SetJSETInstruction
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JSET Jump If Bit Set JSETInstructio
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JSR Jump to Subroutine JSRInstructi
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine if Bit SetJ
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JSSET Jump to Subroutine if Bit Set
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LSL Logical Shift Left LSLCondition
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LSR Logical Shift Right LSRConditio
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LUALoad Updated AddressLUACondition
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MAC Signed Multiply-Accumulate MACC
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed MUltiply-Accumulate and
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MOVE Move Data MOVEExplanation of E
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MOVE Move Data MOVEWhen a 56-bit ac
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No Parallel Data MoveInstruction Fo
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I Immediate Short Data Move IExampl
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I Immediate Short Data Move IDDD d
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R Register to Register Data Move RE
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R Register to Register Data Move RI
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uAddress Register UpdateuInstructio
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X: X Memory Data Move X:Note:Due to
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X: X Memory Data Move X:S D DS,D d
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X: X Memory Data Move X:S D DS,D d
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X:R X Memory and Register Data Move
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Y: Y Memory Data Move Y:Note: This
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Y: Y Memory Data Move Y:S D DS,D d
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Y: Y Memory Data Move Y:S D DS,D d
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R:V Register and V Memory Data Move
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R:V Register and Y Memory Data Move
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R:V Register and Y Memory Data Move
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L: Long Memory Data Move L:Example:
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L: Long Memory Data Move L:Instruct
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X: Y: xv Memory Data Move X: Y:Exam
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X: Y: xv Memory Data Move X: Y:S1 D
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MOVEC Move Control Register MOVECst
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MOVEC Move Control Register MOVECCo
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MOVECMove Control RegisterMOVECInst
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MOVEC Move Control Register MOVECTi
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MOVEM Move Program Memory MOVEMoper
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MOVEM Move Program Memory MOVEMInst
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MOVEMMove Program MemoryMOVEMInstru
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MOVEP Move Peripheral Data MOVEPist
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MOVEP Move Peripheral Data MOVEPCon
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MOVEP Move Peripheral Data MOVEPIns
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MOVEP Move Peripheral Data MOVEPIns
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MPY Signed Multiply MPYExplanation
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MPY Signed Multiply MPYInstruction
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MPYR Signed Multiply and Round MPYR
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MPYR Signed Multiply and Round MPYR
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NEGNegate AccumulatorNEGInstruction
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NOPNo OperationNOPInstruction Forma
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NORM Normalize Accumulator Iteratio
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NOTLogical ComplementNOTInstruction
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ORLogical Inclusive ORORInstruction
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ORI OR Immediate with Control Regis
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REP Repeat Next Instruction REPRest
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REPRepeat Next InstructionREPInstru
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REPRepeat Next InstructionREPInstru
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REP Repeat Next Instruction REPNote
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RESETReset On-Chip Peripheral Devic
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RND Round Accumulator RNDConvergent
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RNDRound AccumulatorRNDInstruction
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ROL Rotate Left ROLCondition Codes:
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ROR Rotate Right RORCondition Codes
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RTIReturn from InterruptRTIConditio
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RTSReturn from SubroutineRTSInstruc
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sec Subtract Long with Carry secExp
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secSubtract Long with CarrysecInstr
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STOPStop Instruction ProcessingSTOP
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SUB Subtract SUBCondition Codes:S -
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SUBL Shift Left and Subtract Accumu
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SUBR Shift Right and Subtract Accum
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SWISoftware InterruptSWICondition C
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Tee Transfer Conditionally Teetion
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Tee Transfer Conditionally TeeInstr
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TFR Transfer Data ALU Register TFRC
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TSTTest AccumulatorTSTInstruction F
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WAIT Wait for Interrupt WAITConditi
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including the number of words per i
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5. Compute final results.Thus, base
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JLC (R2+N2)will requireand will exe
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Table A-6 Instruction Timing Summar
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Note that the "ap" term in Table A-
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Table A-14 Memory Access Timing Sum
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Other RestrictionsDO SSH,xxxxJSR to
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Immediately before MOVEC from SSH o
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A.9.S REP RestrictionsThe REP instr
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Table A-18 Triple-Bit Register Enco
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Table A-24 Program Control Unit Reg
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R: Register to Register Parallel Da
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JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
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JSSET#n,S,xxxx23 16 15 87 000001011
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BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
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MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
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LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
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ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
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Table A-28 Operation Code QQQ Decod
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Table A-30 Special Case #10 P E R C
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NEGD23 87 43 0DATA BUS MOVE FIELDLS
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ADDRS,D23 87 43 oDATA BUS MOVE FIEL
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lEI
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Table 8-1 27-MHz Benchmark Results
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.*._---*-----*-------**-------....
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;Latest Revision - September 30, 19
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All coefficients are divided by 2:w
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Real input FFT based on Glenn Bergl
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countountcountcountorg y:coefset 0d
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; Real-Valued FFT for MOTOROLA DSP5
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; first group in the last passmove
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A Accumulator ....... ' ...........
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-H- fast ..........................
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PGND ..............................
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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