section 7 - Index of
section 7 - Index of section 7 - Index of
(Rn) ± Nn MOD MWHERE Nn = 2k (Le., P = 1)Figure 4-12 Linear Addressing with a Modulo Modifierplus 20 (M-1». The Mn register is loaded with the value 20 (M-1). The offset register isarbitrarily chosen to be 15 (Nn~M). The address pointer is not required to start at the loweraddress boundary and can begin anywhere within the defined modulo address range -. i.e., within the lower boundary + (2k) address region. The address pointer, Rn, is arbitrarilychosen to be 75 in this example. When R2 is post-incremented by the offset by the MOVEinstruction, instead of pointing to 90 (as it would in the linear mode) it wraps around to 69.If the address register pointer increments past the upper boundary of the buffer (base addressplus M-1), it will wrap around to the base address. If the address decrements pastthe lower boundary (base address), it will wrap around to the base address plus M-1.If Rn is outside the valid modulo buffer range and an operation occurs that causes Rn tobe updated, the contents of Rn will be updated according to modulo arithmetic rules. Forexample, a MOVE BO,X:(RO)+ NO instruction (where RO=6, MO=5, and NO=O) would apparentlyleave RO unchanged since NO=O. However, since RO is above the upperboundary, the AGU calculates RO+ NO-MO-1 for the new contents of RO and sets RO=O.The MOVE instruction in Figure 4-13 takes the contents of the XO register and moves it toa location in the X memory pointed to by (R2), and then (R2) is updated modulo 21. The
EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00 ..... 0010100 I MODULUS=21N2 00 ..... 0001111 I OFFSET=15R2 00 ..... 1001011 I POINTER=75-Figure 4-13 Modulo Modifier Examplenew value of R2 is not 90 (75+ 15), which would be the case if linear arithmetic had beenused, but rather is 69 since modulo arithmetic was used.4.4.2.2.2 Mn=$8001 to $BFFFIn this range, the modulo (M) equals (Mn+ 1 )-$8000, where Mn is the value in the modifierregister (see Table 4-2). This range firmly restricts the address register to the samebuffer, causing the address register to wrap around within the buffer. This multiple wraparoundaddressing feature reduces argument overhead and is useful for decimation,interpolation, and waveform generation.The address modification is performed modulo M, where M may be any power of 2 in therange from 21 to 214. Modulo M arithmetic causes the address register value to remainwithin an address range of size M defined by a lower and upper address boundary. Thevalue M-1 is stored in the modifier register Mn least significant 14 bits while the two mostsignificant bits are set to '10'. The lower boundary (base address) value must have zeroesin the k LSBs, where 2k = M, and therefore must be a multiple of 2k. The upper boundaryis the lower boufldary plus the modulo size minus one (base address plus M-1).For example, to create a circular buffer of 32 stages, M is chosen as 32 and the lower addressboundary must have its 5 least significant bits equal to zero (2 k = 32, thus k = 5).
- Page 23 and 24: Digital FilteringFinite Impulse Res
- Page 25 and 26: architecture matches the shape of t
- Page 27 and 28: • DSP56001 Compatibility - All me
- Page 29: SECTION 2DSP56K CENTRAL ARCHITECTUR
- Page 32 and 33: --I«a:w:ca.ffi~a. a.24-Bit 56KModu
- Page 34 and 35: -rectly addressable registers: the
- Page 37 and 38: 3.1 DATA ARITHMETIC LOGIC UNITThis
- Page 39 and 40: 3.2.1 Data ALU Input Registers (X1,
- Page 41 and 42: """""" 24 BITS;:~:>~~::~~~:~:~:~:::
- Page 43 and 44: 3.2.4 Accumulator ShifterThe accumu
- Page 45 and 46: Table 3-1 Limited Data ValuesDestin
- Page 47 and 48: _--- N BITS ---_TWOS COMPLEMENT INT
- Page 49 and 50: CASE I: IF AO < $800000 (1/2), THEN
- Page 51 and 52: one instruction cycle. The ANDI ins
- Page 53: 3.5 DATA ALU PROGRAMMING MODELThe D
- Page 57 and 58: 4.1 ADDRESS GENERATION UNIT AND ADD
- Page 59 and 60: !---LOWADDRESS ALU -----I~.j.I.....
- Page 61 and 62: •••••••• _ ........
- Page 63 and 64: 4.4.1 Address Register Indirect Mod
- Page 65 and 66: EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
- Page 67 and 68: EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
- Page 69 and 70: EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
- Page 71 and 72: Table 4-2 Address Modifier SummaryM
- Page 73: ADDRESS -f-_POINTERUPPER BOUNDARYiM
- Page 77 and 78: oundary gives a 16-bit binary numbe
- Page 79 and 80: 4.4.2.4 Address-Modifier-Type Encod
- Page 81: SECTION 5PROGRAM CONTROL UNIT-
- Page 84 and 85: X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
- Page 86 and 87: interruptible since they are fetche
- Page 88 and 89: PROGRAM CONTROL UNIT-23 1615 023 16
- Page 90 and 91: The GGR is a special purpose contro
- Page 92 and 93: If S 1 =0 and SO=O (no scaling)then
- Page 94 and 95: -23 876543210I * 1* JSO I * I Mel y
- Page 96 and 97: 5.4.5.1 Stack Pointer (Bits 0-3)The
- Page 98 and 99: -DATA ARITHMETIC LOGIC UNITINPUT RE
- Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
- Page 103 and 104: shown in Figure 6-2. Most instructi
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
- Page 121 and 122: 6.4.2 LogicallnstructlonsThe logica
- Page 123 and 124: START OF LOOP1)SP+ 1 • SP; LA. SS
(Rn) ± Nn MOD MWHERE Nn = 2k (Le., P = 1)Figure 4-12 Linear Addressing with a Modulo Modifierplus 20 (M-1». The Mn register is loaded with the value 20 (M-1). The <strong>of</strong>fset register isarbitrarily chosen to be 15 (Nn~M). The address pointer is not required to start at the loweraddress boundary and can begin anywhere within the defined modulo address range -. i.e., within the lower boundary + (2k) address region. The address pointer, Rn, is arbitrarilychosen to be 75 in this example. When R2 is post-incremented by the <strong>of</strong>fset by the MOVEinstruction, instead <strong>of</strong> pointing to 90 (as it would in the linear mode) it wraps around to 69.If the address register pointer increments past the upper boundary <strong>of</strong> the buffer (base addressplus M-1), it will wrap around to the base address. If the address decrements pastthe lower boundary (base address), it will wrap around to the base address plus M-1.If Rn is outside the valid modulo buffer range and an operation occurs that causes Rn tobe updated, the contents <strong>of</strong> Rn will be updated according to modulo arithmetic rules. Forexample, a MOVE BO,X:(RO)+ NO instruction (where RO=6, MO=5, and NO=O) would apparentlyleave RO unchanged since NO=O. However, since RO is above the upperboundary, the AGU calculates RO+ NO-MO-1 for the new contents <strong>of</strong> RO and sets RO=O.The MOVE instruction in Figure 4-13 takes the contents <strong>of</strong> the XO register and moves it toa location in the X memory pointed to by (R2), and then (R2) is updated modulo 21. The