section 7 - Index of
section 7 - Index of section 7 - Index of
EXAMPLE: MOVE X: -(R5),B1BEFORE EXECUTIONAFTER EXECUTIONB2 B1 BO55 48 47 24 23 01 3 BIB 6 2 0 0 41 A 5 5 4 C 017 0 23 o 23 oB255 48 4713 BI17 o 23B1BO24 23 02 3 4 5 61 A 5 5 4 C 01o 23 0X MEMORY23 oX MEMORY23 0$3007$3006 I-------i$3007 1-------1$3006 I---'------i15 oR5 '---'----'R515 015 0N51 xxxx I15 0M51 $FFFFI15 0N51 XXXX I15 0M51 $FFFF1Assembler Syntax: -RnMemory Spaces: P:, X:, V:, L:Additional Instruction Execution Time (Clocks): 2Additional Effective Address Words: 0Figure 4-10 Address Register Indirect -Predecrement4.4.2.1 Linear Modifier (Mn=$FFFF)When the value in the modifier register is $FFFF, address modification is performed usingnormal 16-bit linear arithmetic (see Table 4-2). A 16-bit offset, Nn, and + 1 or -1 can beused in the address calculations. The range of values can be considered as signed (Nnfrom -32,768 to + 32,767) or unsigned (Nn from 0 to + 65,535) since there is no arithmeticdifference between these two data representations. Addresses are normally consideredunsigned, and data is normally considered signed.
Table 4-2 Address Modifier SummaryMMMMAddressing Mode Arithmetic0000 Reverse Carry (Bit Reverse)0001 Modulo 20002 Modulo 3-7FFE Modulo 327677FFF Modulo 327688000 Reserved8001 Multiple Wrap-Around Modulo 28002 Reserved8003 Multiple Wrap-Around Modulo 4Reserved8007 Multiple Wrap-Around Modulo 8Reserved800F Multiple Wrap-Around Modulo 24Reserved801F Multiple Wrap-Around Modulo 2 5 ..Reserved803F Multiple Wrap-Around Modulo 2 6Reserved807F Multiple Wrap-Around Modulo 27Reserved80FF Multiple Wrap-Around Modulo 2 8Reserved81FF Multiple Wrap-Around Modulo 29Reserved83FF Multiple Wrap-Around Modulo 2 10Reserved87FF Multiple Wrap-Around Modulo 211Reserved8FFF Multiple Wrap-Around Modulo 212Reserved9FFF Multiple Wrap-Around Modulo 2 13ReservedBFFF Multiple Wrap-Around Modulo 214ReservedFFFF Linear (Modulo 2 15 )
- Page 19 and 20: 1.1 INTRODUCTIONThe DSP56K family i
- Page 21 and 22: Fewer componentsStable, determinist
- Page 23 and 24: Digital FilteringFinite Impulse Res
- Page 25 and 26: architecture matches the shape of t
- Page 27 and 28: • DSP56001 Compatibility - All me
- Page 29: SECTION 2DSP56K CENTRAL ARCHITECTUR
- Page 32 and 33: --I«a:w:ca.ffi~a. a.24-Bit 56KModu
- Page 34 and 35: -rectly addressable registers: the
- Page 37 and 38: 3.1 DATA ARITHMETIC LOGIC UNITThis
- Page 39 and 40: 3.2.1 Data ALU Input Registers (X1,
- Page 41 and 42: """""" 24 BITS;:~:>~~::~~~:~:~:~:::
- Page 43 and 44: 3.2.4 Accumulator ShifterThe accumu
- Page 45 and 46: Table 3-1 Limited Data ValuesDestin
- Page 47 and 48: _--- N BITS ---_TWOS COMPLEMENT INT
- Page 49 and 50: CASE I: IF AO < $800000 (1/2), THEN
- Page 51 and 52: one instruction cycle. The ANDI ins
- Page 53: 3.5 DATA ALU PROGRAMMING MODELThe D
- Page 57 and 58: 4.1 ADDRESS GENERATION UNIT AND ADD
- Page 59 and 60: !---LOWADDRESS ALU -----I~.j.I.....
- Page 61 and 62: •••••••• _ ........
- Page 63 and 64: 4.4.1 Address Register Indirect Mod
- Page 65 and 66: EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
- Page 67 and 68: EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
- Page 69: EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
- Page 73 and 74: ADDRESS -f-_POINTERUPPER BOUNDARYiM
- Page 75 and 76: EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
- Page 77 and 78: oundary gives a 16-bit binary numbe
- Page 79 and 80: 4.4.2.4 Address-Modifier-Type Encod
- Page 81: SECTION 5PROGRAM CONTROL UNIT-
- Page 84 and 85: X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
- Page 86 and 87: interruptible since they are fetche
- Page 88 and 89: PROGRAM CONTROL UNIT-23 1615 023 16
- Page 90 and 91: The GGR is a special purpose contro
- Page 92 and 93: If S 1 =0 and SO=O (no scaling)then
- Page 94 and 95: -23 876543210I * 1* JSO I * I Mel y
- Page 96 and 97: 5.4.5.1 Stack Pointer (Bits 0-3)The
- Page 98 and 99: -DATA ARITHMETIC LOGIC UNITINPUT RE
- Page 101 and 102: 6.1 INSTRUCTION SET INTRODUCTIONThe
- Page 103 and 104: shown in Figure 6-2. Most instructi
- Page 105 and 106: 23 87 0L...-I ___-'-I_---'I BUS~ LS
- Page 107 and 108: The MR and CCR may be accessed indi
- Page 109 and 110: 6.3.4 Operand ReferencesThe DSP sep
- Page 111 and 112: Some address register indirect mode
- Page 113 and 114: EXAMPLE A: IMMEDIATE INTO 24-BIT RE
- Page 115 and 116: EXAMPLE A: IMMEDIATE SHORT INTO AO,
- Page 117 and 118: EXAMPLE A: MOVE P: $3200,XOBEFORE E
- Page 119 and 120: Table 6-1 Addressing Modes SummaryA
Table 4-2 Address Modifier SummaryMMMMAddressing Mode Arithmetic0000 Reverse Carry (Bit Reverse)0001 Modulo 20002 Modulo 3-7FFE Modulo 327677FFF Modulo 327688000 Reserved8001 Multiple Wrap-Around Modulo 28002 Reserved8003 Multiple Wrap-Around Modulo 4Reserved8007 Multiple Wrap-Around Modulo 8Reserved800F Multiple Wrap-Around Modulo 24Reserved801F Multiple Wrap-Around Modulo 2 5 ..Reserved803F Multiple Wrap-Around Modulo 2 6Reserved807F Multiple Wrap-Around Modulo 27Reserved80FF Multiple Wrap-Around Modulo 2 8Reserved81FF Multiple Wrap-Around Modulo 29Reserved83FF Multiple Wrap-Around Modulo 2 10Reserved87FF Multiple Wrap-Around Modulo 211Reserved8FFF Multiple Wrap-Around Modulo 212Reserved9FFF Multiple Wrap-Around Modulo 2 13ReservedBFFF Multiple Wrap-Around Modulo 214ReservedFFFF Linear (Modulo 2 15 )
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