section 7 - Index of

TABLE OF CONTENTSParagraphNumberTitleSECTION 1DSP56K FAMILY INTRODUCTIONPageNumber1.1 INTRODUCTION ............................................... 1-31.2 ORIGIN OF DIGITAL SIGNAL PROCESSING ........................ 1-31.3 SUMMARY OF DSP56K FAMILY FEATURES ........................ 1-91.4 MANUAL ORGANIZATION ...................................... 1-11SECTION 2DSP56K CENTRAL ARCHITECTUREOVERVIEW2.1 DSP56K CENTRAL ARCHITECTURE OVERVIEW .................... 2-32.2 DATA BUSES ................................................. 2-32.3 ADDRESS BUSES ............................................. 2-42.4 DATA ALU .................................................... 2-52.5 ADDRESS GENERATION UNIT ................................... 2-52.6 PROGRAM CONTROL UNIT ..................................... 2-52.7 MEMORY EXPANSION PORT (PORT A) ........................... 2-62.8 ON-CHIP EMULATOR (OnCE) .................................... 2-62.9 PHASE-LOCKED LOOP (PLL) BASED CLOCKING ................... 2-6SECTION 3DATA ARITHMETIC LOGIC UNIT3.1 DATA ARITHMETIC LOGIC UNIT ................................. 3-33.2 OVERVIEW AND DATA ALU ARCHITECTURE ...................... 3-33.3 DATA REPRESENTATION AND ROUNDING ....................... 3-103.4 DOUBLE PRECISION MULTIPLY MODE .......................... 3-16