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section 7 - Index of

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4.4.1 Address Register Indirect ModesWhen an address register is used to point to a memory location, the addressing mode iscalled "address register indirect" (see Table 4-1). The term indirect is used because theregister contents are not the operand itself, but rather the address <strong>of</strong> the operand. Theseaddressing modes specify that an operand is in memory and specify the effectiveaddress <strong>of</strong> that operand.A portion <strong>of</strong> the data bus movement field in the instruction specifies the memory space tobe referenced. The contents <strong>of</strong> specific AGU registers that determine the effectiveaddress are modified by arithmetic operations performed in the AGU. The type <strong>of</strong>address arithmetic used is specified by the address modifier register, Mn. The <strong>of</strong>fset register,Nn, is only used when the update specifies an <strong>of</strong>fset.Not all possible combinations are available, such as + (Rn). The 24-bit instruction wordsize is not large enough to allow a completely orthogonal instruction set for all instructionsused by the DSP.An example and description <strong>of</strong> each mode is given in the following paragraphs. SEC­TION 6 - INSTRUCTION SET INTRODUCTION and APPENDIX A - INSTRUCTION SETDETAILS give a complete description <strong>of</strong> the instruction syntax used in these examples.In particular, XV: memory references refer to instructions in which an operand in X memoryand an operand in V memory are referenced in the same instruction.4.4.1.1 No UpdateThe address <strong>of</strong> the operand is in the address register, Rn (see Table 4-1). The contents<strong>of</strong> the Rn register are unchanged by executing the instruction. Figure 4-4 shows a MOVEinstruction using address register indirect addressing with no update. This mode can beused for making XV: memory references. This mode does not use Nn or Mn registers.4.4.1.2 Postincrement By 1The address <strong>of</strong> the operand is in the address register, Rn (see Table 4-1 and Figure 4-5).After the operand address is used, it is incremented by 1 and stored in the same addressregister. This mode can be used for making XV: memory references and for modifyingthe contents <strong>of</strong> Rn without an associated data move.4.4.1.3 Postdecrement By 1The address <strong>of</strong> the operand is in the address register, Rn'(see Table 4-1 and Figure 4-6).After the operand address is used, it is decremented by 1 and stored in the sameaddress register. This mode can be used for making XV: memory references and formodifying the contents <strong>of</strong> Rn without an associated data move.

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