section 7 - Index of
section 7 - Index of section 7 - Index of
-M- OnCE Commands ..................... 10-19OnCE Controller ....................... 10-6OnCE Decoder ........................ 10-9OnCE Memory Breakpoint .............. 10-11OnCE Pins ........................... 10-3OnCE Serial Interface ................... 10-6OnCE Status and Control Register ......... 10-9On-Chip Emulator (OnCE) ................ 2-6Opcode ...................... '" ...... 6-3Opcode Field ........................... 6-5Operands ........... ; ................. 6-3accumulator ........................ 6-5byte .............................. 6-5long word .......................... 6-5miscellaneous ...................... A-7short word ......................... 6-5symbols for ........................ 6-9word .............................. 6-5Operating Mode Register (OMR) ...... 5-5, 5-14stop delay (SO) bit .................. 7-38Operation Word ......................... 6-3Operatorstable, binary ........................ A-7table, unary ........................ A-7Optional Effective Address Extension Word ... 6-3OR ................................ A-244OR(I) " ............................ A-246Overflow Bit ...................... 5-10, A-17Overflow Protection ...................... 3-8MAC ............................ 3-6,3-13MAC Instruction ...................... A-150MACR .............................. A-154Memory Breakpoint Control Bits ........... 10-9Memory Breakpoint Occurrence Bit ....... 10-11Memory Upper Limit Register ............ 10-12MFO-MF11 ........................... 9-12MODAlIROA ........................... 5-6MODBIIROB ........................... 5-6MODC/NMI ............................ 5-6Mode Control Pins ...................... 2-6Mode Register (MR) ..................... 5-9double precision multiply mode (bit 14) .. 5-13interrupt masks (bits 8 and 9) ......... 5-12loop flag (bit 15) ................... 5-13scaling mode (bits 10 and 11) ......... 5-12symbols table ...................... A-8trace mode (bit 13) ............. 5-13, 7-22Modulo Arithmetic ...................... 4-14Modulo Modifier ....................... 4-18linear addressing ................... 4-18multiple wrap-around addressing ...... 4-21MOVE .............................. A-158Move Instructions ...................... 6-26MOVE(C) ........................... A-206MOVE(M) ........................... A-214MOVEP ............................. A-220MPY ............................... A-228MPYR .............................. A-232Low Power Divider (LPD) ................. 9-5 -0-LSL ................................ A-144LSR ................................ A-146 Offset Reg isters ....................... .4-4LUA ................................ A-148OnCE ........................... 2-6, 10-3using the OnCE ................... 10-20OnCE Bit Counter .. " .................. 10-8-p--N- Parallel Move Descriptions ......... A-20, A-160address register update ............. A-172NEG ............................... A-236immediate short data move .......... A-164Negative Bit ..................... 5-10, A-17long memory data move ............ A-198NMI ............................. 5-6,7-17no parallel data move .............. A-162Nonmaskable Interrupt (NMI) " ........... 7-17register and Y memory data move .... A-192NOP ............................... A-238register to register data move ........ A-168NORM .............................. A-240X memory and register data move .... A-180Normal Processing State ................. 7-3X memory data move .............. A-17 4NOT ............................... A-242XY memory data move ............. A-202Y memory data move .............. A-186PC ...... " .. '" ............. '" ...... 5-5PCAP ............................... 9-10
PGND ................................ 9-9Phase Detector ......................... 9-4Phase-Locked Loop (PLL) ............ 2-6, 9-3PINIT ............................... 9-10PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 9-3frequency multiplier .................. 9-5hardware reset and . . . . . . . . . . . . . . . . . 9-11introduction ........................ 9-3loss of lock ....................... 9-13low power divider ................... 9-5operating frequency ................ 9-11operation while disabled ............. 9-12phase detector ..................... 9-4PLL control register .................. 9-5stop processing state and ............ 9-13voltage controlled oscillator (VCO) ...... 9-5PLL Control Register .................... 9-5division factor bits .................. 9-12multiplication factor bits .............. 9-12PLL Pins .............................. 9-9ckout ............................ 9-10ckp ............................. '. 9-10clgnd ............................ 9-10clvcc ............................ 9-10pcap ............................ 9-10pgnd ............................. 9-9pinit ............................. 9-10plock ............................ 9-10pvcc .............................. 9-9PLOCK .............................. 9-10Port A ............................ 2-6, 8-3Port A Interface ......................... 8-3Port A Signals .......................... 8-3bus control ......................... 8-5data bus .......................... 8-5Port A address ..................... 8-5Port A Wait States ...................... 8-6Power Consumption .................... 7-37Processing States ....................... 7-3interrupt (exception) ................ 7-10normal ................... , ........ 7-3stop ............................. 7-37wait ..... , ............ " ., .... '" 7-36Program Address Bus (PAB) .............. 2-4Program Address Generator (PAG) ......... 5-5Program Control Instructions ............. 6-27Program Control RegistersOMR and SR ....................... 6-8Program Control Unit .................... 5-3loop address (LA) ................... 2-6loop counter (LC) ................... 2-6operating mode register (OMR) ......... 2-6program address generator . . . . . . . . 2-5, 5-5program counter (PC) ................ 2-6program decode controller. . . . . . . .. 2-5, 5-5program interrupt controller . . . . . . .. 2-5, 5-6registers operands table .............. A-6stack pointer (SP) ................... 2-6status register (SR) .................. 2-6system stack ................... 2-5, 5-3. Program Counter (PC) ............... 5-5, 5-8Program Data Bus (PDB) ................. 2-3Program Decode Controller ............... 5-5Program Interrupt Controller ............... 5-6Programming ModelAGU .............................. 4-6data ALU ......................... 3-19program control unit .................. 5-8summary ......................... 5-17PVCC ................................ 9-9-R-Read/Write Controls ..................... 8-5Referencesmemory .......................... 6-11operand .......................... 6-11program .......................... 6-11register ........................... 6-11stack ............................ 6-11Register Direct ........................ 6-13Register Indirect ....................... .4-8Register References .................... 6-11REP Instruction ................... 5-5, A-248RESET Instruction .................... A-256RESET Pin ............................ 5-6Reset Processing Stateentering .......................... 7-33leaving ........................... 7-33PLL and .......................... 9-11Reverse-Carry Arithmetic ................ 4-14Reverse-Carry Modifier ................. .4-22RND .............................. A-258ROL ............................... A-262ROR .............................. A-264Rounding ............................. 3-10RTI ............................... A-266RTI and RTS Instruction Restrictions ........ 7-9RTS ............................... A-268
- Page 551 and 552: A.9.S REP RestrictionsThe REP instr
- Page 553 and 554: Table A-18 Triple-Bit Register Enco
- Page 555 and 556: Table A-24 Program Control Unit Reg
- Page 557 and 558: R: Register to Register Parallel Da
- Page 559 and 560: JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
- Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
- Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
- Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
- Page 567 and 568: LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
- Page 569 and 570: ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
- Page 571 and 572: Table A-28 Operation Code QQQ Decod
- Page 573 and 574: Table A-30 Special Case #10 P E R C
- Page 575 and 576: NEGD23 87 43 0DATA BUS MOVE FIELDLS
- Page 577: ADDRS,D23 87 43 oDATA BUS MOVE FIEL
- Page 580 and 581: lEI
- Page 582 and 583: Table 8-1 27-MHz Benchmark Results
- Page 584 and 585: .*._---*-----*-------**-------....
- Page 586 and 587: ;Latest Revision - September 30, 19
- Page 588 and 589: All coefficients are divided by 2:w
- Page 590 and 591: Real input FFT based on Glenn Bergl
- Page 592 and 593: countountcountcountorg y:coefset 0d
- Page 594 and 595: ; Real-Valued FFT for MOTOROLA DSP5
- Page 596 and 597: ; first group in the last passmove
- Page 599 and 600: A Accumulator ....... ' ...........
- Page 601: -H- fast ..........................
- Page 605 and 606: DSP56K FAMILY INTRODUCTIONDSP56K CE
PGND ................................ 9-9Phase Detector ......................... 9-4Phase-Locked Loop (PLL) ............ 2-6, 9-3PINIT ............................... 9-10PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 9-3frequency multiplier .................. 9-5hardware reset and . . . . . . . . . . . . . . . . . 9-11introduction ........................ 9-3loss <strong>of</strong> lock ....................... 9-13low power divider ................... 9-5operating frequency ................ 9-11operation while disabled ............. 9-12phase detector ..................... 9-4PLL control register .................. 9-5stop processing state and ............ 9-13voltage controlled oscillator (VCO) ...... 9-5PLL Control Register .................... 9-5division factor bits .................. 9-12multiplication factor bits .............. 9-12PLL Pins .............................. 9-9ckout ............................ 9-10ckp ............................. '. 9-10clgnd ............................ 9-10clvcc ............................ 9-10pcap ............................ 9-10pgnd ............................. 9-9pinit ............................. 9-10plock ............................ 9-10pvcc .............................. 9-9PLOCK .............................. 9-10Port A ............................ 2-6, 8-3Port A Interface ......................... 8-3Port A Signals .......................... 8-3bus control ......................... 8-5data bus .......................... 8-5Port A address ..................... 8-5Port A Wait States ...................... 8-6Power Consumption .................... 7-37Processing States ....................... 7-3interrupt (exception) ................ 7-10normal ................... , ........ 7-3stop ............................. 7-37wait ..... , ............ " ., .... '" 7-36Program Address Bus (PAB) .............. 2-4Program Address Generator (PAG) ......... 5-5Program Control Instructions ............. 6-27Program Control RegistersOMR and SR ....................... 6-8Program Control Unit .................... 5-3loop address (LA) ................... 2-6loop counter (LC) ................... 2-6operating mode register (OMR) ......... 2-6program address generator . . . . . . . . 2-5, 5-5program counter (PC) ................ 2-6program decode controller. . . . . . . .. 2-5, 5-5program interrupt controller . . . . . . .. 2-5, 5-6registers operands table .............. A-6stack pointer (SP) ................... 2-6status register (SR) .................. 2-6system stack ................... 2-5, 5-3. Program Counter (PC) ............... 5-5, 5-8Program Data Bus (PDB) ................. 2-3Program Decode Controller ............... 5-5Program Interrupt Controller ............... 5-6Programming ModelAGU .............................. 4-6data ALU ......................... 3-19program control unit .................. 5-8summary ......................... 5-17PVCC ................................ 9-9-R-Read/Write Controls ..................... 8-5Referencesmemory .......................... 6-11operand .......................... 6-11program .......................... 6-11register ........................... 6-11stack ............................ 6-11Register Direct ........................ 6-13Register Indirect ....................... .4-8Register References .................... 6-11REP Instruction ................... 5-5, A-248RESET Instruction .................... A-256RESET Pin ............................ 5-6Reset Processing Stateentering .......................... 7-33leaving ........................... 7-33PLL and .......................... 9-11Reverse-Carry Arithmetic ................ 4-14Reverse-Carry Modifier ................. .4-22RND .............................. A-258ROL ............................... A-262ROR .............................. A-264Rounding ............................. 3-10RTI ............................... A-266RTI and RTS Instruction Restrictions ........ 7-9RTS ............................... A-268
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