section 7 - Index of

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; first group in the last passmove x:(rO)+,A y:(r4)+,Bsub B,A x:(rO)+,xO y:(r6)+,yOaddl A,B A,x:(r1) y:(r4),Asub xO,A B,x:(r7)move y:(r4)+,Badd xO,B A,y:(r1)move x:(rO)+,A B,y:(r7);A=a, B=c;A=a-c=c',xO=b, yO=Wr for next bfly;B=a+C=a', A=d,PUT c' to x:b;A=d-b=d',PUT a' to x;B=d;B=d+b=b', A=next a,PUT d';A=next a, PUT b'movedox:(r2)+,xO y:(r4)+,Bn2,endJastg;xO=Wi,B=next c;rest groups in the last passIntermediate Passes -- W(n) < 1A---\ /---A'= Re[ A + jC + (B - jO)W(k)] = A+BWr+OWi=A+ T1B----\-'-'----B'= Im[ A + jC - (B - jO)W(k)] = C+OWr-BWi= T2+CC----/I \----C'= Re[ A + jC - (B - jO)W(k)] = A-(BWr+OWi)=A-T10---/ \---0'= Im[-A - jC - (B - jO)W(k) ] = -C+OWr-BWi= T2-Cmove x:(rO)+,x1 y:(r4)-,y1mpy x1 ,yO,B x:(r3)+,r7mac xO,y1,B x:(r3)+,r1sub B,Aaddl A,B A,x:(r1)mpy y1 ,yO,A B,x:(r7)mac -x1,xO,A y:(r4)+n4,Bsub B,A x:(r2)+,xO y:(r6)+,yOaddl A,B A,y:(r1)move x:(rO)+,A B,y:(r7)move y:(r4)+,B;x1 =b, y1 =d, r4 ptr back to c;A=bWr,;B=bWr +dWi= T1 , get first index;A=a-T1=c', get second index;B=a+ T1 =a', PUT c' to x:b;B=dWr, B=c PUT a';A=dWi-bWr= T2, B=c, r4 ptr to next c;A= T2-c=d',xO=next Wi, yO=next Wr;B= T2+c=b', update r4, A=next a, PUT d';PUT b', A=next a;B=nextcendm; Real input FFT based on Glenn Bergland algorithm; Normal order input and normal order output.; Since 56001 does not support Bergland addressing, extra instruction cycles are needed; for converting Bergland order to normal order.lt has been done in the last pass by; looking at the bergtable.; 'bergsincos' generates sin and cos table with size of points/4,COS in Y, SIN in X; 'bergorder' generates table for address conversion, the size of twiddle factors is half; of FFT output's; 'rfft-56b' does FFT.; Normal order input and normal order output.Figure 8-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 7 of 8)
; Real input data are split into two parts, the first part is put in X, the second in Y.; Real output data are in X, imaginary output data are in Y.; The first real output is DC; The first imaginary output is the Nyquist frequency.; Note that only DC to Nyquist frequency range is calculated by this algorithm; After twiddle factors and bergtable are generated, you may overwrite 'bergorder',; 'norm2berg' by 'rfft-56b' for saving P memory.Performance,----------------------------------------------- -----------------Real input data points641282565121024Clock cycle1686384686561929649776Memory (word),----------------------------------------------------------------P memoryX memory87points/2+ (real input)points/4+ (SIN table)points/2+ (real output)points/2 (bergtable)Ymemorypoints/2+ (imaginary input)points/4+ (COS table)pOints/2 (imaginary output)Figure 8-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 8 of 8)
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DSP56K FAMILY INTRODUCTIONDSP56K CE
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Motorola reserves the right to make
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Table of Contents (Continued)Paragr
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ParagraphNumberTable of Contents (C
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FigureNumberList of Figures (Contin
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List of Tables (Continued)TablePage
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1.1 INTRODUCTIONThe DSP56K family i
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Fewer componentsStable, determinist
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Digital FilteringFinite Impulse Res
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architecture matches the shape of t
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• DSP56001 Compatibility - All me
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SECTION 2DSP56K CENTRAL ARCHITECTUR
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--I«a:w:ca.ffi~a. a.24-Bit 56KModu
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-rectly addressable registers: the
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3.1 DATA ARITHMETIC LOGIC UNITThis
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3.2.1 Data ALU Input Registers (X1,
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"""""" 24 BITS;:~:>~~::~~~:~:~:~:::
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3.2.4 Accumulator ShifterThe accumu
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Table 3-1 Limited Data ValuesDestin
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_--- N BITS ---_TWOS COMPLEMENT INT
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CASE I: IF AO < $800000 (1/2), THEN
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one instruction cycle. The ANDI ins
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3.5 DATA ALU PROGRAMMING MODELThe D
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4.1 ADDRESS GENERATION UNIT AND ADD
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!---LOWADDRESS ALU -----I~.j.I.....
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•••••••• _ ........
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4.4.1 Address Register Indirect Mod
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EXAMPLE: MOVE BO,V: (R1)+BEFORE EXE
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EXAMPLE: MOVE X1,X: (R2)+N2BEFORE E
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EXAMPLE: MOVE Y1,X: (RS+NS)BEFORE E
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Table 4-2 Address Modifier SummaryM
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ADDRESS -f-_POINTERUPPER BOUNDARYiM
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EXAMPLE: MOVE XO,X:(R2)+NLET:M2 00
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oundary gives a 16-bit binary numbe
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4.4.2.4 Address-Modifier-Type Encod
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SECTION 5PROGRAM CONTROL UNIT-
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X MEMORYRAM/ROMIII E:XPAf'JSIC)N LI
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interruptible since they are fetche
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PROGRAM CONTROL UNIT-23 1615 023 16
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The GGR is a special purpose contro
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If S 1 =0 and SO=O (no scaling)then
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-23 876543210I * 1* JSO I * I Mel y
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5.4.5.1 Stack Pointer (Bits 0-3)The
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-DATA ARITHMETIC LOGIC UNITINPUT RE
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6.1 INSTRUCTION SET INTRODUCTIONThe
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shown in Figure 6-2. Most instructi
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23 87 0L...-I ___-'-I_---'I BUS~ LS
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The MR and CCR may be accessed indi
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6.3.4 Operand ReferencesThe DSP sep
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Some address register indirect mode
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EXAMPLE A: IMMEDIATE INTO 24-BIT RE
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EXAMPLE A: IMMEDIATE SHORT INTO AO,
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EXAMPLE A: MOVE P: $3200,XOBEFORE E
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Table 6-1 Addressing Modes SummaryA
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6.4.2 LogicallnstructlonsThe logica
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START OF LOOP1)SP+ 1 • SP; LA. SS
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OPCODE/OPERANDSPARALLEL MOVE EXAMPL
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SECTION 7PROCESSING STATES-
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Each instruction requires a minimum
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second instruction of the downloade
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The DO instruction is another instr
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SP and SSH/SSL register manipulatio
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7.3.1 Interrupt TypesThe DSP56K rel
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Table 7-2 Status Register Interrupt
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7.3.3 Interrupt SourcesInterrupts c
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interrupts makes it very useful for
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MAINPROGRAMFETCHESLONG INTERRUPTSER
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7.3.3.3 Other Interrupt SourcesOthe
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7.3.4 Interrupt ArbitrationInterrup
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7.3.7 Interrupt Instruction Executi
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MAINPROGRAMMEMORYINTERRUPT SYNCHRON
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MAINPROGRAMFETCHESINTERRUPTSYNCHRON
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MAINPROGRAMFAST INTERRUPTVECTORLONG
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MAINPROGRAMFETCHESNTERRUPTSYN8HRCNZ
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7.5 WAIT PROCESSING STATEThe WAIT i
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The stop processing state halts all
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the first instruction fetch). If th
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RESET -----------------------------
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16 - BIT INTERNALADDRESS BUSESX ADD
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8.2.2.1 Address (AO-A15)These three
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SECTION 9PLL CLOCK OSCILLATOR-
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X MEMORYRAM/ROMEXPANSION24-Bit56KMo
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23 22 21 20 19 18 17 16 15 14 13 12
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cleared. To enable rapid recovery w
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-CLVCCVCC for the CKOUT output. The
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4. For all input frequencies which
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While the PLL is regaining lock, th
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10.1 ON-CHIP EMULATION INTRODUCTION
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10.2.2 Debug Serial Clock/Chip Stat
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76543210I R/W I GO I EX I RS41 RS31
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shifted in (so a new command is ava
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10.3.4.4 Software Debug Occurrence
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10.4.4 Memory High Address Comparat
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10.6.1 External Debug Request Durin
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PABCIRCULARBUFFERPOINTERDSCKDSOFigu
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are serially available to the exter
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k. ACKI. ClKm. Send command READ FI
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19. ACK20. Send command READ GDB RE
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10.11.6.1 Case 1: Return To The Pre
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SECTION 11ADDITIONAL SUPPORTDr. BuB
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The following is a partial list of
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• In-line assembler language code
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I Document 10 I Version Synopsis I
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I Document ID I Version Synopsis I
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11.5 MOTOROLA DSP NEWSThe Motorola
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DIGITAL SIGNAL PROCESSINGAlan V. Op
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C Programming Language:Controls:. C
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Image Processing:DIGITAL IMAGE PROC
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LINEAR PREDICTION OF SPEECHJ. D. Ma
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A.1 APPENDIX A INTRODUCTIONThis app
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XnYnTable A-1 Instruction Descripti
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Table A-1 Instruction Description N
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Table A-1 Instruction Description N
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Table A-2 DSP56K Addressing ModesAd
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The address register indirect addre
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A.SCONDITION CODE COMPUTATION15 14
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S1 SO Scaling Mode Signed Integer P
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Table A-5 Condition Code Computatio
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A.7 INSTRUCTION DESCRIPTIONSThe fol
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ABSAbsolute ValueABSInstruction For
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ADC Add Long with Carry ADCresult.
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ADD Add ADDCondition Codes:15 14 13
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ADDL Shift Left and Add Accumulator
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ADDR Shift Right and Add Accumulato
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ANDLogical ANDANDInstruction Format
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ANDIAND Immediate with Control Regi
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ASL Arithmetic Shift Accumulator Le
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ASR Arithmetic Shift Accumulator Ri
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BCHG Bit Test and Change BCHGExplan
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BCHGBit Test and ChangeBCHGInstruct
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BCHGBit Test and ChangeBCHGInstruct
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BCHG Bit Test and Change BCHGNotes:
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BCLR Bit Test and Clear BCLRExplana
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BClRBit Test and ClearBClRInstructi
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BClRBit Test and ClearBClRInstructi
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BClR Bit Test and Clear BClRNotes:
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BSET Bit Test and Set BSETExplanati
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BSETBit Test and SetBSETInstruction
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BSETBit Test and SetBSETInstruction
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BSET Bit Test and Set BSETNotes: If
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BTSTBit TestBTSTCondition Codes:115
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8TSTBit Test8TSTInstruction Format:
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8TSTBit Test8TSTInstruction Format:
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CLRClear AccumulatorCLRInstruction
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CMP Compare CMPCondition Codes:15 1
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CMPM Compare Magnitude CMPMConditio
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DEBUGEnter Debug ModeDEBUGOpcode:23
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DEBUGcc Enter Debug Mode Conditiona
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DEC Decrement by One DECInstruction
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DIV Divide Interation DIVThe DIV in
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DIV Divide Interation DIVNote that
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DIVInstruction Format:DIV S,DDivide
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DO Start Hardware Loop DOexecuted 6
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DOStart Hardware LoopDOAt LAOther R
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DOStart Hardware LoopDOInstruction
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DOStart Hardware LoopDOInstruction
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DO Start Hardware Loop DONotes: If
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ENDDO End Current DO Loop ENDDOExpl
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EOR Logical Exclusive OR EORInstruc
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ILLEGALIllegal Instruction Interrup
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INC Increment by One INCInstruction
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Jcc Jump Conditionally JccRestricti
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JccJump ConditionallyJccEffectiveAd
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JCLR Jump If Bit Clear JCLRRestrict
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JCLRJump If Bit ClearJCLRInstructio
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JCLR Jump If Bit Clear JCLRInstruct
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JMPJumpJMPInstruction Fields:xxx=12
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JSccJump to Subroutine Conditionall
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JScc Jump to Subroutine Conditional
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JSCLR Jump to Subroutine if Bit Cle
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JSCLRJump to Subroutine If Bit Clea
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JSCLRJump to Subroutine If Bit Clea
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JSCLR Jump to Subroutine If Bit Cle
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JSET Jump if Bit Set JSETRestrictio
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JSETJump if Bit SetJSETInstruction
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JSET Jump If Bit Set JSETInstructio
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JSR Jump to Subroutine JSRInstructi
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JSSET Jump to Subroutine if Bit Set
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JSSETJump to Subroutine if Bit SetJ
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JSSET Jump to Subroutine if Bit Set
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LSL Logical Shift Left LSLCondition
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LSR Logical Shift Right LSRConditio
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LUALoad Updated AddressLUACondition
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MAC Signed Multiply-Accumulate MACC
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MACSigned Multiply-AccumulateMACTim
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MACR Signed Multiply-Accumulate and
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MACR Signed MUltiply-Accumulate and
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MOVE Move Data MOVEExplanation of E
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MOVE Move Data MOVEWhen a 56-bit ac
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No Parallel Data MoveInstruction Fo
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I Immediate Short Data Move IExampl
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I Immediate Short Data Move IDDD d
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R Register to Register Data Move RE
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R Register to Register Data Move RI
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uAddress Register UpdateuInstructio
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X: X Memory Data Move X:Note:Due to
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X: X Memory Data Move X:S D DS,D d
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X: X Memory Data Move X:S D DS,D d
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X:R X Memory and Register Data Move
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Y: Y Memory Data Move Y:Note: This
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Y: Y Memory Data Move Y:S D DS,D d
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Y: Y Memory Data Move Y:S D DS,D d
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R:V Register and V Memory Data Move
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R:V Register and Y Memory Data Move
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R:V Register and Y Memory Data Move
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L: Long Memory Data Move L:Example:
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L: Long Memory Data Move L:Instruct
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X: Y: xv Memory Data Move X: Y:Exam
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X: Y: xv Memory Data Move X: Y:S1 D
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MOVEC Move Control Register MOVECst
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MOVEC Move Control Register MOVECCo
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MOVECMove Control RegisterMOVECInst
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MOVEC Move Control Register MOVECTi
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MOVEM Move Program Memory MOVEMoper
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MOVEM Move Program Memory MOVEMInst
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MOVEMMove Program MemoryMOVEMInstru
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MOVEP Move Peripheral Data MOVEPist
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MOVEP Move Peripheral Data MOVEPCon
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MOVEP Move Peripheral Data MOVEPIns
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MOVEP Move Peripheral Data MOVEPIns
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MPY Signed Multiply MPYExplanation
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MPY Signed Multiply MPYInstruction
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MPYR Signed Multiply and Round MPYR
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MPYR Signed Multiply and Round MPYR
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NEGNegate AccumulatorNEGInstruction
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NOPNo OperationNOPInstruction Forma
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NORM Normalize Accumulator Iteratio
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NOTLogical ComplementNOTInstruction
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ORLogical Inclusive ORORInstruction
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ORI OR Immediate with Control Regis
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REP Repeat Next Instruction REPRest
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REPRepeat Next InstructionREPInstru
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REPRepeat Next InstructionREPInstru
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REP Repeat Next Instruction REPNote
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RESETReset On-Chip Peripheral Devic
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RND Round Accumulator RNDConvergent
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RNDRound AccumulatorRNDInstruction
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ROL Rotate Left ROLCondition Codes:
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ROR Rotate Right RORCondition Codes
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RTIReturn from InterruptRTIConditio
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RTSReturn from SubroutineRTSInstruc
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sec Subtract Long with Carry secExp
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secSubtract Long with CarrysecInstr
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STOPStop Instruction ProcessingSTOP
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SUB Subtract SUBCondition Codes:S -
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SUBL Shift Left and Subtract Accumu
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SUBR Shift Right and Subtract Accum
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SWISoftware InterruptSWICondition C
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Tee Transfer Conditionally Teetion
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Tee Transfer Conditionally TeeInstr
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TFR Transfer Data ALU Register TFRC
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TSTTest AccumulatorTSTInstruction F
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WAIT Wait for Interrupt WAITConditi
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including the number of words per i
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5. Compute final results.Thus, base
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JLC (R2+N2)will requireand will exe
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Table A-6 Instruction Timing Summar
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Note that the "ap" term in Table A-
Page 545 and 546: Table A-14 Memory Access Timing Sum
Page 547 and 548: Other RestrictionsDO SSH,xxxxJSR to
Page 549 and 550: Immediately before MOVEC from SSH o
Page 551 and 552: A.9.S REP RestrictionsThe REP instr
Page 553 and 554: Table A-18 Triple-Bit Register Enco
Page 555 and 556: Table A-24 Program Control Unit Reg
Page 557 and 558: R: Register to Register Parallel Da
Page 559 and 560: JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
Page 567 and 568: LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
Page 569 and 570: ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
Page 571 and 572: Table A-28 Operation Code QQQ Decod
Page 573 and 574: Table A-30 Special Case #10 P E R C
Page 575 and 576: NEGD23 87 43 0DATA BUS MOVE FIELDLS
Page 577: ADDRS,D23 87 43 oDATA BUS MOVE FIEL
Page 580 and 581: lEI
Page 582 and 583: Table 8-1 27-MHz Benchmark Results
Page 584 and 585: .*._---*-----*-------**-------....
Page 586 and 587: ;Latest Revision - September 30, 19
Page 588 and 589: All coefficients are divided by 2:w
Page 590 and 591: Real input FFT based on Glenn Bergl
Page 592 and 593: countountcountcountorg y:coefset 0d
Page 594 and 595: ; Real-Valued FFT for MOTOROLA DSP5
Page 599 and 600: A Accumulator ....... ' ...........
Page 601 and 602: -H- fast ..........................
Page 603 and 604: PGND ..............................
Page 605 and 606: DSP56K FAMILY INTRODUCTIONDSP56K CE
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