section 7 - Index of

page 132,66,0,6opt rc...._..__......._...__.....*-_..._..*••••••_••••••••_-•••••,;Motorola Austin DSP Operation June 30, 1988._•••••*•••_•••••_••_••_•••_._--------_.--_.__••••_._-•••••;DSP56000/1;8-pole 4-multiply cascaded canonic IIR filter;File name: 4-56.asm.••••_.__•___••••_••_.___•___•_____•_____._••__•___._••*_••_*._....._......___._._.__..____*_••___••__•••___ *'It'lt••_____•,Maximum sample rate: 410.0 kHz at 20.5 MHz/540.0 kHz at 27.0 MHzMemory Size: Prog: 6+10 words; Data: 4(2+4) wordsNumber of clock cycles: 50 (25 instruction cycles)Clock Frequency: 20.5 MHz/27.0 MHz, Instruction cycle time: 97.5 nsn4.1 ns.*****************************************************.*'It'lt'lt__••__.**__._*______....__._.______....._.*._.... 'It'lt'lt'lt'lt_._•••This IIR filter reads the input samplefrom the memory location Y:inputand writes the filtered output sampleto the memory location Y:outputThe samples are stored in the X memoryThe coefficients are stored in the Y memoryThe equations of the filter are:w(n)= x(n)-ai1 *w(n-1 )-ai2*w(n-2)y(n)= w(n)+bi1 *w(n-1 )+bi2*w(n-2)x(n}/----( -)/----------1---+-1.,--------(wen)zw(n-1)~ai1+bi1~z-1 w(n-2)+ }----- yen)f-o_--- ai2 __ -,----..._....Ll--l._--- bi2---__ -lFigure 8-3 a-Pole 4-Multlply Cascaded Canonic IIR Filter (Sheet 1 of 2)