section 7 - Index of
section 7 - Index of section 7 - Index of
A.10.3 Instruction Encoding for Instructions Which Do Not Allow Parallel MovesNote:JScc xxxFor following bit class instructions bbbbb = 11 bbb is reserved:JSSET, JSClR, JSET, JClR, BTST, BCHG, BSET, and BClA.23 16 15 87 0I 0 0 0 0 1 1 1 1 C C C C a a a a I a a a a a a a a IJccJSRXXX23 16 15 87 0I 0 0 0 0 1 1 1 o I C C C C a a a a I a a a a a a a a IXXXJMP XXXJScc ea23 16 15 87 0I 0 0 0 0 1 1 0 1 I 0 0 0 0 a a a a I a a a a a a a a I23 16 15 87 0I 0 0 0 0 1 1 0 0 0 0 0 0 a a a a I a a a a a a a a I23 16 15 87 00 0 0 0 1 0 1 1 1 1 M M M R R R 1 0 1 0 C C C COPTIONAL EFFECTIVE ADDRESS EXTENSIONJSRea23 16 15 87 00 0 0 0 1 0 1 1 1 1 M M M R R R 1 0 0 0 0 0 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSIONJccea23 16 15 87 00 0 0 0 1 0 1 0 1 1 M M M R R R 1 0 1 0 C C C COPTIONAL EFFECTIVE ADDRESS EXTENSIONJMP ea23 16 15 87 00 0 0 0 1 0 1 0 1 1 M M M R R R 1 0 0 0 0 0 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSION
JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx23 16 15 87o00001011 10pppppp 1 S 1 b b b b bABSOLUTE ADDRESS EXTENSIONJSCLRJSCLR#n,X:pp,XXXX#n,Y:pp,XXXX23 16 15 87 000001011 10pppppp 1S0bbbbbABSOLUTE ADDRESS EXTENSIONJSETJSET#n,X:pp,XXXX#n,Y:pp,XXXX23 1615 87 000001010 10pppppp 1S1 bbbbbABSOLUTE ADDRESS EXTENSIONJCLRJCLR#n,X:pp,XXXX#n,Y:pp,XXXX23 16 15 87 000001010 10pppppp 1S0bbbbbABSOLUTE ADDRESS EXTENSIONJSSETJSSET#n,X:ea,xxxxIn, Y:ea,xxxx23 16 15 8700001011 01MMMRRR 1S1 bbbbbABSOLUTE ADDRESS EXTENSIONoJSCLRJSCLR#n,X:ea,xxxxIn, Y:ea,xxxx23 16 15 87 000001011 01MMMRRR 1S0bbbbbABSOLUTE ADDRESS EXTENSION
- Page 507 and 508: RTIReturn from InterruptRTIConditio
- Page 509 and 510: RTSReturn from SubroutineRTSInstruc
- Page 511 and 512: sec Subtract Long with Carry secExp
- Page 513 and 514: secSubtract Long with CarrysecInstr
- Page 515 and 516: STOPStop Instruction ProcessingSTOP
- Page 517 and 518: SUB Subtract SUBCondition Codes:S -
- Page 519 and 520: SUBL Shift Left and Subtract Accumu
- Page 521 and 522: SUBR Shift Right and Subtract Accum
- Page 523 and 524: SWISoftware InterruptSWICondition C
- Page 525 and 526: Tee Transfer Conditionally Teetion
- Page 527 and 528: Tee Transfer Conditionally TeeInstr
- Page 529 and 530: TFR Transfer Data ALU Register TFRC
- Page 531 and 532: TSTTest AccumulatorTSTInstruction F
- Page 533 and 534: WAIT Wait for Interrupt WAITConditi
- Page 535 and 536: including the number of words per i
- Page 537 and 538: 5. Compute final results.Thus, base
- Page 539 and 540: JLC (R2+N2)will requireand will exe
- Page 541 and 542: Table A-6 Instruction Timing Summar
- Page 543 and 544: Note that the "ap" term in Table A-
- Page 545 and 546: Table A-14 Memory Access Timing Sum
- Page 547 and 548: Other RestrictionsDO SSH,xxxxJSR to
- Page 549 and 550: Immediately before MOVEC from SSH o
- Page 551 and 552: A.9.S REP RestrictionsThe REP instr
- Page 553 and 554: Table A-18 Triple-Bit Register Enco
- Page 555 and 556: Table A-24 Program Control Unit Reg
- Page 557: R: Register to Register Parallel Da
- Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
- Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
- Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
- Page 567 and 568: LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
- Page 569 and 570: ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
- Page 571 and 572: Table A-28 Operation Code QQQ Decod
- Page 573 and 574: Table A-30 Special Case #10 P E R C
- Page 575 and 576: NEGD23 87 43 0DATA BUS MOVE FIELDLS
- Page 577: ADDRS,D23 87 43 oDATA BUS MOVE FIEL
- Page 580 and 581: lEI
- Page 582 and 583: Table 8-1 27-MHz Benchmark Results
- Page 584 and 585: .*._---*-----*-------**-------....
- Page 586 and 587: ;Latest Revision - September 30, 19
- Page 588 and 589: All coefficients are divided by 2:w
- Page 590 and 591: Real input FFT based on Glenn Bergl
- Page 592 and 593: countountcountcountorg y:coefset 0d
- Page 594 and 595: ; Real-Valued FFT for MOTOROLA DSP5
- Page 596 and 597: ; first group in the last passmove
- Page 599 and 600: A Accumulator ....... ' ...........
- Page 601 and 602: -H- fast ..........................
- Page 603 and 604: PGND ..............................
- Page 605 and 606: DSP56K FAMILY INTRODUCTIONDSP56K CE
A.10.3 Instruction Encoding for Instructions Which Do Not Allow Parallel MovesNote:JScc xxxFor following bit class instructions bbbbb = 11 bbb is reserved:JSSET, JSClR, JSET, JClR, BTST, BCHG, BSET, and BClA.23 16 15 87 0I 0 0 0 0 1 1 1 1 C C C C a a a a I a a a a a a a a IJccJSRXXX23 16 15 87 0I 0 0 0 0 1 1 1 o I C C C C a a a a I a a a a a a a a IXXXJMP XXXJScc ea23 16 15 87 0I 0 0 0 0 1 1 0 1 I 0 0 0 0 a a a a I a a a a a a a a I23 16 15 87 0I 0 0 0 0 1 1 0 0 0 0 0 0 a a a a I a a a a a a a a I23 16 15 87 00 0 0 0 1 0 1 1 1 1 M M M R R R 1 0 1 0 C C C COPTIONAL EFFECTIVE ADDRESS EXTENSIONJSRea23 16 15 87 00 0 0 0 1 0 1 1 1 1 M M M R R R 1 0 0 0 0 0 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSIONJccea23 16 15 87 00 0 0 0 1 0 1 0 1 1 M M M R R R 1 0 1 0 C C C COPTIONAL EFFECTIVE ADDRESS EXTENSIONJMP ea23 16 15 87 00 0 0 0 1 0 1 0 1 1 M M M R R R 1 0 0 0 0 0 0 0OPTIONAL EFFECTIVE ADDRESS EXTENSION
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