section 7 - Index of

Table A-24 Program Control Unit Register EncodingE E Register0 0 MR Mode Register0 1 CCR Condition Code Register1 0 OMR Operating Mode Register1 1 - ReservedTable A-25 Condition Code and Address EncodingCodeCode Definitionecce 16 Condition Code Combinationsb bbbb 5-Bit Immediate Dataiiii iiii 8-Bit Immediate Data (int, trac, mask)iiii iiii xxxx hhhh 12-Bit Immediate Data (iiii iiii hhhh)aa aaaa 6-Bit Absolute Short (Low) Addresspp pppp 6-Bit Absolute I/O (High) Addressaaaa aaaa aaaa 12-Bit Fast Absolute Short (Low) AddressTable A-26 Effective Addressing Mode EncodingM2 M1 MO R2 R1 ROCode Definition0 0 0 r r r Post - N0 0 1 r r r Post + N0 1 0 r r r Post -10 1 1 r r r Post + 11 0 0 r r r No Update1 0 1 r r r Indexed + N1 1 1 r r r Pre - 11 1 0 0 0 0 Absolute Address1 1 0 1 0 0 Immediate DataMMM = three bits M2, M1, MO determine modeRRR = three bits R2, R1 , RO determine which address register number where rrr refers to thebinary representation of the numberNotes:(1) R2 is 0 for low register bank and 1 for the high register bank.(2) M2 is 0 for all post update modes and 1 otherwise.(3) M1 is 0 for update by register offset and no update and 1 otherwise.(4) MO is 0 for minus and 1 for plus, except for predecrement which is also 1.(5) For X:Y: parallel data moves, bits 14 and 13 of the opcode are a subset of the above RRRand are labelled rr. See the XY parallel data move description for a detailed explanation.(6) For X:Y: parallel data moves, bits 21 and 20 of the opcode are a subset of the above MMMand are labelled mm. See the XY parallel data move description for a detailed explanation-