section 7 - Index of
section 7 - Index of section 7 - Index of
Table A-20 Five-Bit Register Encodings for28 Registers in Data ALU and Address ALUe e e e eord d d d d0 0 0 0 X0 0 0 1 X0 0 1 D D0 1 D D D1 0 T T T1 1 N N NWhere: eeeee = sourceddddd = destinationDescriptionReservedReservedData ALU RegisterData ALU RegisterAddress ALU RegisterAddress Offset RegisterTable A-21 Six-Bit Register Encodingsfor 43 Registers On-Chipd d d d d d Description0 0 0 0 X X Reserved0 0 0 1 D D Data ALU Register0 0 1 D D D Data ALU Register0 1 0 T T T Address ALU Register0 1 1 N N N Address Offset Register1 0 0 F F F Address Modifier Register1 0 1 X X X Reserved1 1 0 X X X Reserved1 1 1 G G G Program Controller RegisterTable A-22 Write Control EncodingWOperation-0 Read Register or Peripheral1 Write Register or PeripheralTable A-23 Memory Space Bit EncodingS Operation0 X Memory1 Y Memory
Table A-24 Program Control Unit Register EncodingE E Register0 0 MR Mode Register0 1 CCR Condition Code Register1 0 OMR Operating Mode Register1 1 - ReservedTable A-25 Condition Code and Address EncodingCodeCode Definitionecce 16 Condition Code Combinationsb bbbb 5-Bit Immediate Dataiiii iiii 8-Bit Immediate Data (int, trac, mask)iiii iiii xxxx hhhh 12-Bit Immediate Data (iiii iiii hhhh)aa aaaa 6-Bit Absolute Short (Low) Addresspp pppp 6-Bit Absolute I/O (High) Addressaaaa aaaa aaaa 12-Bit Fast Absolute Short (Low) AddressTable A-26 Effective Addressing Mode EncodingM2 M1 MO R2 R1 ROCode Definition0 0 0 r r r Post - N0 0 1 r r r Post + N0 1 0 r r r Post -10 1 1 r r r Post + 11 0 0 r r r No Update1 0 1 r r r Indexed + N1 1 1 r r r Pre - 11 1 0 0 0 0 Absolute Address1 1 0 1 0 0 Immediate DataMMM = three bits M2, M1, MO determine modeRRR = three bits R2, R1 , RO determine which address register number where rrr refers to thebinary representation of the numberNotes:(1) R2 is 0 for low register bank and 1 for the high register bank.(2) M2 is 0 for all post update modes and 1 otherwise.(3) M1 is 0 for update by register offset and no update and 1 otherwise.(4) MO is 0 for minus and 1 for plus, except for predecrement which is also 1.(5) For X:Y: parallel data moves, bits 14 and 13 of the opcode are a subset of the above RRRand are labelled rr. See the XY parallel data move description for a detailed explanation.(6) For X:Y: parallel data moves, bits 21 and 20 of the opcode are a subset of the above MMMand are labelled mm. See the XY parallel data move description for a detailed explanation-
- Page 503 and 504: ROL Rotate Left ROLCondition Codes:
- Page 505 and 506: ROR Rotate Right RORCondition Codes
- Page 507 and 508: RTIReturn from InterruptRTIConditio
- Page 509 and 510: RTSReturn from SubroutineRTSInstruc
- Page 511 and 512: sec Subtract Long with Carry secExp
- Page 513 and 514: secSubtract Long with CarrysecInstr
- Page 515 and 516: STOPStop Instruction ProcessingSTOP
- Page 517 and 518: SUB Subtract SUBCondition Codes:S -
- Page 519 and 520: SUBL Shift Left and Subtract Accumu
- Page 521 and 522: SUBR Shift Right and Subtract Accum
- Page 523 and 524: SWISoftware InterruptSWICondition C
- Page 525 and 526: Tee Transfer Conditionally Teetion
- Page 527 and 528: Tee Transfer Conditionally TeeInstr
- Page 529 and 530: TFR Transfer Data ALU Register TFRC
- Page 531 and 532: TSTTest AccumulatorTSTInstruction F
- Page 533 and 534: WAIT Wait for Interrupt WAITConditi
- Page 535 and 536: including the number of words per i
- Page 537 and 538: 5. Compute final results.Thus, base
- Page 539 and 540: JLC (R2+N2)will requireand will exe
- Page 541 and 542: Table A-6 Instruction Timing Summar
- Page 543 and 544: Note that the "ap" term in Table A-
- Page 545 and 546: Table A-14 Memory Access Timing Sum
- Page 547 and 548: Other RestrictionsDO SSH,xxxxJSR to
- Page 549 and 550: Immediately before MOVEC from SSH o
- Page 551 and 552: A.9.S REP RestrictionsThe REP instr
- Page 553: Table A-18 Triple-Bit Register Enco
- Page 557 and 558: R: Register to Register Parallel Da
- Page 559 and 560: JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
- Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
- Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
- Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
- Page 567 and 568: LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
- Page 569 and 570: ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
- Page 571 and 572: Table A-28 Operation Code QQQ Decod
- Page 573 and 574: Table A-30 Special Case #10 P E R C
- Page 575 and 576: NEGD23 87 43 0DATA BUS MOVE FIELDLS
- Page 577: ADDRS,D23 87 43 oDATA BUS MOVE FIEL
- Page 580 and 581: lEI
- Page 582 and 583: Table 8-1 27-MHz Benchmark Results
- Page 584 and 585: .*._---*-----*-------**-------....
- Page 586 and 587: ;Latest Revision - September 30, 19
- Page 588 and 589: All coefficients are divided by 2:w
- Page 590 and 591: Real input FFT based on Glenn Bergl
- Page 592 and 593: countountcountcountorg y:coefset 0d
- Page 594 and 595: ; Real-Valued FFT for MOTOROLA DSP5
- Page 596 and 597: ; first group in the last passmove
- Page 599 and 600: A Accumulator ....... ' ...........
- Page 601 and 602: -H- fast ..........................
- Page 603 and 604: PGND ..............................
Table A-20 Five-Bit Register Encodings for28 Registers in Data ALU and Address ALUe e e e eord d d d d0 0 0 0 X0 0 0 1 X0 0 1 D D0 1 D D D1 0 T T T1 1 N N NWhere: eeeee = sourceddddd = destinationDescriptionReservedReservedData ALU RegisterData ALU RegisterAddress ALU RegisterAddress Offset RegisterTable A-21 Six-Bit Register Encodingsfor 43 Registers On-Chipd d d d d d Description0 0 0 0 X X Reserved0 0 0 1 D D Data ALU Register0 0 1 D D D Data ALU Register0 1 0 T T T Address ALU Register0 1 1 N N N Address Offset Register1 0 0 F F F Address Modifier Register1 0 1 X X X Reserved1 1 0 X X X Reserved1 1 1 G G G Program Controller RegisterTable A-22 Write Control EncodingWOperation-0 Read Register or Peripheral1 Write Register or PeripheralTable A-23 Memory Space Bit EncodingS Operation0 X Memory1 Y Memory