section 7 - Index of
section 7 - Index of section 7 - Index of
Section A.10.4 gives the encoding for the data ALU portion of those instructions whichallow parallel data moves. These a-bit partial instruction codes may be combined withthe 16-bit parallel move opcodes listed in Section A.10.1 to form a complete 24-bitinstruction word.A.10.1 Partial Encodings for Use in Instruction EncodingTable A-15 Single-Bit Register EncodingsCode d* e f Where:0 A XO YO d = 2 Accumulators in Data ALU1 B X1 Y1 e = 2 Registers in Data ALU• For class II encodings for R:Y and X:R, see Table A-16f = 2 Registers in Data ALUTable A-16 Single-Bit Special Register Encodingsd X:R Class II Opcode R:Y Class II Opcode0 A ~ X: XO ~ A YO ~ AA ~ Y:1 B ~ X: XO ~ B YO ~ B B ~ Y:Table A-17 Double-Bit Register EncodingsCode DD ee00 XO XO01 X1 X110 YO A11 Y1 BffYOY1ABWhere: DD = 4 registers in data ALUee = 4 XDS registers in data ALUff = 4 YDS registers in data ALU-
Table A-18 Triple-Bit Register EncodingsCode DDD LLL FFF NNN TTT GGG000 AO A10 MO NO RO *001 BO B10 M1 N1 R1 SR010 A2 X M2 N2 R2 OMR011 B2 Y M3 N3 R3 SP100 A1 A M4 N4 R4 SSH101 B1 B M5 N5 R5 SSL110 A AB M6 N6 R6 LA111 B BA M7 N7 R7 LC* ReservedWhere: DOD: 8 accumulators in data ALULLL: 8 extended-precision registers in data ALU; LLL field is encoded as LOLLFFF: 8 address modifier registers in address ALUNNN: 8 address offset registers in address ALUTTT: 8 address registers in addressFFF: 8 program controller registersTable A-19(a) Four-Bit Register Encodings for 12 Registers in Data ALUD D D D Description0 0 X X Reserved0 1 D D Data ALU Register1 D D D Data ALU RegisterTable A-19(b) Four-Bit Register Encodings for 16 Condition CodesMnemonic C C C C Mnemo'nic C C C cCC(HS) 0 0 0 0 CS(LO) 1 0 0 0GE 0 0 0 1 LT 1 0 0 1NE 0 0 1 0 EQ 1 0 1 0PL 0 0 1 1 MI 1 0 1 1NN 0 1 0 0 NR 1 1 0 0EC 0 1 0 1 ES 1 1 0 1LC 0 1 1 0 LS 1 1 1 0GT 0 1 1 1 LE 1 1 1 1
- Page 501 and 502: RNDRound AccumulatorRNDInstruction
- Page 503 and 504: ROL Rotate Left ROLCondition Codes:
- Page 505 and 506: ROR Rotate Right RORCondition Codes
- Page 507 and 508: RTIReturn from InterruptRTIConditio
- Page 509 and 510: RTSReturn from SubroutineRTSInstruc
- Page 511 and 512: sec Subtract Long with Carry secExp
- Page 513 and 514: secSubtract Long with CarrysecInstr
- Page 515 and 516: STOPStop Instruction ProcessingSTOP
- Page 517 and 518: SUB Subtract SUBCondition Codes:S -
- Page 519 and 520: SUBL Shift Left and Subtract Accumu
- Page 521 and 522: SUBR Shift Right and Subtract Accum
- Page 523 and 524: SWISoftware InterruptSWICondition C
- Page 525 and 526: Tee Transfer Conditionally Teetion
- Page 527 and 528: Tee Transfer Conditionally TeeInstr
- Page 529 and 530: TFR Transfer Data ALU Register TFRC
- Page 531 and 532: TSTTest AccumulatorTSTInstruction F
- Page 533 and 534: WAIT Wait for Interrupt WAITConditi
- Page 535 and 536: including the number of words per i
- Page 537 and 538: 5. Compute final results.Thus, base
- Page 539 and 540: JLC (R2+N2)will requireand will exe
- Page 541 and 542: Table A-6 Instruction Timing Summar
- Page 543 and 544: Note that the "ap" term in Table A-
- Page 545 and 546: Table A-14 Memory Access Timing Sum
- Page 547 and 548: Other RestrictionsDO SSH,xxxxJSR to
- Page 549 and 550: Immediately before MOVEC from SSH o
- Page 551: A.9.S REP RestrictionsThe REP instr
- Page 555 and 556: Table A-24 Program Control Unit Reg
- Page 557 and 558: R: Register to Register Parallel Da
- Page 559 and 560: JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
- Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
- Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
- Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
- Page 567 and 568: LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
- Page 569 and 570: ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
- Page 571 and 572: Table A-28 Operation Code QQQ Decod
- Page 573 and 574: Table A-30 Special Case #10 P E R C
- Page 575 and 576: NEGD23 87 43 0DATA BUS MOVE FIELDLS
- Page 577: ADDRS,D23 87 43 oDATA BUS MOVE FIEL
- Page 580 and 581: lEI
- Page 582 and 583: Table 8-1 27-MHz Benchmark Results
- Page 584 and 585: .*._---*-----*-------**-------....
- Page 586 and 587: ;Latest Revision - September 30, 19
- Page 588 and 589: All coefficients are divided by 2:w
- Page 590 and 591: Real input FFT based on Glenn Bergl
- Page 592 and 593: countountcountcountorg y:coefset 0d
- Page 594 and 595: ; Real-Valued FFT for MOTOROLA DSP5
- Page 596 and 597: ; first group in the last passmove
- Page 599 and 600: A Accumulator ....... ' ...........
- Page 601 and 602: -H- fast ..........................
Section A.10.4 gives the encoding for the data ALU portion <strong>of</strong> those instructions whichallow parallel data moves. These a-bit partial instruction codes may be combined withthe 16-bit parallel move opcodes listed in Section A.10.1 to form a complete 24-bitinstruction word.A.10.1 Partial Encodings for Use in Instruction EncodingTable A-15 Single-Bit Register EncodingsCode d* e f Where:0 A XO YO d = 2 Accumulators in Data ALU1 B X1 Y1 e = 2 Registers in Data ALU• For class II encodings for R:Y and X:R, see Table A-16f = 2 Registers in Data ALUTable A-16 Single-Bit Special Register Encodingsd X:R Class II Opcode R:Y Class II Opcode0 A ~ X: XO ~ A YO ~ AA ~ Y:1 B ~ X: XO ~ B YO ~ B B ~ Y:Table A-17 Double-Bit Register EncodingsCode DD ee00 XO XO01 X1 X110 YO A11 Y1 BffYOY1ABWhere: DD = 4 registers in data ALUee = 4 XDS registers in data ALUff = 4 YDS registers in data ALU-
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