section 7 - Index of
section 7 - Index of section 7 - Index of
additional (if any) instruction program words that are required for the effective address ofthe Jcc instruction. The term "jx" represents the number of additional (if any) oscillatorclock cycles required for a jump-type instruction.2. Evaluate the "jx" term using Table A-11.According to Table A-11, the Jcc instruction will require jx=ea+(2 * ap) additional oscillatorclock cycles. The term "ea" represents the number of additional (if any) oscillatorclock cycles that are required for the effective addressing mode specified in the Jccinstruction. The term "ap" represents the number of additional (if any) oscillator clockcycles that are required to access a P memory operand. Note that the "+(2 * ap)" termrepresents the two program memory instruction fetches executed at the end of a onewordjump instruction to refill the instruction pipeline.3. Evaluate the "ea" term using Table A-13.The JLC (R2+N2) instruction uses the "indexed by offset Nn" effective addressing mode.According to Table A-13, this operation will require ea=O additional instruction programwords and ea=2 additional oscillator clock cycles.4. Evaluate the "ap" term using Table A-14.According to Table A-14, the term "ap" depends upon where the referenced P memorylocation is located in the DSP56K memory space. External memory accesses requireadditional oscillator clock cycles according to the number of wait states programmed intothe DSP56K bus control register (8CR). Thus, assuming that the 16-bit bus control registercontains the value $2246, external P memory accesses require wp=4 wait states oradditional oscillator clock cycles. For this example, the P memory reference is assumedto be an external reference. Thus, according to Table A-14, the Jcc instruction will usethe value ap=wp=4 oscillator clock cycles.5. Compute final results.Thus, based upon the assumptions given for Table A-6 and those listed in the problemstatement for Example 2, the instruction-
JLC (R2+N2)will requireand will execute in= (1 +ea)= (1 +0)= 1= (4+jx)instruction program word= (4+ea+(2 * ap»= (4+ea+(2 * wp»= (4+2+(2 * 4» oscillator clock cycles.= 14Example 18: RTll!lstructionproblem: Calculate the number of 24-bit instruction program words and the number ofoscillator clock cycles required for the instructionRTIwhereOperating Mode Register (OMR)Sus Control Register (SCR)Return Address (on the stack)= 02 (normal expanded memory map),= $0012, and,= $0100 (internal P memory).Solution: To determine the number of instruction program words and the number ofoscillator clock cycles required for the given instruction, the user should perform the followingoperations:1. Look up the number of instruction program words and the number of oscillator clockcycles required for the opcode-operand portion of the instruction in Table A-6.According to Table A-6, the RTI instruction will require one instruction program word andwill execute in (4+rx) oscillator clock cycles. The term "rx" represents the number of additional(if any) oscillator clock cycles required for an RTI or RTS instruction.2. Evaluate the "rx" term using Table A-12.According to Table A-12, the RTI instruction will require rx=(2 * ap) additional oscillator-clock cycles. The term "ap" represents the number of additional (if any) oscillator clockcycles that are required to access a P memory operand. Note that the term "(2 * ap)" representsthe two program memory instruction fetches executed at the end of an RTI orRTS instruction to refill the instruction pipeline.
- Page 487 and 488: ORI OR Immediate with Control Regis
- Page 489 and 490: REP Repeat Next Instruction REPRest
- Page 491 and 492: REPRepeat Next InstructionREPInstru
- Page 493 and 494: REPRepeat Next InstructionREPInstru
- Page 495 and 496: REP Repeat Next Instruction REPNote
- Page 497 and 498: RESETReset On-Chip Peripheral Devic
- Page 499 and 500: RND Round Accumulator RNDConvergent
- Page 501 and 502: RNDRound AccumulatorRNDInstruction
- Page 503 and 504: ROL Rotate Left ROLCondition Codes:
- Page 505 and 506: ROR Rotate Right RORCondition Codes
- Page 507 and 508: RTIReturn from InterruptRTIConditio
- Page 509 and 510: RTSReturn from SubroutineRTSInstruc
- Page 511 and 512: sec Subtract Long with Carry secExp
- Page 513 and 514: secSubtract Long with CarrysecInstr
- Page 515 and 516: STOPStop Instruction ProcessingSTOP
- Page 517 and 518: SUB Subtract SUBCondition Codes:S -
- Page 519 and 520: SUBL Shift Left and Subtract Accumu
- Page 521 and 522: SUBR Shift Right and Subtract Accum
- Page 523 and 524: SWISoftware InterruptSWICondition C
- Page 525 and 526: Tee Transfer Conditionally Teetion
- Page 527 and 528: Tee Transfer Conditionally TeeInstr
- Page 529 and 530: TFR Transfer Data ALU Register TFRC
- Page 531 and 532: TSTTest AccumulatorTSTInstruction F
- Page 533 and 534: WAIT Wait for Interrupt WAITConditi
- Page 535 and 536: including the number of words per i
- Page 537: 5. Compute final results.Thus, base
- Page 541 and 542: Table A-6 Instruction Timing Summar
- Page 543 and 544: Note that the "ap" term in Table A-
- Page 545 and 546: Table A-14 Memory Access Timing Sum
- Page 547 and 548: Other RestrictionsDO SSH,xxxxJSR to
- Page 549 and 550: Immediately before MOVEC from SSH o
- Page 551 and 552: A.9.S REP RestrictionsThe REP instr
- Page 553 and 554: Table A-18 Triple-Bit Register Enco
- Page 555 and 556: Table A-24 Program Control Unit Reg
- Page 557 and 558: R: Register to Register Parallel Da
- Page 559 and 560: JSSETJSSET#n,X:pp,XXXX#n,Y:pp,xxxx2
- Page 561 and 562: JSSET#n,S,xxxx23 16 15 87 000001011
- Page 563 and 564: BCHGBCHG#n,X:aa#n,Y:aa23 16 15 87 0
- Page 565 and 566: MOVE(M)MOVE(M)S,P:aaP:aa,DREP #XXXR
- Page 567 and 568: LUAea,O23 16 15 87 0I 0 0 0 0 0 1 0
- Page 569 and 570: ENDDO23 16 15 87 00 0 0 0 0 0 0 o 1
- Page 571 and 572: Table A-28 Operation Code QQQ Decod
- Page 573 and 574: Table A-30 Special Case #10 P E R C
- Page 575 and 576: NEGD23 87 43 0DATA BUS MOVE FIELDLS
- Page 577: ADDRS,D23 87 43 oDATA BUS MOVE FIEL
- Page 580 and 581: lEI
- Page 582 and 583: Table 8-1 27-MHz Benchmark Results
- Page 584 and 585: .*._---*-----*-------**-------....
- Page 586 and 587: ;Latest Revision - September 30, 19
JLC (R2+N2)will requireand will execute in= (1 +ea)= (1 +0)= 1= (4+jx)instruction program word= (4+ea+(2 * ap»= (4+ea+(2 * wp»= (4+2+(2 * 4» oscillator clock cycles.= 14Example 18: RTll!lstructionproblem: Calculate the number <strong>of</strong> 24-bit instruction program words and the number <strong>of</strong>oscillator clock cycles required for the instructionRTIwhereOperating Mode Register (OMR)Sus Control Register (SCR)Return Address (on the stack)= 02 (normal expanded memory map),= $0012, and,= $0100 (internal P memory).Solution: To determine the number <strong>of</strong> instruction program words and the number <strong>of</strong>oscillator clock cycles required for the given instruction, the user should perform the followingoperations:1. Look up the number <strong>of</strong> instruction program words and the number <strong>of</strong> oscillator clockcycles required for the opcode-operand portion <strong>of</strong> the instruction in Table A-6.According to Table A-6, the RTI instruction will require one instruction program word andwill execute in (4+rx) oscillator clock cycles. The term "rx" represents the number <strong>of</strong> additional(if any) oscillator clock cycles required for an RTI or RTS instruction.2. Evaluate the "rx" term using Table A-12.According to Table A-12, the RTI instruction will require rx=(2 * ap) additional oscillator-clock cycles. The term "ap" represents the number <strong>of</strong> additional (if any) oscillator clockcycles that are required to access a P memory operand. Note that the term "(2 * ap)" representsthe two program memory instruction fetches executed at the end <strong>of</strong> an RTI orRTS instruction to refill the instruction pipeline.