section 7 - Index of

additional (if any) instruction program words that are required for the effective address ofthe Jcc instruction. The term "jx" represents the number of additional (if any) oscillatorclock cycles required for a jump-type instruction.2. Evaluate the "jx" term using Table A-11.According to Table A-11, the Jcc instruction will require jx=ea+(2 * ap) additional oscillatorclock cycles. The term "ea" represents the number of additional (if any) oscillatorclock cycles that are required for the effective addressing mode specified in the Jccinstruction. The term "ap" represents the number of additional (if any) oscillator clockcycles that are required to access a P memory operand. Note that the "+(2 * ap)" termrepresents the two program memory instruction fetches executed at the end of a onewordjump instruction to refill the instruction pipeline.3. Evaluate the "ea" term using Table A-13.The JLC (R2+N2) instruction uses the "indexed by offset Nn" effective addressing mode.According to Table A-13, this operation will require ea=O additional instruction programwords and ea=2 additional oscillator clock cycles.4. Evaluate the "ap" term using Table A-14.According to Table A-14, the term "ap" depends upon where the referenced P memorylocation is located in the DSP56K memory space. External memory accesses requireadditional oscillator clock cycles according to the number of wait states programmed intothe DSP56K bus control register (8CR). Thus, assuming that the 16-bit bus control registercontains the value $2246, external P memory accesses require wp=4 wait states oradditional oscillator clock cycles. For this example, the P memory reference is assumedto be an external reference. Thus, according to Table A-14, the Jcc instruction will usethe value ap=wp=4 oscillator clock cycles.5. Compute final results.Thus, based upon the assumptions given for Table A-6 and those listed in the problemstatement for Example 2, the instruction-